`
`Godo Kaisha IP Bridge I
`
`Plaintiff,
`
`
`v.
`
`Micron Technology, Inc.;
`Micron Semiconductor Products, Inc.; and
`Micron Technology Texas, LLC
`
`
`
`
`
`
`Civil Action No. 6:20-cv-00178-ADA
`
`JURY TRIAL DEMANDED
`
`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 1 of 43
`
`
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`Defendants.
`
`
`IP BRIDGE’S OPENING MARKMAN BRIEF
`
`
`
`
`
`
`
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 2 of 43
`
`
`
`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES ......................................................................................................... iii
`TABLE OF EXHIBITS .................................................................................................................. v
`AGREED CLAIM CONSTRUCTIONS ...................................................................................... vii
`DISPUTED CLAIM CONSTRUCTIONS .................................................................................. viii
`I.
`INTRODUCTION .............................................................................................................. 1
`II.
`LEGAL STANDARD ......................................................................................................... 2
`III.
`LEVEL OF ORDINARY SKILL IN THE ART ................................................................ 3
`IV.
`U.S. PATENT NO. 6,424,041 (CLAIMS 1-5 AND 13-14) ............................................... 3
`A.
`Overview of the ’041 Patent ................................................................................. 3
`B.
`Claim 1 of the ’041 Patent .................................................................................... 6
`C.
`“copper-diffusion blocking means” (claims 1-5) ................................................. 6
`D.
`“memory storage portion” (claims 1-2, 5, and 13-14) ......................................... 9
`E.
`“apart from said memory storage portion” (claim 1) ......................................... 12
`F.
`“provided in a region surrounding the memory storage portion” (claim 1) ....... 13
`U.S. PATENT NO. 6,445,047 (CLAIMS 1-2 AND 4)..................................................... 14
`A.
`Overview of the ’047 Patent ............................................................................... 14
`B.
`Claim 1 of the ’047 Patent .................................................................................. 16
`C.
`“surface-channel-type MOSFET” (claims 1-2 and 4) ........................................ 16
`U.S. PATENT NO. 7,189,616 (CLAIM 1) ....................................................................... 18
`A.
`Overview of the ’616 Patent ............................................................................... 18
`B.
`Claim 1 of the ’616 Patent .................................................................................. 19
`C.
`“forming a plate electrode on the capacitor insulating film” (claim 1) .............. 20
`D.
`“wherein the length of a portion where the opposing capacitors are overlapped
`in the mask layout is set so that the value of the parasitic capacitance between
`adjacent cell capacitors is not more than 10% of the set cell capacitance value”
`(claim 1) ............................................................................................................. 21
`VII. U.S. PATENT NO. 6,747,320 (CLAIM 1) ....................................................................... 23
`A.
`Overview of the ’320 Patent ............................................................................... 23
`B.
`Claim 1 of the ’320 Patent .................................................................................. 25
`C.
`“a DRAM region and a high-speed CMOS logic region that are co-resident with
`each other” (claim 1) .......................................................................................... 25
`“sense amplifier transistor” (claim 1) ................................................................. 27
`
`V.
`
`VI.
`
`D.
`
`
`
`
`i
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 3 of 43
`
`E.
`
`“a N-type sense amplifier transistor and … a P-type sense amplifier transistor
`constituting a CMOS sense amplifier” (claim 1) ............................................... 28
`“parallel” (claim 1) ............................................................................................. 29
`F.
`VIII. CONCLUSION ................................................................................................................. 30
`
`
`
`
`
`
`
`
`
`ii
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 4 of 43
`
`TABLE OF AUTHORITIES
`
`Cases
`
`Page
`
`Acumed LLC v. Stryker Corp.,
` 483 F.3d 800 (Fed. Cir. 2007).............................................................................................. 2, 29
`
`Global-Tech Appliances, Inc. v. SEB S.A.,
` 563 U.S. 754 (2011) ................................................................................................................. 22
`
`Hill-Rom Services, Inc. v. Stryker Corp.,
` 755 F.3d 1367 (Fed. Cir. 2014)................................................................................ 3, 23, 26, 28
`
`Hoganas AB v. Dresser Indus., Inc.,
` 9 F.3d 948 (Fed. Cir. 1993)...................................................................................................... 21
`
`Liquid Dynamics Corp. v. Vaughan Co., Inc.,
` 355 F.3d 1361 (Fed. Cir. 2004).................................................................................................. 2
`
`Markman v. Westview Instruments, Inc.,
` 52 F.3d 967 (Fed. Cir. 1995), aff’d, 517 U.S. 370 (1996) ......................................................... 2
`
`Omega Eng’g, Inc. v. Raytek Corp.,
` 334 F.3d 1314 (Fed. Cir. 2003)................................................................................................ 13
`
`Paltalk Holdings, Inc. v. Microsoft Corp.,
` 2008 WL 4830571 (E.D. Tex. July 29, 2008) ................................................................... 13, 14
`
`Paragon Sols., LLC v. Timex Corp.,
` 566 F.3d 1075 (Fed. Cir. 2009)................................................................................................ 17
`
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005).................................................................................................. 2
`
`SciMed Life Sys., Inc. v. Adv. Cardiovascular Sys., Inc.,
` 242 F.3d 1337 (2001) ......................................................................................................... 20, 26
`
`Sensor Elec. Tech., Inc. v. Bolb, Inc.,
` No. 18-cv-05194-LHK, 2019 WL 4645338 (N.D. Cal. Sept. 24, 2019) ................................. 17
`
`Teleflex, Inc. v. Ficosa N. Am. Corp.,
` 299 F.3d 1313 (Fed. Cir. 2002)................................................................................................ 20
`
`Thorner v. Sony Computer Entm’t Am. LLC,
` 669 F.3d 1362 (Fed. Cir. 2012).................................................................................................. 3
`
`Vitronics Corp. v. Conceptronic Inc.,
` 90 F.3d 1576 (Fed. Cir. 1996).................................................................................. 2, 21, 23, 29
`
`
`
`
`iii
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 5 of 43
`
`Rules / Statutes
`
`35 U.S.C. § 112 ............................................................................................................................... 7
`
`
`
`
`
`
`
`
`
`iv
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 6 of 43
`
`
`
`Exhibit
`Number
`
`TABLE OF EXHIBITS
`
`Description
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`U.S. Patent No. 6,424,041 (the ’041 Patent)
`
`U.S. Patent No. 6,445,047 (the ’047 Patent)
`
`U.S. Patent No. 7,189,616 (the ’616 Patent)
`
`U.S. Patent No. 6,747,320 (the ’320 Patent)
`
`Declaration of Dr. Kelin Kuhn Regarding U.S. Patent Nos. 6,424,041 and
`6,445,047 (Kuhn Declaration)
`
`Declaration of Dr. Konstantinos P. Giapis Regarding U.S. Patent Nos.
`7,189,616 and 6,747,320 (Giapis Declaration)
`
`Petition for Inter Partes Review of U.S. Patent No. 6,424,041, IPR2020-
`01007, IPB-MICRON-00005970 (’041 IPR Petition)
`
`Newton’s Telecom Dictionary (14th Ed. 1998), IPB-MICRON-00007241
`
`U.S. Patent No. 6,021,063 (Tai), IPB-MICRON-00007232
`
`U.S. Patent No. 3,387,286 (Dennard), IPB-MICRON-00007223
`
`Baker et al., DRAM Circuit Design – A Tutorial, IEEE Press Series on
`Microelectronic Systems (Tewksbury & Brewer ed., 2001), IPR2020-01008,
`Ex. 1018 (Baker ’047), IPR-MICRON-00008161
`
`Petition for Inter Partes Review of U.S. Patent No. 6,445,047, IPR2020-
`01008, IPB-MICRON-00007443 (’047 IPR Petition)
`
`Declaration of Dr. Bravman, IPR2020-01008, IPB-MICRON-00007742
`(Bravman Decl., ’047 IPR)
`
`Merriam-Webster’s Collegiate Dictionary, 10th Edition (1999), IPB-
`MICRON-00005964
`
`John Y. Chen, CMOS Devices and Technology for VLSI (1990) (Chen), IPB-
`MICRON-00007934
`
`U.S. Patent No. 5,763,921 (Okumura)
`
`
`
`
`v
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 7 of 43
`
`Exhibit
`Number
`
`17
`
`18
`
`19
`
`20
`
`Description
`
`Yannis Tsividis, Operation and Modeling of The MOS Transistor (1999)
`(Tsividis), IPB-MICRON-00005097
`
`Application No. 10/756,961, October 16, 2006 Amendment and Remarks (Oct.
`16, 2006 Amendment)
`
`Petition for Inter Partes Review of U.S. Patent No. 6,747,320, IPR2020-
`01009, IPB-MICRON-00009184 (’320 IPR Petition)
`
`Baker et al., DRAM Circuit Design – A Tutorial, IEEE Press Series on
`Microelectronic Systems (Tewksbury & Brewer ed., 2001), IPR2020-01009,
`Ex. 1012 (Baker ’320), IPR-MICRON-00009948
`
`
`
`vi
`
`
`
`
`
`
`
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 8 of 43
`
`AGREED CLAIM CONSTRUCTIONS
`
`Claim
`
`616:1
`
`Term
`
`Agreed Construction
`
`side edges of the adjacent hole patterns
`
`Plain meaning
`
`
`
`vii
`
`
`
`
`
`
`
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 9 of 43
`
`DISPUTED CLAIM CONSTRUCTIONS
`
`Claim
`
`Term
`
`Proposer
`
`IPB’s Construction
`
`Micron’s
`Construction
`
`041:
`1-5
`
`copper-diffusion
`blocking means
`
`Both
`
`Function: “blocking copper diffusion from said
`wiring portion toward said memory storage
`portion”
`
`Structure: “a ceiling
`film or a vertical wall
`as shown in Figs. 1, 19,
`20, or 21.”
`
`“the region where at
`least the components
`that are used for the
`storage of information
`are located”
`
`“not a part of or a
`component of the
`memory storage
`portion”
`
`“located in a region
`that surrounds, and
`does not include, the
`memory storage
`portion”
`
`Structure: a film
`composed of a material
`such as tungsten,
`aluminum, silicon
`nitride, tantalum, and
`tantalum nitride that
`reliably blocks diffusion
`of copper. Col. 5:45-58,
`2:56-3:8, 3:43-50, 4:4-
`5:25, 7:25-8:14, 8:61-
`9:46; Figs. 1, 14-21.
`
`a portion of a
`semiconductor device
`that includes at least a
`storage element (e.g., a
`capacitor) and access
`circuitry (e.g., a
`transistor) that together
`form a memory
`
`a memory storage
`portion
`
`IPB
`
`041:
`1-2,
`5,
`13-14
`
`041:1
`
`apart from said
`memory storage
`portion
`
`Micron No construction
`necessary for “apart
`from”
`
`041:1 provided in a region
`surrounding the
`memory storage
`portion
`
`Micron No construction
`necessary for “provided
`in a region surrounding”
`
`
`
`viii
`
`
`
`
`
`
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 10 of 43
`
`Claim
`
`Term
`
`Proposer
`
`IPB’s Construction
`
`047:
`1-2, 4
`
`surface-channel-type
`MOSFET
`
`Micron
`
`Plain meaning
`
`Claim
`
`616:1
`
`Term
`
`Proposer
`
`IPB’s Construction
`
`Micron
`
`Plain meaning
`
`forming a plate
`electrode on the
`capacitor insulating
`film
`
`Micron
`
`Plain meaning
`
`616:1 wherein the length
`of a portion where
`the opposing
`capacitors are
`overlapped in the
`mask layout is set so
`that the value of the
`parasitic capacitance
`between adjacent
`cell capacitors is not
`more than 10% of
`the set cell
`capacitance value
`
`
`
`Micron’s
`Construction
`
`“a MOSFET (metal-
`oxide-semiconductor-
`field-effect-transistor)
`in which the channel
`forms near the top
`surface of the
`semiconductor
`substrate”
`
`Micron’s
`Construction
`“the plate electrode is
`formed on the capacitor
`insulating film so that
`the plate electrode does
`not cover any portion
`of the outer surface of
`the storage node”
`“wherein the length of
`a portion where the
`opposing capacitors are
`overlapped in the mask
`layout is designed to
`reduce the value of the
`parasitic capacitance
`between adjacent cell
`capacitors and to
`prevent the parasitic
`capacitance from
`exceeding 10% of the
`set cell capacitance”
`
`ix
`
`
`
`
`
`
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 11 of 43
`
`Claim
`
`Claim Term
`
`Proposer
`
`Micron
`
`320:1
`
`a DRAM region and
`a high-speed CMOS
`logic region that are
`co-resident with each
`other
`
`IPB’s
`Construction
`Plain meaning
`
`320:1
`
`sense amplifier
`transistor
`
`Micron
`
`Plain meaning
`
`Micron
`
`Plain meaning
`
`320:1
`
`a N-type sense
`amplifier transistor
`and … a P-type sense
`amplifier transistor
`constituting a CMOS
`sense amplifier
`
`320:1
`
`parallel
`
`Micron
`
`Plain meaning
`
`Micron’s Construction
`
`“embedded DRAM that
`includes a DRAM region
`and a high-speed CMOS
`logic region that is
`separate from and not part
`of the DRAM region on
`the same device”
`“a transistor that senses
`and amplifies the signal
`voltage on the bit lines
`during cell access”
`“the CMOS sense
`amplifier is formed from
`an N-type sense amplifier
`transistor and a P-type
`sense amplifier transistor
`that are interconnected to,
`and cooperate with, each
`other to sense and amplify
`the signal voltage on the
`bit lines”
`“side by side and having
`the same distance
`continuously between
`them”
`
`
`
`
`
`
`
`x
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 12 of 43
`
`I.
`
`INTRODUCTION
`
`IP Bridge’s complaint asserts four patents that are particularly useful for manufacturing
`
`smaller, faster, and more reliable semiconductor devices, such as DRAM chips1: For these four
`
`patents, there are 11 disputed terms. The first term “copper-diffusion blocking means” is a means-
`
`plus-function term from the ’041 Patent; the second term “memory storage portion” is at issue in
`
`Micron’s IPR petition for the ’041 Patent; and the nine remaining terms were identified by Micron.
`
`The parties agree the term “copper-diffusion blocking means” should be construed as a
`
`means-plus-function term, and also agree on the recited function; the only dispute is the
`
`corresponding structure. IP Bridge’s construction identifies the “barrier films” that perform the
`
`recited function. Micron’s construction, on the other hand, limits the structure to particular figures,
`
`ignoring the disclosure of the corresponding structure in the specification.
`
`The term “memory storage portion” should be construed to mean the portion of a chip that
`
`is memory storage. IP Bridge’s construction sets forth the plain meaning of “memory storage
`
`portion” within the context of the claim as a whole. Micron’s construction, however, seeks to use
`
`the term “portion” to rewrite the term to include vague “components” that may form part of
`
`memory storage, but that would not be considered by a person of ordinary skill in the art
`
`(“POSITA”) to be “memory storage.”
`
`The nine remaining terms should be given their plain meaning and do not require
`
`construction. The term “surface-channel-type MOSFET,” for example, is a term of art readily
`
`understood by a POSITA. For other terms, like “apart from” or “parallel,” they are everyday words
`
`that are readily understood by POSITAs and lay people alike. Micron’s proposed constructions
`
`depart from the ordinary meaning and the intrinsic record, often introducing ambiguity that fails
`
`to offer an alternative meaning that would assist a jury in understanding the scope and meaning of
`
`
`1 “DRAM” stands for Dynamic Random-Access Memory.
`
`1
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 13 of 43
`
`the claim. Additionally, Micron’s constructions contain unwarranted “negative limitations,” such
`
`as: “does not include”; “do not cover any portion”; and “not part of the DRAM region.” Micron
`
`cannot, however, meet the high-bar that is required for these negative limitations to be proper.
`
`There was no “clear disavowal, disclaimer, or estoppel” in the intrinsic record; instead, the intrinsic
`
`record confirms that the applicable terms should be given the full scope of their plain meaning.
`
`For these reasons, IP Bridge’s proposed constructions should be adopted.
`
`II.
`
`LEGAL STANDARD
`
`Claim construction is a matter of law to be determined by the Court. Markman v. Westview
`
`Instruments, Inc., 52 F.3d 967, 979 (Fed. Cir. 1995) (en banc), aff’d, 517 U.S. 370 (1996). “It is
`
`well-settled that, in interpreting an asserted claim, the court should look first to the intrinsic
`
`evidence of record, i.e., the patent itself, including the claims, the specification and, if in evidence,
`
`the prosecution history. Such intrinsic evidence is the most significant source of the legally
`
`operative meaning of disputed claim language.” Liquid Dynamics Corp. v. Vaughan Co., Inc., 355
`
`F.3d 1361, 1367 (Fed. Cir. 2004) (quoting Vitronics Corp. v. Conceptronic Inc., 90 F.3d 1576,
`
`1582 (Fed. Cir. 1996)). In addition to intrinsic evidence, a court may rely on extrinsic evidence,
`
`such as dictionaries and treatises, to shed light on the claimed technology, although such evidence
`
`is “less significant than the intrinsic record.” Phillips v. AWH Corp., 415 F.3d 1303, 1317-18 (Fed.
`
`Cir. 2005) (en banc) (internal citations omitted).
`
`When construing claims, the Court must begin by “look[ing] to the words of the claims
`
`themselves . . . to define the scope of the patented invention.” Vitronics, 90 F.3d at 1582. “The
`
`task of comprehending those words is not always a difficult one. In some cases, the ordinary
`
`meaning of claim language as understood by a person of skill in the art may be readily apparent
`
`even to lay judges, and claim construction in such cases involves little more than the application
`
`of the widely accepted meaning of commonly understood words. Acumed LLC v. Stryker Corp.,
`
`
`
`
`2
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 14 of 43
`
`483 F.3d 800, 805 (Fed. Cir. 2007) (quotations omitted).
`
`While claims are read in view of the specification, the specification should not be used to
`
`limit the claim absent lexicography or disavowal. Hill-Rom Services, Inc. v. Stryker Corp., 755
`
`F.3d 1367, 1371-72 (Fed. Cir. 2014). The standards for these two exceptions are exacting. Id.
`
`“To act as its own lexicographer, a patentee must clearly set forth a definition of the disputed claim
`
`term other than its plain and ordinary meaning” and must “clearly express an intent to redefine the
`
`term.” Id. (quoting Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir.
`
`2012). Disavowal requires that the intrinsic record makes clear that the invention does not include
`
`a particular feature, or is clearly limited to a particular form of the invention. Id.
`
`III. LEVEL OF ORDINARY SKILL IN THE ART
`
`A person of ordinary skill in the art in the field of the ’041, ’047, ’616, and ’320 patents
`
`would have had a degree in electrical engineering, physics, materials science, or a similar
`
`discipline, along with two years of experience in the development, design, or implementation of
`
`semiconductor devices. A more advanced degree can substitute for work experience. A person of
`
`ordinary skill in the art would be aware of and generally knowledgeable about the structure and
`
`operation of DRAM.
`
`IV. U.S. PATENT NO. 6,424,041 (CLAIMS 1-5 AND 13-14)
`
`A.
`
`Overview of the ’041 Patent
`
`The ’041 Patent enables smaller, faster, and more reliable DRAM chips by efficiently
`
`keeping harmful copper out of the memory storage portion of the chip.2 Ex. 1, 1:5-9. Copper
`
`wiring is frequently used in smaller, faster semiconductor devices because it is an excellent
`
`conductor with low electrical resistance that can be formed into thin wire. Id., 1:18-34. Copper
`
`
`2 For brevity purposes, the memory storage portion of the chip is sometimes referred to as the
`memory portion of the chip, or simply the memory.
`
`3
`
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 15 of 43
`
`wiring presents challenges, however. Copper atoms readily diffuse from the copper wiring into
`
`the surrounding materials, and this diffusion can cause malfunctions. Id., 1:35-40. For example,
`
`in DRAM chips, the copper can diffuse into the DRAM’s capacitors and destroy their ability to
`
`store information. Id., 2:12-21.
`
`The logical solution would be to wrap (or coat) the copper wires with a “barrier film” to
`
`keep the copper from diffusing. Ex. 1, 1:41-2:8 (discussing background prior art). This approach
`
`does not work, however, in smaller DRAMs because the copper atoms can still get through the
`
`film, and even a small number of copper atoms can destroy the DRAM’s capacitors. Id., 2:9-16.
`
`Instead of wrapping the copper wiring, the ’041 invention takes the counter-intuitive approach of
`
`surrounding the “memory storage portion” of the chip with a barrier film. Id., 2:56-63. By doing
`
`so, the ’041 invention allows the copper atoms to escape the copper wire into the surrounding
`
`materials and diffuse towards the memory. But by the time the copper atoms arrive at the barrier
`
`film, the “driving force” for diffusion of the copper atoms has diminished, and the copper atoms
`
`cannot get into the memory potion of the chip. Id., 2:64-3:8.
`
`In the “Summary of the Invention,” the ’041 Patent refers to the barrier film as a “copper
`
`diffusion blocking means.” Ex. 1, 2:60, 67 et seq. At the end of the Summary, the ’041 Patent
`
`further explains that the “copper-diffusion preventing film forming the copper-diffusion blocking
`
`means may be, for example, any one of a tungsten film, an aluminum film, a silicon nitride film, a
`
`tantalum film and a tantalum nitride film.” It is a film formed from these disclosed materials that
`
`blocks the copper atoms that are diffusing from the copper wires toward the memory.
`
`Armed with this understanding, the ’041 Patent provides four exemplary embodiments of
`
`how these films (i.e., the identified “copper-diffusion blocking means”) may be “provided in a
`
`region surrounding the memory storage portion” of the chip. The first embodiment is shown in
`
`Figure 1, which is reproduced below.
`
`
`
`
`4
`
`

`

`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 16 of 43
`
`
`
`The “memory storage portion” of the chip, which is referred to as the “memory cell
`
`portion” of the chip, is shown on the left-hand side of the figure as reference numeral 30. This
`
`portion of the chip (highlighted yellow) has capacitors (red) and transistors (blue) that work
`
`together to store information in memory.
`
`The copper wiring is shown in orange. The copper-diffusion blocking film is shown in
`
`green. This film is “provided in a region surrounding the memory storage portion” of the chip.
`
`Importantly, as the copper atoms diffuse from the copper wiring towards the barrier film, they
`
`cannot get into the memory cell and damage its capacitors and transistors.
`
`In this first embodiment, the copper-diffusion blocking means is a silicon nitride film, Ex.
`
`1, 7:24-26, and a tungsten film, id., 7:43-45. These films are “provided in a region surrounding
`
`the memory storage portion” as a ceiling film, id., 7:24-25, and a vertical wall, id., 7:39-45,
`
`respectively. The silicon-nitride ceiling film is shown as reference numeral 14. The tungsten wall
`
`films are shown as reference numerals 13b and 9b. The second embodiment is shown in Fig. 19.
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`It is similar to the first embodiment, except that both the ceiling films and wall films are silicon
`
`nitride films. Id., 9:4-11. In the third embodiment (shown in Fig. 20), the ceiling film is an
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`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 17 of 43
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`aluminum film, and the wall film is a tungsten film. Id., 9:14-22. The fourth embodiment (shown
`
`in Fig. 21) is different from the previous three embodiments. In the first three embodiments, there
`
`is a ceiling film and a wall film. In the fourth embodiment, one of the films is eliminated, such
`
`that there is only a ceiling film or a wall film, but not both. Id., 9:26-28 (eliminating wall films);
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`9:39-46 (eliminating ceiling film).
`
`B.
`
`Claim 1 of the ’041 Patent
`
`Turning to claim 1 of the ’041 Patent, it is easy to see how it tracks Fig. 1 of the ’041
`
`Patent. The preamble of the claim is directed to a semiconductor device, such as a DRAM chip.
`
`The semiconductor device has both a memory storage portion and a wiring portion.
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`1. A semiconductor device, comprising:
`
`a semiconductor substrate,
`
`a memory storage portion on a main surface of said semiconductor substrate,
`
`a wiring portion including a copper wire positioned on the main surface of said
`semiconductor substrate and apart from said memory storage portion, and
`
`copper-diffusion blocking means provided in a region surrounding the memory
`storage portion for blocking copper diffusion from said wiring portion toward said
`memory storage portion.3
`
`C.
`
`“copper-diffusion blocking means” (claims 1-5)
`
`Term
`
`copper-
`diffusion
`blocking
`means
`
`IPB’s Construction
`
`Micron’s Construction
`
`Function: “blocking copper diffusion from said wiring portion toward said
`memory storage portion”
`
`Structure: a film composed of a material such
`as tungsten, aluminum, silicon nitride,
`tantalum, and tantalum nitride that reliably
`blocks diffusion of copper. Col. 5:45-58, 2:56-
`3:8, 3:43-50, 4:4-5:25, 7:25-8:14, 8:61-9:46;
`Figs. 1, 14-21.
`
`Structure: a ceiling film
`or a vertical wall as shown
`in Figs. 1, 19, 20, or 21.
`
`
`3 The color coding in the claim corresponds to the color coding in Figure 1 above
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`6
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`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 18 of 43
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`There is no dispute that this term invokes 35 U.S.C. § 112, ¶ 6, and that the recited function
`
`is “blocking copper diffusion from said portion toward said memory storage portion.” The only
`
`dispute is regarding the corresponding structure disclosed in the ’041 Patent for performing this
`
`function. IP Bridge’s proposed construction captures the specific structures disclosed in the
`
`specification for performing the function of “blocking copper diffusion from said wiring portion
`
`toward said memory storage portion.”
`
`When construing a means-plus-function term, the Court is tasked with identifying the
`
`corresponding structures that perform the claimed function. See B. Braun Med., 124 F.3d at 1424.
`
`“[S]tructure disclosed in the specification is ‘corresponding' structure only if the specification or
`
`prosecution history clearly links or associates that structure to the function recited in the claim.”
`
`Id. Here, the patent expressly discloses that the “copper-diffusion blocking means” is formed by
`
`specific “copper-diffusion preventing film(s)” that “can reliably block diffusion of copper atoms”:
`
`In the semiconductor device of the present invention, each copper-diffusion
`preventing film forming the copper-diffusion blocking means may be, for
`example, any one of a tungsten film, an aluminum film, a silicon nitride film, a
`tantalum film and a tantalum nitride film.
`
`These films can reliably block diffusion of copper atoms, and have been
`actually formed in the manufacturing process of the semiconductor devices.
`
`Ex. 1, 5:45-52; see also 4:57-59 (“the copper-diffusion blocking means is, for example, a copper-
`
`diffusion preventing film.”). These disclosed films (identified as the claimed “means”) are
`
`expressly linked to performance of the recited function of “blocking copper diffusion from said
`
`wiring portion toward said memory storage portion.” As a result, the proper construction of this
`
`term must identify these films as the corresponding structure, as IP Bridge’s construction does.
`
`Micron’s proposed construction fails to clearly link or associate the identified structure to
`
`the function recited in the claim: “blocking copper diffusion from said wiring portion toward said
`
`memory storage portion.” The proposed generic “ceiling film” or “vertical wall” shown in Figs.
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`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 19 of 43
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`1, 19, 20, or 21 of the patent does not address the recited function. The patent clearly describes a
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`film formed from disclosed materials that “can reliably block diffusion of copper atoms” as
`
`performing the recited function; no particular shape or configuration of the film is required by the
`
`phrase “copper-diffusion blocking means.”
`
`Furthermore, the Summary of the Invention repeatedly states that the “copper-diffusion
`
`blocking means” (“CDBM”) is provided in a region surrounding the memory storage portion, and
`
`that it can be located on a top-surface region, a side-surface region, or both. The summary of the
`
`invention never says that these regions must be a “ceiling film” or a “vertical wall.” Ex. 1, 2:59-
`
`64, 2:67-3:8; 3:54-56; 4:4-13; 4:15-18; 4:25-29; 4:34-38 (“cover whole range of the region . . . [or]
`
`part of the region, as far as it blocks copper diffusion to the memory storage portion”); 4:42-44
`
`(“can be located, for example, across a whole region of both the top-surface region and the side-
`
`surface region); 4:45-47; 4:65-67 (“may be formed as a vertical wall . . . at an angle to the
`
`semiconductor substrate”); 5:3-6 (“extend in parallel with a surface of the semiconductor
`
`substrate”). Moreover, the specification is explicit that the CDBM can cover all or part of a region.
`
`In the latter case, the film may look different from the ceiling films and vertical walls shown in
`
`the figures. Thus, the patent makes clear that the blocking of copper-diffusion is focused on the
`
`types of films used—i.e., films made from materials that “can reliably block diffusion of copper
`
`atoms—and not their location or orientation, other than generally to be in a region surrounding a
`
`memory storage portion of the device.
`
`Finally, Micron’s proposed construction of a ceiling film or vertical wall as corresponding
`
`structure excludes three embodiments where the copper-diffusion blocking film is formed into a
`
`ceiling film and a vertical wall. Ex. 1, 7:1-9:22. Only in the fourth embodiment is the film formed
`
`into just a ceiling film, or just a vertical wall. Id., 9:23-47. Therefore, Micron’s construction
`
`improperly excludes the first three embodiments.
`
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`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 20 of 43
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`D.
`
`“memory storage portion” (claims 1-2, 5, and 13-14)
`
`Term
`
`IPB’s Construction
`
`Micron’s Construction
`
`a memory storage
`portion
`
`a portion of a semiconductor device that
`includes at least a storage element (e.g.,
`a capacitor) and access circuitry (e.g., a
`transistor) that together form a memory
`
`the region where at least
`the components that are
`used for the storage of
`information are located
`
`This claim recites a “memory storage portion” of the claimed “semiconductor device.” IP
`
`Bridge’s construction is consistent with the intrinsic evidence and the understanding of a POSITA.
`
`Starting with the claims, claim 1 is directed to a semiconductor device (e.g., a chip) with a
`
`semiconductor substrate. Ex. 1, 9:54-55. On this substrate, there is a “memory storage portion”
`
`and a “wiring portion” of the semiconductor device (e.g., a DRAM chip). The word “portion” in
`
`claim 1 is a reference to part of the chip, not part of the memory storage or wiring. In other
`
`words, the “memory storage portion” has the necessary circuitry to operate as a memory, as
`
`opposed to a single capacitor that is unable to store information without additional help.
`
`The specification confirms that the “memory storage portion” “includes a memory cell
`
`portion of the DRAM.” Ex. 1, 5:31-33. Throughout the specification, the two terms “memory
`
`storage” and “memory cell” are used interchangeably. See, e.g., id., 3:28-29 (“in a memory cell
`
`portion, i.e., in the memory storage portion”); 7:3-12 (“a memory cell portion 30, i.e., a memory
`
`storage region”). As shown in Fig. 1, the memory cell (highlighted yellow) includes both
`
`capacitors and transistors.
`
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`9
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`Case 6:20-cv-00178-ADA Document 59 Filed 09/25/20 Page 21 of 43
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`
`
`In Fig. 1, t