Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 1 of 35
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`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`GODO KAISHA IP BRIDGE 1,
`
`Plaintiff,
`
`v.
`
`MICRON TECHNOLOGY, INC., MICRON
`SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS, LLC,
`
`Defendants.
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`C.A. No. 6:20-cv-178-ADA
`
`JURY TRIAL DEMANDED
`
`MICRON’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
`
`
`
`Jared Bobrow (CA State Bar No. 133712)
`Jason Lang (CA State Bar No. 255642)
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`Tel: (650) 614-7400
`Fax: (650) 614-7401
`jbobrow@orrick.com
`jlang@orrick.com
`
`Claudia Wilson Frost
`State Bar No. 21671300
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`609 Main Street, 40th Floor
`Houston, TX 77002
`Tel: (713) 658-6400
`Fax: (713) 658-6400
`cfrost@orrick.com
`
`Attorneys for Defendants Micron Technology,
`Inc., Micron Semiconductor Products, Inc., and
`Micron Technology Texas, LLC
`
`
`
`

`

`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 2 of 35
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`
`
`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES .......................................................................................................... ii 
`
`I. 
`
`INTRODUCTION .................................................................................................................. 1 
`
`II. 
`
`’047 PATENT ......................................................................................................................... 1 
`
`A. 
`
`“surface-channel-type MOSFET” ........................................................................... 1 
`
`III.  ’616 PATENT ......................................................................................................................... 3 
`
`A. 
`
`B. 
`
`“forming a plate electrode on the capacitor insulating film” .................................. 3 
`
`“Wherein the length of a portion where the opposing capacitors are
`overlapperd [sic] in the mask layout is set so that the value of the parasitic
`capacitance between adjacent cell capacitors is not more than 10% of the
`set cell capacitance value” ...................................................................................... 7 
`
`IV.  ’320 PATENT ....................................................................................................................... 12 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`“a DRAM region and a high-speed CMOS logic region that are co-
`resident with each other” ...................................................................................... 12 
`
`“sense amplifier transistor” ................................................................................... 15 
`
`“a N-type sense amplifier transistor and … a P-type sense amplifier
`transistor constituting a CMOS sense amplifier” .................................................. 17 
`
`“parallel” ............................................................................................................... 19 
`
`V. 
`
`’041 PATENT ....................................................................................................................... 19 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`“Copper-Diffusion Blocking Means” ................................................................... 19 
`
`“A Memory Storage Portion” ............................................................................... 22 
`
`“[A Wiring Portion] … Apart From Said Memory Storage Portion” ................... 26 
`
`“[Copper-Diffusion Blocking Means] Provided in a Region Surrounding
`the Memory Storage Portion” ............................................................................... 27 
`
`VI.  CONCLUSION ..................................................................................................................... 29 
`
`CERTIFICATE OF SERVICE ..................................................................................................... 30 
`
`
`
`i
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 3 of 35
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`
`
`Cases 
`
`TABLE OF AUTHORITIES
`
`Adaptix, Inc. v. Alcatel-Lucent USA, Inc.,
`No. 6:12-CV-22, 2014 WL 894844 (E.D. Tex. Feb. 26, 2014) .......................................... 3
`
`Akzo Nobel Coatings, Inc. v. Dow Chem. Co.,
`811 F.3d 1334 (Fed. Cir. 2016)......................................................................................... 14
`
`Aylus Networks, Inc. v. Apple Inc.,
`856 F.3d 1353 (Fed. Cir. 2017)........................................................................................... 3
`
`BASF Agro v. B.V. Makhteshim Agan of N. Am., Inc.,
`519 F. App’x 1008 (Fed. Cir. 2013) ................................................................................... 3
`
`Becton, Dickinson & Co., v. Tyco Healthcare Grp., LP,
`616 F.3d 1249 (Fed. Cir. 2010)................................................................................... 14, 28
`
`Blackboard, Inc. v. Desire2Learn, Inc.,
`574 F.3d 1371 (Fed. Cir. 2009)......................................................................................... 20
`
`Brown v. 3M,
`265 F.3d 1349 (Fed. Cir. 2001)......................................................................................... 22
`
`Chef Am., Inc. v. Lamb-Weston, Inc.,
`358 F.3d 1371 (Fed. Cir. 2004)......................................................................................... 23
`
`Digital-Vending Servs. Int’l, LLC v. Univ. of Phoenix, Inc.,
`672 F.3d 1270 (Fed. Cir. 2012)......................................................................................... 10
`
`Fenner Invs., Ltd. v. Cellco P’ship,
`778 F.3d 1320 (Fed. Cir. 2015)......................................................................................... 12
`
`Fonar Corp. v. Gen. Elec. Co.,
`107 F.3d 1543 (Fed. Cir.), cert. denied, 522 U.S. 908 (1997) .......................................... 22
`
`Gaus v. Conair Corp.,
`363 F.3d 1284 (Fed. Cir. 2004)......................................................................................... 28
`
`Helmsderfer v. Bobrick Washroom Equip., Inc.,
`527 F.3d 1379 (Fed. Cir. 2008)......................................................................................... 16
`
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014)......................................................................................... 26
`
`IGT v. Bally Gaming Int’l, Inc.,
`659 F.3d 1109 (Fed. Cir. 2011)................................................................................... 16, 23
`
`ii
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`

`

`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 4 of 35
`
`
`
`Intel Corp. v. VIA Techs.,
`319 F.3d 1357 (Fed. Cir. 2003)......................................................................................... 17
`
`Interactive Gift Exp., Inc. v. Compuserve Inc.,
`256 F.3d 1323 (Fed. Cir. 2001)........................................................................................... 4
`
`Invensas Corp. v. Renesas Elecs. Corp.,
`No. 11-448-GMS, 2013 WL 3753621 (D. Del. July 15, 2013) .......................................... 8
`
`Invensas Corp. v. Samsung Elecs. Co., Ltd.,
`No. 2:17-cv-00670-RWS-RSP, 2018 WL 5306757 (E.D. Tex. Oct. 26, 2018) ................. 8
`
`Jansen v. Rexall Sundown, Inc.,
`342 F.3d 1329 (Fed. Cir. 2003)........................................................................................... 8
`
`Leach v. Pharmedoc, Inc.,
`No. CIV-16-1034-SLP, 2019 WL 2453669 (W.D. Okla. June 12, 2019) ........................ 18
`
`Liberty Ammunition, Inc. v. U.S.,
`835 F.3d 1388 (Fed. Cir. 2016)......................................................................................... 27
`
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co., Ltd.,
`521 F.3d 1351 (Fed. Cir. 2008)......................................................................................... 26
`
`Oatey Co. v. IPS Corp.,
`514 F.3d 1271 (Fed. Cir. 2008)......................................................................................... 26
`
`Paragon Sols., LLC v. Timex Corp.,
`556 F.3d 1075 (Fed. Cir. 2009)........................................................................................... 2
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................... 3, 17, 24
`
`Rapoport v. Dement,
`254 F.3d 1053 (Fed. Cir. 2001)........................................................................................... 8
`
`SciMed Life Sys., Inc. v. Advanced Cardiovascular Sys., Inc.,
`242 F.3d 1337 (Fed. Cir. 2001)........................................................................................... 4
`
`Sensor Elec. Tech., Inc. v. Bolb, Inc.,
`No. 18-cv-05194-LHK, 2019 WL 4645338 (N.D. Cal. Sept. 24, 2019) ............................ 2
`
`Spectrum Int’l, Inc. v. Sterilite Corp.,
`164 F.3d 1372 (Fed. Cir. 1988)........................................................................................... 4
`
`Teleflex, Inc. v. Ficosa N. Am. Corp.,
`299 F.3d 1313 (Fed. Cir. 2002)........................................................................................... 4
`
`iii
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 5 of 35
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`
`
`USB Bridge Sols., LLC v. Buffalo Inc.,
`No. 1-17-CV-001158-LY, 2020 WL 1906898 (W.D. Tex. Apr. 17, 2020) ....................... 4
`
`Ushijima v. Samsung Elecs. Co., Ltd.,
`No. A-12-cv-318-LY, 2014 WL 12167634 (W.D. Tex. Oct. 10, 2014) ............................. 2
`
`Whirlpool Corp. v. LG Elecs., Inc.,
`423 F. Supp. 2d 730 (W.D. Mich. 2004) ............................................................................ 9
`
`
`
`
`
`iv
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 6 of 35
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`
`
`I.
`
`INTRODUCTION
`
`Godo Kaisha’s proposed claim constructions are premised on four fundamental errors.
`
`First, Godo Kaisha uses the claim language as a mere suggestion and repeatedly reads out express
`
`requirements of the claims or overlooks the surrounding claim language. Second, Godo Kaisha
`
`mischaracterizes the specification by citing passages out of context, broadly glossing over (or
`
`wholly disregarding) contrary passages—including passages defining the structural requirements
`
`for the means-plus-function claim limitation—and reading limitations into the claims that are not
`
`supported by the specification. Third, Godo Kaisha flatly ignores the prosecution history, refusing
`
`to even acknowledge the patentee’s express statements distinguishing the prior art. Finally, Godo
`
`Kaisha insists that “plain and ordinary meaning” is a sufficient construction while leaving the jury
`
`to guess at the meaning of complex, technical terms—defeating the very purpose of claim
`
`construction. In sum, under its flawed reading of the intrinsic record, Godo Kaisha urges the Court
`
`to adopt constructions that are not only legally erroneous but fail to provide the jury the necessary
`
`guidance to properly apply the claims to the accused products and prior art. Godo Kaisha’s
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`unhelpful, inaccurate constructions should be rejected.
`
`II.
`
`’047 PATENT
`A.
`
`“surface-channel-type MOSFET”
`
`The parties agree on the meaning of the technical term “surface-channel-type MOSFET.”
`
`The parties dispute, however, whether the Court should instruct the jury on what the term means
`
`(Micron’s position), or whether it should leave lay jurors to grapple with a claim term about which
`
`none of them have heard (Godo Kaisha’s position).
`
`Godo Kaisha does not dispute that the channel of a surface-channel-type MOSFET forms
`
`near the top surface of the semiconductor substrate. Dkt. No. 59 (“Godo Kaisha Op. Br.”), 16-18.
`
`Instead, it raises artificial objections to Micron’s construction. First, it alleges that Micron’s
`
`1
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 7 of 35
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`construction could exclude certain surface-channel-type MOSFETs in which their channels form
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`“at” the semiconductor surface. Id., 18. Not so. By definition, the word “near” includes, and is
`
`broader than, “at”: “near” means “at, within, or to a short distance or time.” Lang Resp. Decl., Ex.
`
`32, Merriam-Webster’s Collegiate Dictionary at MIPB0006023. For example, if a visitor is “at”
`
`the front door, she necessarily is “near” it.1
`
`Second, Godo Kaisha complains that Micron’s construction uses the relative terms “near”
`
`and “deeper.” Id., 17. To start, Micron’s construction does not use the term “deeper.” As for
`
`“near,” Godo Kaisha does not dispute that this characteristic of a surface channel transistor
`
`(“near”) is what defines it. That is, Godo Kaisha admits that a surface-channel transistor means
`
`that it has a channel that forms near (e.g., close to, at, or along) the top surface of the substrate,
`
`whereas a buried-channel transistor has a channel that forms below the top surface. Id., 18. It is
`
`entirely appropriate, therefore, to construe the term in this way.2 See, e.g., Ushijima v. Samsung
`
`Elecs. Co., Ltd., No. A-12-cv-318-LY, 2014 WL 12167634, at *2 (W.D. Tex. Oct. 10, 2014)
`
`
`1 If there is any concern here, Micron does not object to the following construction: “a MOSFET
`(metal-oxide-semiconductor-field-effect-transistor) in which the channel forms at or near the top
`surface of the semiconductor substrate.”
`2 Godo Kaisha’s reliance on Paragon Sols., LLC v. Timex Corp., 556 F.3d 1075, 1090-91 (Fed.
`Cir. 2009), is misplaced. There, the Federal Circuit did not reject the district court’s construction
`based on the use of a “vague term[] of degree.” Godo Kaisha Op. Br. at 17. Instead, the Federal
`Circuit found that the dictionary definition on which the district court relied was “too vague to be
`of significant help in resolving the dispute” because it “shed[] no light on” the meaning of the
`disputed term. Paragon Sols., 556 F.3d at 1092. The Federal Circuit’s reasoning was thus
`unrelated to the use of a term of degree. Moreover, Godo Kaisha’s citation to Sensor Elec. Tech.,
`Inc. v. Bolb, Inc., No. 18-cv-05194-LHK, 2019 WL 4645338, at *37 (N.D. Cal. Sept. 24, 2019),
`Godo Kaisha Op. Br. at 17-18, supports Micron’s construction. There, the court did not wholly
`reject using terms of degree to construe claims but, instead, distinguished between vague terms of
`degree and those that are tethered to an objective property and thus proper. Sensor Elec., 2019
`WL 4645338, at *37 (rejecting construction that the “thickness of a barrier and well is short (thin)”
`as vague, and adopting construction that “the barriers are thin enough to provide carrier
`movement”). Micron’s construction here properly ties the term of degree (“near”) specifically to
`an objective boundary, i.e., “the top surface of the semiconductor substrate” and is thus appropriate
`under Sensor Electronic.
`
`2
`
`

`

`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 8 of 35
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`
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`(construing claim language using terms of degree “close” and “loose”); Adaptix, Inc. v. Alcatel-
`
`Lucent USA, Inc., No. 6:12-CV-22, 2014 WL 894844, at *8-9 (E.D. Tex. Feb. 26, 2014) (adopting
`
`claim construction including relative term “roughly the same”).
`
`At bottom, the dispute boils down to whether the jury should be instructed about the
`
`meaning of a highly technical term. It should be, because the jury will need the instruction to
`
`decide whether the accused transistors and those in the prior art are surface-channel or buried-
`
`channel transistors. Dkt. No. 60 (“Micron Op. Br.”), 2-3. It cannot do so unless it knows that the
`
`factual question is where does the channel form (near the top surface or below the top surface).
`
`III.
`
`’616 PATENT
`A.
`
`“forming a plate electrode on the capacitor insulating film”
`
`Godo Kaisha attacks Micron’s construction solely on the theory that it is not described in
`
`the patent specification. Godo Kaisha Op. Br., 20. This argument fails for at least two reasons.
`
`First, Godo Kaisha blithely ignores the fact that a claim term can be limited by statements
`
`made during patent prosecution. The Federal Circuit has “recognized that ‘the prosecution history
`
`can often inform the meaning of the claim language by demonstrating how the inventor understood
`
`the invention.’” Aylus Networks, Inc. v. Apple Inc., 856 F.3d 1353, 1359 (Fed. Cir. 2017) (quoting
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1317 (Fed. Cir. 2005) (en banc)). Because “[t]he public
`
`has a right to rely on representations a patentee has made in the course of obtaining her patent,”
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`BASF Agro v. B.V. Makhteshim Agan of N. Am., Inc., 519 F. App’x 1008, 1015 (Fed. Cir. 2013),
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`a patentee’s statements “distinguishing the claimed invention over the prior art during prosecution
`
`indicates what a claim does not cover.” USB Bridge Sols., LLC v. Buffalo Inc., No. 1-17-CV-
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`3
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 9 of 35
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`
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`001158-LY, 2020 WL 1906898, at *2 (W.D. Tex. Apr. 17, 2020) (citing Spectrum Int’l, Inc. v.
`
`Sterilite Corp., 164 F.3d 1372, 1378-79 (Fed. Cir. 1988)).3
`
`Here, during prosecution, the patentee clearly limited the term “forming a plate electrode
`
`on the capacitor insulating film” to plate electrodes that do not shield the outer surface of the
`
`storage electrode. During prosecution, the examiner issued a final rejection of claim 1 as
`
`anticipated by DeBoer et al. (U.S. Patent No. 6,737,696) and rendered obvious by DeBoer in
`
`combination with Huang (U.S. Patent No. 6,617,631). Ex. 7, 6/14/2006 Final Office Action at
`
`MIPB0000695-98.4 The examiner explained that DeBoer disclosed each step of claim 1, including
`
`arranging capacitors in a staggered manner. Id. The patentee overcame this rejection by arguing:
`
`DeBoer et al. [is] directed to a capacitor structure like that shown in Figure 15 of
`the specification. The capacitor structure disclosed by DeBoer et al. is therefore
`different from the structure recited in claim [1] because parasitic capacitance is not
`caused between adjacent cell capacitors in the capacitor structure disclosed by
`DeBoer et al.
`
`Ex. 7, 10/16/2006 Response at MIPB0000739; Dkt. No. 60-2 (“Schubert Decl.”) ¶¶ 53-55, 57-59.
`
`That is, the patentee unambiguously distinguished DeBoer on the ground that it disclosed
`
`a different capacitor structure from that disclosed in claim 1 of the ’616 patent. The three capacitor
`
`structures—DeBoer (Fig. 17), ’616 patent Figure 15 (depicting the prior art (see ’616, 6:52-53,
`
`
`3 Godo Kaisha’s own caselaw authorities recognize that “a deviation from the clear language of
`the claims … may [] be necessary if a patentee has relinquished a potential claim construction in
`an amendment to the claim or in an argument to overcome or distinguish a reference.” Interactive
`Gift Exp., Inc. v. Compuserve Inc., 256 F.3d 1323, 1331 (Fed. Cir. 2001) (internal quotation marks
`omitted); see also Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313, 1326 (Fed. Cir. 2002)
`(“[T]he prosecution history may demonstrate that the patentee intended to deviate from a term’s
`ordinary and accustomed meaning.”). Godo Kaisha’s reliance on SciMed Life Sys., Inc. v.
`Advanced Cardiovascular Sys., Inc., 242 F.3d 1337, 1340 (Fed. Cir. 2001), is misplaced because,
`there, the court explained that “[t]here is nothing pertinent to this [claim construction] issue in the
`prosecution history of the three patents; the case turns entirely on an interpretation of the asserted
`claims in light of the specification.” Id. That, of course, is not the case here as detailed below.
`4 Unless otherwise noted, exhibits cited herein are attached to Micron’s Opening Claim
`Construction Brief, Dkt. Nos. 60, 61.
`
`4
`
`

`

`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 10 of 35
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`1:66-2:3)), and ’616 patent Figure 2 (depicting the capacitor structure used in claim 1 (see ’616,
`
`7:41-51))—are below:
`
`
`
`DeBoer (Ex. 28) Fig. 17; ’616, Figs. 15, 2 (all annotated).
`
`As the figures show, in both DeBoer and Figure 15—the “conventional” capacitor
`
`structure—the plate electrode (green) covers a substantial portion (if not the entirety) of the outer
`
`surface of the storage node (blue), thus shielding adjacent storage nodes from each other. See
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`’616, 6:52-53, 1:66-2:3; see also Schubert Decl. ¶ 60. In contrast, in the “different” structure
`
`shown in Figure 2 (claim 1)—the “trench-type” capacitor structure—the plate electrode does not
`
`cover the outer surface of the storage node. Instead, storage nodes are separated only by the
`
`interlayer insulating film. See ’616, 2:66-3:3; see also Schubert Decl. ¶¶ 62-63.
`
`The patentee explained exactly why this distinction between capacitor structures was
`
`important. In conventional capacitor structures like those used in DeBoer and Figure 15, “a large
`
`parasitic capacitance is not generated between the adjacent cell capacitors” due to the positioning
`
`of the plate electrode. Ex. 7, 10/16/2006 Response at MIPB0000739; see Schubert Decl. ¶ 61.
`
`Trench-type capacitor structures, on the other hand, generate larger parasitic capacitance because
`
`the plate electrode does not shield adjacent storage nodes from each other. See ’616, 2:66-3:36
`
`(trench-type stacked cell structure capacitors generate larger parasitic capacitance “compared with
`
`5
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 11 of 35
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`
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`other cell capacitor structures”); Schubert Decl. ¶ 64. The patentee thus argued that, even though
`
`DeBoer disclosed staggering capacitors, “DeBoer [] does not disclose the reduction of a parasitic
`
`capacitance or even suggest the feature of sufficiently reducing the parasitic capacitance such as
`
`recited in claim [1]” because barely any parasitic capacitance is generated to begin with. Ex. 7,
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`10/16/2006 Response at MIPB0000740 (emphasis added).
`
`This was the very problem that the ’616 patent aimed to address—reducing parasitic
`
`capacitance caused by the trench-type capacitor structure. See, e.g., ’616, Abstract (“A DRAM is
`
`provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors.”);
`
`id., 3:40-46 (“[I]t is an object of the present invention to provide a semiconductor memory device
`
`that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a DRAM
`
`memory cell region.”); Schubert Decl. ¶ 65. And the alleged solution to this problem was
`
`staggering the capacitors. See ’616, 7:35-40, 9:8-29. Had the ’616 patent claimed capacitor
`
`structures like those used in DeBoer or Figure 15 (the prior art), the parasitic capacitance would
`
`already be negligible and there would be no need to stagger the capacitors to reduce parasitic
`
`capacitance, as the patentee itself explained. See Schubert Decl. ¶¶ 61, 66; see also Ex. 7,
`
`10/16/2006 Response at MIPB0000740. Thus, the capacitor structure distinction that was made
`
`during prosecution was critical to the patent’s issuance, and the patentee’s disclaimer is clear—in
`
`the capacitor structure disclosed by claim 1 of the ’616 patent, the plate electrode does not cover
`
`any portion of the outer surface of the storage nodes. See Schubert Decl. ¶ 67. Godo Kaisha’s
`
`proposed construction, which ignores the prosecution history and captures the claim scope
`
`expressly disclaimed by the patentee, should be rejected.
`
`Godo Kaisha’s argument that Micron’s construction “is found nowhere in the
`
`specification” fails for a second reason: it is found in the specification. The specification states
`
`6
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 12 of 35
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`that “the trench-type stacked cell structure” to which the patent is directed “is a cell structure that
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`utilizes only the inner surfaces of the trenches.” ’616, 1:58-61 (emphasis added); Schubert Decl.
`
`¶ 51. This corresponds directly to Micron’s construction, which provides that the plate electrode
`
`does not shield the outer surface of the storage node. The specification also distinguishes between
`
`the negligible parasitic capacitance generated by the conventional capacitor structure that uses the
`
`plate electrode to shield adjacent storage nodes, and the larger parasitic capacitance generated by
`
`the claimed capacitor structure in which the plate electrode does not shield adjacent storage nodes.
`
`Compare id., 2:28-30 (In the prior art capacitor structures, “adjacent cell capacitors are connected
`
`electrically by the plate electrodes [] each of which has the same electric potential. Therefore, a
`
`large parasitic capacitance is not generated between the adjacent cell capacitors even if the plate
`
`electrode is covered with an interlayer insulating film.”), with 2:66-3:6 (“In the trench-type stacked
`
`cell structure, though the storage nodes … are separated electrically and have different potentials,
`
`an interlayer insulating film is interposed between the adjacent cell capacitors. Therefore, the
`
`trench-type stacked cell structure may cause a problem that a larger parasitic capacitance is
`
`generated easily compared with other cell capacitor structures.”). The specification then insists
`
`that “the trench-type stacked cell structures,” not the conventional structure, “are expected to be
`
`used as the capacitor structure of memory cells in [the] future.” ’616, 2:49-65. The specification
`
`thus describes the configuration in Micron’s construction.
`
`B.
`
`“Wherein the length of a portion where the opposing capacitors are
`overlapperd [sic] in the mask layout is set so that the value of the parasitic
`capacitance between adjacent cell capacitors is not more than 10% of the set
`cell capacitance value”
`
`Notwithstanding that the claim requires that the layout “is set so that” a particular parasitic
`
`capacitance value is thereby achieved, Godo Kaisha insists that the intent behind staggering
`
`capacitors is irrelevant to the claim. Godo Kaisha Op. Br., 21-22. In doing so, Godo Kaisha relies
`
`7
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`

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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 13 of 35
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`on erroneous legal standards, ignores the express language of the claim and specification, and
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`misreads the prosecution history.
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`Godo Kaisha argues that “direct infringement is a strict-liability offense” and that intent is
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`therefore irrelevant to its claim. Id., 22. Godo Kaisha is wrong. The Federal Circuit has repeatedly
`
`interpreted claims to include an intent element where the claim language reflects “a statement of
`
`the intentional purpose for which the method must be performed,” especially where such intent is
`
`“bolstered by an analysis of the prosecution history.” Jansen v. Rexall Sundown, Inc., 342 F.3d
`
`1329, 1333 (Fed. Cir. 2003); see also Rapoport v. Dement, 254 F.3d 1053, 1061 (Fed. Cir. 2001)
`
`(finding claim required method be administered “with the intent to cure the underlying condition”).
`
`And district courts have flatly rejected the argument that the “strict liability” nature of infringement
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`means that intent cannot be incorporated during claim construction. See, e.g., Invensas Corp. v.
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`Renesas Elecs. Corp., No. 11-448-GMS, 2013 WL 3753621, at *2 n.10 (D. Del. July 15, 2013)
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`(“There is no rule barring a patentee from including an intent requirement in its claims.”); Invensas
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`Corp. v. Samsung Elecs. Co., Ltd., No. 2:17-cv-00670-RWS-RSP, 2018 WL 5306757, at *9 (E.D.
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`Tex. Oct. 26, 2018) (adopting Renesas intent analysis). As these courts have explained, when a
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`patentee incorporates intent into the claims, “the claimed method itself cannot be performed absent
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`[that] intent.” Renesas, 2013 WL 3753621, at *2 n.10.
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`Here, the express language of the claim, the specification, and the prosecution history
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`require that the claimed staggered capacitor layout be specifically intended to reduce the value of
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`the parasitic capacitance between adjacent cell capacitors and prevent it from exceeding 10% of
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`the set cell capacitance. To start, the claim recites that “the length of a portion where the opposing
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`capacitors are overlappe[d] in the mask layout”—i.e., the staggered layout—“is set so that the
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`value of the parasitic capacitance between adjacent cell capacitors is not more than 10% of the set
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`Case 6:20-cv-00178-ADA Document 62 Filed 10/16/20 Page 14 of 35
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`cell capacitance.” ’616, claim 1 (emphasis added). The phrase “is set so that” recites a clear
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`intention for the staggered layout—namely, reducing parasitic capacitance and preventing it from
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`exceeding 10% of the set cell capacitance. See Schubert Decl. ¶¶ 70, 76; see also Whirlpool Corp.
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`v. LG Elecs., Inc., 423 F. Supp. 2d 730, 753 (W.D. Mich. 2004) (claim language “fresh water is
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`added to cool said fabric” required that “fresh water be added with the intention or purpose of
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`cooling the fabric”).
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`If the claim simply required staggering capacitors for any purpose, as Godo Kaisha argues,
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`there would be no need for the clause “is set so that.” Instead, the claim would just recite “wherein
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`the length of a portion where the opposing capacitors are overlappe[d] in the mask layout and the
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`value of the parasitic capacitance between adjacent cell capacitors is not more than 10% of the set
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`cell capacitance value.” But instead of drafting these limitations as two unrelated requirements
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`(i.e., (1) stagger, and (2) a certain parasitic capacitance value), the patentee chose to tie these
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`requirements together—the stagger “is set so that” a certain parasitic capacitance value is achieved.
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`Godo Kaisha’s construction, which reads out an entire clause from the claim, clearly violates “the
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`well-established rule that claims are interpreted with an eye toward giving effect to all terms in the
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`claim … such that words in a claim are not rendered superfluous.” Digital-Vending Servs. Int’l,
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`LLC v. Univ. of Phoenix, Inc., 672 F.3d 1270, 1275 (Fed. Cir. 2012) (internal quotation and
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`citations omitted).5
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`Moreover, the specification confirms this intent by explaining that the purpose of
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`staggering capacitors is to reduce the parasitic capacitance generated between trench-type stacked
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`5 Godo Kaisha’s insistence that the claim uses “set,” not “designed,” misses the point. In context,
`“set” means arranged, positioned, or designed, and the claim establishes an express intention that
`the staggered layout be set (or designed or arranged) so that the reduced parasitic capacitance level
`is achieved.
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`cell capacitors and to prevent it from exceeding 10% of the set cell capacitance. See, e.g., ’616,
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`3:40-46 (“it is an object of the present invention to provide a semiconductor memory device that
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`can reduce the parasitic capacitance between trench-type stacked cell capacitors”), 8:63-67
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`(“When the parasitic capacitance is more than 10%, it exceeds the set margin,” resulting in
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`malfunctions.), 9:37-43 (“[M]alfunction occurs remarkably when the parasitic capacitance is more
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`than 10% of the set capacitance.”); see also Schubert Decl. ¶ 71. The only example of claim 1 in
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`the specification teaches staggering specifically to prevent the parasitic capacitance from
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`exceeding 10% of the set cell capacitance. See ’616, 7:66-9:47 (reducing parasitic capacitance
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`from 10.6% of the set cell capacitance without staggered layout to 8% with staggered layout); see
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`also Schubert Decl. ¶¶ 77-84. Godo Kaisha cannot identify one passage in the specification where
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`the capacitor layout is staggered for a reason other than reducing parasitic capacitance and
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`preventing it from exceeding 10% of the set cell capacitance. Similarly, Godo Kaisha cannot
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`identify any passage in the specification that discloses achieving reduced parasitic capacitance
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`through any means other than staggering. See Schubert Decl. ¶¶ 74, 86-89 (explaining multiple
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`ways to reduce parasitic capacitance unrelated to staggering capacitors and finding only staggering
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`claimed by the ’616 patent).
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`During prosecution, the patentee was explicit that the stagger recited in claim 1 was
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`“designed to reduce [] parasitic capacitance.” Ex. 7, 10/16/2006 Response at MIPB0000740. In
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`rejecting claim 1 as anticipated by DeBoer and rendered obvious by DeBoer in combination with
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`Huang, the examiner noted that DeBoer disclosed the recited staggered layout. Id., 6/14/2006
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`Office Action at MIPB0000695-97 (“DeBoer [] discloses that the mask pattern having a layout in
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`which a plurality of hole patterns … are arranged in a stagger manner so that side edges of the
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`adjacent hole patterns are only partially opposite to each other.”). To overcome this rejection, the
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