Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 1 of 36
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`C.A. No. 6:20-cv-178-ADA
`
`JURY TRIAL DEMANDED
`
`§§§§§§§§§§
`
`GODO KAISHA IP BRIDGE 1,
`
`Plaintiff,
`
`v.
`
`MICRON TECHNOLOGY, INC., MICRON
`SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS, LLC,
`
`Defendants.
`
`MICRON’S OPENING CLAIM CONSTRUCTION BRIEF
`
`Jared Bobrow (CA State Bar No. 133712)
`Jason Lang (CA State Bar No. 255642)
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`Tel: (650) 614-7400
`Fax: (650) 614-7401
`jbobrow@orrick.com
`jlang@orrick.com
`
`Claudia Wilson Frost
`State Bar No. 21671300
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`609 Main Street, 40th Floor
`Houston, TX 77002
`Tel: (713) 658-6400
`Fax: (713) 658-6400
`cfrost@orrick.com
`
`Attorneys for Defendants Micron Technology,
`Inc., Micron Semiconductor Products, Inc., and
`Micron Technology Texas, LLC
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 2 of 36
`
`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES ......................................................................................................... iii
`
`I.
`
`II.
`
`INTRODUCTION .................................................................................................................. 1
`
`’047 PATENT ......................................................................................................................... 1
`
`A.
`
`B.
`
`Background of the ’047 Patent ............................................................................... 1
`
`Disputed Terms ....................................................................................................... 2
`
`1.
`
`“surface-channel-type MOSFET” ............................................................... 2
`
`III.
`
`’616 PATENT ......................................................................................................................... 3
`
`A.
`
`B.
`
`Background of the ’616 Patent ............................................................................... 3
`
`Disputed Terms ....................................................................................................... 5
`
`1.
`
`2.
`
`“forming a plate electrode on the capacitor insulating film” ...................... 5
`
`“Wherein the length of a portion where the opposing capacitors are
`overlapperd [sic] in the mask layout is set so that the value of the
`parasitic capacitance between adjacent cell capacitors is not more than
`10% of the set cell capacitance value” ........................................................ 9
`
`a.
`
`b.
`
`Stagger To Reduce Parasitic Capacitance ........................................9
`
`Stagger To Prevent Parasitic Capacitance From Exceeding
`10% ................................................................................................11
`
`IV.
`
`’320 PATENT ....................................................................................................................... 13
`
`A.
`
`B.
`
`Background of the ’320 Patent ............................................................................. 13
`
`Disputed Terms ..................................................................................................... 14
`
`1.
`
`2.
`
`3.
`
`4.
`
`“a DRAM region and a high-speed CMOS logic region that are co-
`resident with each other” .......................................................................... 14
`
`“sense amplifier transistor” ....................................................................... 16
`
`“a N-type sense amplifier transistor and … a P-type sense amplifier
`transistor constituting a CMOS sense amplifier”...................................... 17
`
`“parallel” ................................................................................................... 18
`
`i
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 3 of 36
`
`V.
`
`’041 PATENT ....................................................................................................................... 20
`
`A.
`
`B.
`
`Background of the ’041 Patent ............................................................................. 20
`
`Disputed Terms ..................................................................................................... 21
`
`1.
`
`2.
`
`3.
`
`4.
`
`“[A Wiring Portion] … Apart From Said Memory Storage Portion” ....... 21
`
`“Copper-Diffusion Blocking Means” ....................................................... 22
`
`“[Copper-Diffusion Blocking Means] Provided in a Region
`Surrounding the Memory Storage Portion” .............................................. 26
`
`“A Memory Storage Portion” ................................................................... 27
`
`VI. CONCLUSION ..................................................................................................................... 30
`
`CERTIFICATE OF SERVICE ..................................................................................................... 31
`
`ii
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 4 of 36
`
`Cases
`
`TABLE OF AUTHORITIES
`
`Ajinomoto Co. v. Int’l Trade Comm’n,
`932 F.3d 1342 (Fed. Cir. 2019)......................................................................................... 13
`
`Akzo Nobel Coatings, Inc. v. Dow Chem. Co.,
`811 F.3d 1334 (Fed. Cir. 2016)......................................................................................... 15
`
`Aristocrat Techs. Australia Pty Ltd. v. Int'l Game Tech.,
`521 F.3d 1328 (Fed. Cir. 2008)......................................................................................... 24
`
`Aylus Networks, Inc. v. Apple Inc.,
`856 F.3d 1353 (Fed. Cir. 2017)........................................................................................... 9
`
`Default Proof Credit Card Sys., Inc. v. Home Depot U.S.A., Inc.,
`412 F.3d 1291 (Fed. Cir. 2005)......................................................................................... 25
`
`Digital-Vending Servs. Int’l, LLC v. Univ. of Phoenix, Inc.,
`672 F.3d 1270 (Fed. Cir. 2012)..................................................................................... 3, 13
`
`Forest Labs., LLC v. Sigmapharm Labs., LLC,
`918 F.3d 928 (Fed. Cir. 2019)........................................................................................... 15
`
`Greenthread, LLC v. Samsung Elecs. Co., Ltd.,
`No. 2:19-CV-00147-JRG, 2020 WL 1911200 (E.D. Tex. Apr. 20, 2020) ......................... 3
`
`Innovative Memory Sys., Inc. v. Micron Tech., Inc.,
`781 F. App’x 1013 (Fed. Cir. 2019) ................................................................................. 13
`
`Jansen v. Rexall Sundown, Inc.,
`342 F.3d 1329 (Fed. Cir. 2003)......................................................................................... 10
`
`Merck & Co. v. Teva Pharm. USA, Inc.,
`395 F.3d 1364 (Fed. Cir. 2005)......................................................................................... 15
`
`Micro Chem., Inc. v. Great Plains Chem. Co.,
`194 F.3d 1250 (Fed. Cir. 1999)......................................................................................... 26
`
`Motorola, Inc. v. Vosi Techs., Inc.,
`No. 01 C 4182, 2001 WL 1646559 (N.D. Ill. Dec. 21, 2001) .......................................... 26
`
`NeoMagic Corp. v. Trident Microsystems, Inc.,
`287 F.3d 1062 (Fed. Cir. 2002)......................................................................................... 28
`
`Northrop Grumman Corp. v. Intel Corp.,
`325 F.3d 1346 (Fed. Cir. 2003)............................................................................. 23, 24, 25
`
`iii
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 5 of 36
`
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co., Ltd.,
`521 F.3d 1351 (Fed. Cir. 2008)......................................................................................... 21
`
`Omega Eng’g, Inc. v. Raytek Corp.,
`334 F.3d 1314 (Fed. Cir. 2003)........................................................................................... 9
`
`Tomita Techs. USA, LLC v. Nintendo Co., Ltd.,
`594 F. App’x 657 (Fed. Cir. 2014) ............................................................................. 24, 25
`
`Verizon Servs. Corp. v. Vonage Holdings Corp.,
`503 F.3d 1295 (Fed. Cir. 2007)......................................................................................... 15
`
`Vita-Mix Corp. v. Basic Holding, Inc.,
`581 F.3d 1317 (Fed. Cir. 2009)......................................................................................... 28
`
`Whirlpool Corp. v. LG Elecs., Inc.,
`423 F. Supp. 2d 730 (W.D. Mich. 2004) .......................................................................... 10
`
`Statutes
`
`35 U.S.C. § 112 ............................................................................................................................. 23
`
`iv
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 6 of 36
`
`I.
`
`INTRODUCTION
`
`Claim construction is intended to assist the decision-maker by giving meaning to the claim
`
`terms. Contrary to that aim, Godo Kaisha largely avoids construing the disputed claim terms,
`
`instead hiding behind the guise of “plain meaning” in an attempt to broaden the scope of its patents.
`
`But what Godo Kaisha has advanced as the “plain meaning” is repeatedly incorrect, both
`
`considered against the intrinsic record—including the claim language, specification, original
`
`prosecution history, and IPR proceedings—which Godo Kaisha entirely ignores, and from a
`
`technical perspective as understood by a person of ordinary skill in the art. Godo Kaisha’s “plain
`
`meaning” shield would allow the terms to be misinterpreted, the scope of the patents to be
`
`improperly broadened, and the claim construction process as a whole to be vitiated. Regarding
`
`the two terms for which Godo Kaisha offers actual constructions, Godo Kaisha’s proposals
`
`contradict the intrinsic record, including express language in the specification and Godo Kaisha’s
`
`own statements to the Patent Trial and Appeal Board during IPR proceedings. In sum, and as
`
`detailed further below, the Court should adopt Micron’s proposed constructions.1
`
`II.
`
`’047 PATENT
`
`A.
`
`Background of the ’047 Patent
`
`The ’047 Patent relates to a semiconductor memory device with “multiple types of surface-
`
`channel-type MOSFETs.” ’047, 2:15-20.
`
`1 Exhibits cited throughout are attached to the Declaration of J. Jason Lang. The patents-in-suit
`(namely, the ’047, ’616, ’320, and ’041 Patents) are attached as Ex. 1 (’047), Ex. 2 (’616), Ex. 3
`(’320) and Ex. 4 (’041).
`
`1
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 7 of 36
`
`B.
`
`Disputed Terms
`
`1.
`
`“surface-channel-type MOSFET”
`
`Micron’s Proposed Construction
`“a MOSFET
`(metal–oxide–semiconductor
`field effect transistor) in which the channel
`forms near
`the
`top
`surface of
`the
`semiconductor substrate”
`
`Godo Kaisha’s Proposed Construction
`Plain meaning
`
`The dispute between the parties is whether the channel of a “surface-channel-type
`
`MOSFET” forms, as its name implies, “near the top surface of the semiconductor substrate”
`
`(Micron’s position) or whether it can form under the substrate surface (Godo Kaisha’s position).2
`
`There are two categories of MOSFET transistors: surface-channel-type and buried-
`
`channel-type. Surface-channel transistors are distinguished by the fact that their channel forms
`
`near the top surface of the substrate, whereas buried-channel transistors have channels that form
`
`within the substrate (i.e., “buried”). Ex. 6, Chen at MIPB0002696 (“Discussions so far have
`
`covered device operations in surface-channel MOS-FETs in which carriers propagate at the
`
`semiconductor surface. However, in some devices such as depletion-mode devices, carriers
`
`propagate slightly under the semiconductor surface. This type of device is called a buried
`
`channel device.”)3; Sechen Decl. ¶¶ 26-29.
`
`Here, the claim is limited to a “surface-channel-type MOSFET.” Sechen Decl. ¶ 31. This
`
`is a term of art: it means that the channel forms at the surface of the substrate. The specification
`
`and file history are entirely consistent with this well understood meaning. Id. ¶ 32. Thus, the
`
`2 Godo Kaisha states that it is advocating plain meaning. Not so. For example, its expert expressly
`disagrees that the claim requires that the channel form near the top surface of the substrate, which
`is inconsistent with the plain meaning of “surface-channel.” See Ex. 5, Godo Kaisha’s Extrinsic
`Evidence, Ex. B at 1.
`3 Emphasis added unless otherwise noted.
`
`2
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 8 of 36
`
`Court should adopt the Micron’s construction. See, e.g., Greenthread, LLC v. Samsung Elecs. Co.,
`
`Ltd., No. 2:19-CV-00147-JRG, 2020 WL 1911200, at *15 (E.D. Tex. Apr. 20, 2020) (“To stray
`
`from this customary meaning, an alternate meaning must be clearly set forth in the intrinsic
`
`record.” (internal quotation marks omitted)). Godo Kaisha’s implicit construction improperly
`
`renders “surface-channel type” superfluous and would allow a buried-channel-type transistor to
`
`qualify as a surface-channel-type transistor. See Digital-Vending Servs. Int’l, LLC v. Univ. of
`
`Phoenix, Inc., 672 F.3d 1270, 1275 (Fed. Cir. 2012) (explaining “the well-established rule that
`
`claims are interpreted with an eye toward giving effect to all terms in the claim … such that words
`
`in a claim are not rendered superfluous” (internal quotation marks and citations omitted)); Sechen
`
`Decl. ¶ 33.
`
`III.
`
`’616 PATENT
`
`A.
`
`Background of the ’616 Patent
`
`The ’616 Patent is directed to a method for manufacturing semiconductor memory devices
`
`with trench-type stacked cell capacitors by staggering the capacitor layout to reduce parasitic
`
`capacitance (Cp) and prevent it from exceeding a specific level. ’616, 3:40-60. Capacitors store
`
`electrical charge and are made of three components: (1) a storage node electrode; (2) a dielectric
`
`layer (or capacitor insulating film); and (3) a plate electrode. Schubert Decl. ¶ 32. Capacitance,
`
`which measures the amount of charge stored by the capacitor (per applied volt), is calculated by
`
`multiplying the surface area of the capacitor electrodes (A) by the dielectric constant (kε0) of the
`
`dielectric material and then dividing by the distance between the capacitor electrodes (d):
`
`C = kε0A/d. Id. ¶¶ 33-34. Each of these factors impacts capacitance. For example, the smaller
`
`the surface area of the capacitor electrodes, the lower the capacitance. Id. ¶¶ 35-36. Similarly, a
`
`smaller dielectric constant or greater distance between capacitor electrodes will also generate less
`
`capacitance. Id. ¶ 36.
`
`3
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 9 of 36
`
`Parasitic capacitance is unwanted capacitance that results from the proximity of two
`
`conductors separated by a dielectric. Id. ¶ 37. For example, if two capacitor plates belonging to
`
`two different capacitors are adjacent to each other, and if there is only dielectric material between
`
`the plates, they will create unwanted parasitic capacitance. Id.
`
`Depending on the type of capacitor structure used, the magnitude of parasitic capacitance
`
`varies. Id. ¶ 38. For example, in “conventional” capacitor structures, like those used in the prior
`
`art and shown in Figure 15 of the ’616 Patent (below, annotated), “a large parasitic capacitance is
`
`not generated between the adjacent cell capacitors” because the plate electrode (green) shields the
`
`storage nodes (blue) of adjacent capacitors from each other. See ’616, 2:28-34; Schubert Decl.
`
`¶¶ 39-40. As a result, the parasitic capacitance generated in conventional capacitor structures is
`
`negligible. Schubert Decl. ¶ 41.
`
`In contrast, in “trench-type” cell capacitor structures like those claimed in claim 1 of the
`
`’616 Patent, the plate electrode does not shield adjacent storage nodes from each other, as shown
`
`below in Fig. 2 (annotated). Schubert Decl. ¶¶ 42-44. Because there is only dielectric (yellow)
`
`between the adjacent storage nodes, and because the plate electrode does not shield the adjacent
`
`storage nodes from each other, the structure creates a parasitic capacitor (two conductive plates
`
`separated by a dielectric) as indicated by “Cp1.”
`
`4
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 10 of 36
`
`See ’616, 7:41-45; Schubert Decl. ¶ 45. This structure “may cause a problem” in that “a larger
`
`parasitic capacitance is generated easily compared with other cell capacitor structures, even if the
`
`distance between adjacent cell capacitors in the trench-type stacked cell structure is the same as
`
`that in the other structures.” ’616, 2:66-3:8; Schubert Decl. ¶ 46.
`
`The ’616 Patent purports to reduce the parasitic capacitance generated between adjacent
`
`trench-type stacked cell capacitors—and prevent the parasitic capacitance from exceeding 10% of
`
`the set cell capacitance—by staggering the capacitors, as shown in Figure 1 below.
`
`B.
`
`Disputed Terms
`
`1.
`
`“forming a plate electrode on the capacitor insulating film”
`
`Micron’s Proposed Construction
`“the plate electrode is formed on the capacitor
`insulating film so that the plate electrode does
`not cover any portion of the outer surface of
`the storage node”
`
`Godo Kaisha’s Proposed Construction
`Plain meaning
`
`5
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 11 of 36
`
`Claim 1 requires “forming a plate electrode on the capacitor insulating film.” ’616, cl. 1.
`
`The parties dispute whether this limitation means that the plate electrode cannot cover the outer
`
`surface of the storage node. Because the patent applicant disclaimed cell capacitor structures in
`
`which the plate electrode shields adjacent storage nodes to secure its patent during prosecution,
`
`Micron’s construction is required.4
`
`During prosecution, the patent examiner finally rejected claim 1 (previously numbered
`
`application claim 7) as anticipated by U.S. Patent No. 6,737,696 (“DeBoer”) and as obvious over
`
`U.S. Patent No. 6,617,631 (“Huang”) in view of DeBoer. Ex. 7, 06/14/2006 Final Office Action
`
`at MIPB0000695-98. The examiner explained that DeBoer “discloses a method for manufacturing
`
`a semiconductor memory device” that reads on each step of claim 1, including arranging the
`
`capacitors in a staggered manner. Id. The examiner relied on, inter alia, Figures 2 and 17 of
`
`DeBoer (Ex. 28), shown below (annotated):
`
`In response, applicant distinguished DeBoer on the ground that, unlike claim 1, DeBoer is
`
`directed to a conventional capacitor structure, like those used in the prior art and represented in
`
`Figure 15 of the ’616 Patent:
`
`4 By using “cover,” Micron does not suggest that the plate electrode is formed directly on the
`storage node. As the claim requires and as Micron’s construction acknowledges, the plate
`electrode is formed on the capacitor insulating film, which is formed on the storage node.
`
`6
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 12 of 36
`
`DeBoer et al. [is] directed to a capacitor structure like that shown in Figure 15 of
`the specification. The capacitor structure disclosed by DeBoer et al. is therefore
`different from the structure recited in claim [1] because parasitic capacitance is
`not caused between adjacent cell capacitors in the capacitor structure disclosed
`by DeBoer at al.
`
`Ex. 7, 10/16/2006 Response at MIPB0000739. The ’616 Patent explains that Figure 15 (below,
`
`annotated) illustrates “the structure of conventional cylindrical cell capacitors,” ’616, 6:52-53, in
`
`which the plate electrode (green) shields the outside of the adjacent storage nodes (blue) from each
`
`other. Id., 1:66-2:3 (“In FIG. 15, capacitor insulating films 105, and thereon a plate electrode 106,
`
`are formed so as to cover the inner and outer surfaces of cylindrical storage nodes 104.”); Schubert
`
`Decl. ¶¶ 39-40, 60. As explained above, this “conventional” capacitor structure renders parasitic
`
`capacitance negligible. See id. ¶¶ 41, 61.
`
`The capacitor structure disclosed in DeBoer Fig. 17—which applicant equated to ’616 Patent
`
`Figure 15—similarly shows the plate electrode shielding the adjacent storage nodes from each
`
`other. See id. ¶¶ 57-59.
`
`The “different” capacitor structure recited in the ’616 Patent, on the other hand, is a
`
`“trench-type” cell structure in which the plate electrode and dielectric do not shield the outside of
`
`the storage node, and thus parasitic capacitance is a problem. ’616, 1:13-16 (“The present
`
`invention relates to a semiconductor memory device … whose memory cell portion has a trench-
`
`type stacked cell structure.”), 2:66-3:36 (trench-type stacked cell structure capacitors generate
`
`7
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 13 of 36
`
`larger parasitic capacitance “compared with other cell capacitor structures”); Schubert Decl. ¶ 62.
`
`Rather than positioning the plate electrode between adjacent storage nodes, an interlayer insulating
`
`film (yellow) is interposed between them, as shown by Figure 2 of the ’616 Patent below. See
`
`’616, 1:58-61 (“[T]he trench-type stacked cell structure is a cell structure that utilizes only the
`
`inner surfaces of the trenches defined by the interlayer insulating film 11[] as capacitors.”);
`
`Schubert Decl. ¶ 63.
`
`As explained above, this structure creates unwanted parasitic capacitance because the plate
`
`electrode does not shield the adjacent storage nodes from each other. Id. ¶ 64. Applicant’s
`
`distinction from DeBoer based on the configuration of its plate electrode and its function shielding
`
`adjacent storage nodes from each other was critical to the ’616 Patent’s issuance. See id. ¶¶ 66-
`
`67. Without this distinction, the ’616 Patent would not have issued, as DeBoer otherwise disclosed
`
`the method of claim 1, including staggering capacitors. Id. ¶¶ 56-57. Applicant thus expressly
`
`disclaimed capacitors in which the plate electrode shields adjacent storage nodes from the scope
`
`of the ’616 Patent.5 See id. ¶¶ 58-61.
`
`5 While the ’616 Patent specification also displays an embodiment in which the plate electrode is
`buried in a cavity between storage nodes, see ’616, Fig. 5, that embodiment was withdrawn
`following an election requirement. Ex. 7, 03/30/2005 Requirement for Election at MIPB0000613;
`id., 04/29/2005 Response to Election at MIPB0000617. And even if this embodiment were not
`withdrawn, it was disclaimed during prosecution as addressed above. At a minimum, even
`considering the structure of Figure 5, it is indisputable that the patent applicant disclaimed
`
`8
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 14 of 36
`
`Adopting the plain and ordinary meaning of “forming a plate electrode on the capacitor
`
`insulating film” as Godo Kaisha insists would impermissibly extend the scope of the claim to cover
`
`capacitor structures that were clearly, and repeatedly, disclaimed during prosecution. Id. ¶ 68.
`
`Godo Kaisha cannot now reclaim subject matter that applicant expressly disavowed during the
`
`prosecution history. See Aylus Networks, Inc. v. Apple Inc., 856 F.3d 1353, 1359 (Fed. Cir. 2017)
`
`(“Prosecution disclaimer ‘precludes patentees from recapturing through claim interpretation
`
`specific meanings disclaimed during prosecution.’” (quoting Omega Eng’g, Inc. v. Raytek Corp.,
`
`334 F.3d 1314, 1323 (Fed. Cir. 2003)).
`
`2.
`
`“Wherein the length of a portion where the opposing capacitors are
`overlapperd [sic] in the mask layout is set so that the value of the
`parasitic capacitance between adjacent cell capacitors is not more
`than 10% of the set cell capacitance value”
`
`Godo Kaisha’s Proposed Construction
`Plain meaning
`
`Micron’s Proposed Construction
`“wherein the length of a portion where the
`opposing capacitors are overlapped in the mask
`layout is designed to reduce the value of the
`parasitic capacitance between adjacent cell
`capacitors and
`to prevent
`the parasitic
`capacitance from exceeding 10% of the set cell
`capacitance”
`
`Based on the claim language (“is set so that”) and the patentee’s representations in the
`
`specification and file history, the claim must be limited to capacitors that are staggered for the
`
`purposes of reducing parasitic capacitance and preventing it from exceeding 10% of the set cell
`
`capacitance value. Godo Kaisha’s approach ignores the intrinsic record and should be rejected.
`
`a.
`
`Stagger To Reduce Parasitic Capacitance
`
`Claim 1 recites that the staggered layout “is set so that” the parasitic capacitance is lowered
`
`capacitor structures in which the plate electrode covers a significant portion of the outer surface of
`the storage node.
`
`9
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 15 of 36
`
`to a specific level. ’616, cl. 1; see also Schubert Decl. ¶ 70. The claim language thus requires
`
`staggering for a distinct purpose—namely, to reduce the level of parasitic capacitance between
`
`adjacent cell capacitors. Schubert Decl. ¶ 70; Jansen v. Rexall Sundown, Inc., 342 F.3d 1329,
`
`1333-34 (Fed. Cir. 2003) (finding that claim language included “statement of the intentional
`
`purpose for which the method must be performed” and holding that performing the method “for
`
`some purpose other than [the claimed purpose] is not practicing the claimed method”); Whirlpool
`
`Corp. v. LG Elecs., Inc., 423 F. Supp. 2d 730, 753 (W.D. Mich. 2004) (claim language “fresh water
`
`is added to cool said fabric” required that “fresh water be added with the intention or purpose of
`
`cooling the fabric”).
`
`The specification confirms this interpretation, repeatedly explaining that the purpose of
`
`staggering capacitors is to reduce the parasitic capacitance between trench-type stacked cell
`
`capacitors. See, e.g., ’616, 3:40-46 (“it is an object of the present invention to provide a
`
`semiconductor … that can reduce the parasitic capacitance between trench-type stacked cell
`
`capacitors”), 8:63-67 (“When the parasitic capacitance is more than 10%, it exceeds the set
`
`margin,” resulting in malfunctions.), 9:37-43 (same); Schubert Decl. ¶ 71.
`
`During prosecution, applicant also made clear that the stagger must be designed to reduce
`
`parasitic capacitance. Applicant expressly distinguished DeBoer on this ground, stating:
`
`“Although DeBoer et al. disclose[s] a stagger structure, DeBoer et al. do[es] not teach or suggest
`
`that such a structure can be designed to reduce a parasitic capacitance.” Ex. 7, 10/16/2006
`
`Response at MIPB0000740; see also Schubert Decl. ¶ 73. Applicant further explained that because
`
`DeBoer reduced parasitic capacitance by using a conventional cell capacitor structure, DeBoer did
`
`“not disclose the reduction of a parasitic capacitance or even suggest the feature of sufficiently
`
`reducing the parasitic capacitance such as recited in claim [1].” Ex. 7, 10/16/2006 Response at
`
`10
`
`

`

`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 16 of 36
`
`MIPB0000740; see also Schubert Decl. ¶ 72. Applicant thus acknowledged that there were known
`
`ways in the prior art to reduce parasitic capacitance that had nothing to do with staggering
`
`capacitors (e.g., capacitor structure) and then confined the invention to reducing parasitic
`
`capacitance by staggering. Ex. 7, 10/16/2006 Response at MIPB0000740; Schubert Decl. ¶ 74.
`
`b.
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`Stagger To Prevent Parasitic Capacitance From Exceeding 10%
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`The ’616 Patent additionally requires staggering capacitors to prevent the parasitic-to-set
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`cell capacitance ratio from exceeding 10%. To start, the language of claim 1 recites that the
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`staggered capacitor layout “is set so that the value of the parasitic capacitance between adjacent
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`cell capacitors is not more than 10% of the set cell capacitance value.” ’616, cl. 1. In other words,
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`but for the stagger, the ratio of parasitic-to-set cell capacitance would exceed 10%. See Schubert
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`Decl. ¶¶ 75-76.
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`Further, the only example of claim 1 in the specification supports this reading. See ’616,
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`7:66-9:47; Schubert Decl. ¶ 77. Specifically, Figure 13 (below) shows a circuit with three
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`capacitors (A, B, and C) in parallel.
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`The parasitic capacitance of Capacitor B is the sum of the parasitic capacitance between Capacitors
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`A and B plus the parasitic capacitance between Capacitors B and C, i.e., Cp(B) = Cp(AB) + Cp(BC).
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`’616, 8:45-52. The specification explains that, in an unstaggered layout like that shown in Figure
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`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 17 of 36
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`13, the parasitic capacitance for Capacitor B is 10.6%, that is, 5.3% between Capacitors A and B
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`and an additional 5.3% between Capacitors B and C. Id. The specification then shows that by
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`staggering the capacitors, the respective parasitic capacitance between Capacitors A and B, and
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`between Capacitors B and C, is only 4% of the set cell capacitance. Id., 9:8-20. The parasitic
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`capacitance of Capacitor B thus falls from 10.6% (or greater than 10%) to 8% (or less than 10%)
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`of the set cell capacitance due to the staggered layout (and not other factors that affect capacitance).
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`The specification thus directly teaches that it is staggering, and not other factors, that prevents the
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`parasitic-to-set cell capacitance ratio from exceeding 10%. See ’616, 7:66-9:47; Schubert Decl.
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`¶¶ 78-84.
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`If the “wherein” clause were construed as Godo Kaisha proposes, the claim could extend
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`to capacitor structures in which low parasitic capacitance results from adjusting variables unrelated
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`to a staggered layout. It is indisputable that there were known ways in the prior art to achieve a
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`ratio of parasitic capacitance to set cell capacitance below 10% that had nothing to do with
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`staggering capacitors. Schubert Decl. ¶¶ 35-39, 41, 44-46, 85-86. As the patent explains, parasitic
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`capacitance is impacted by the dielectric constant of the material between adjacent storage nodes,
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`the distance between capacitors, and the use of the plate electrode to shield adjacent storage nodes
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`from each other. See ’616, 8:19-32 & Eq. 2; Schubert Decl. ¶ 87. Changing any one of these
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`variables could produce a parasitic capacitance value of less than 10% of the set cell capacitance.
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`Id. ¶ 88. But none of these variables has anything to do with staggering capacitors. Id.
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`The ’616 Patent applicant chose to claim a 10% parasitic capacitance ratio that results from
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`staggering capacitors, not from adjustments to other variables. Construing the “wherein” clause
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`as Godo Kaisha suggests would improperly read “is set so that” out of the claim, on top of ignoring
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`the specification’s stated purpose of the invention and sole example (see, e.g., ’616, 3:56-60, 9:8-
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`Case 6:20-cv-00178-ADA Document 60 Filed 09/25/20 Page 18 of 36
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`47). See Digital-Vending Servs. Int’l, LLC v. Univ. of Phoenix, Inc., 672 F.3d 1270, 1275 (Fed.
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`Cir. 2012) (explaining “the well-established rule that claims are interpreted with an eye toward
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`giving effect to all terms in the claim … such that words in a claim are not rendered superfluous”
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`(internal quotation marks and citations omitted)); Ajinomoto Co. v. Int’l Trade Comm’n, 932 F.3d
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`1342, 1349, 1351-52 (Fed. Cir. 2019) (finding the “sole specification example” supported the
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`Commission’s construction); Innovative Memory Sys., Inc. v. Micron Tech., Inc., 781 F. App’x
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`1013, 1016 (Fed. Cir. 2019) (claim construction supported by “every embodiment disclosed in the
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`’498 patent specification”). Because the ’616 Patent achieves the 10% ratio by staggering
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`capacitors and not any other variables, claim 1 must be limited to staggering that itself prevents
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`the parasitic capacitance from exceeding 10% of the set cell capacitance.
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`IV.
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`’320 PATENT
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`A.
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`Background of the ’320 Patent
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`The ’320 Patent relates to a sense amplifier for a specific type of DRAM known as
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`“EDRAM, in which DRAM is co-resident with a high-speed CMOS logic circuit.” ’320, 1:8-10,
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`2:17-21. Unlike “commodity” or stand-alone DRAM,6 EDRAM (which stands for “embedded”
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`DRAM) has “the faculties of both the DRAM and” separate “logic LSI.” Id., 1:12-18; see also
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`Ex. 8, Prince at MIPB0003093-94 (explaining that it was known that DRAM can exist as “[a]
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`stand-alone memory device[]” or “embedded in processor chips”); Sechen Decl. ¶¶ 35-37.
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`In DRAM, each bit of data is stored in a capacitor. See Ex. 8, Prince at MIPB0003080-81.
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`A typical DRAM circuit includes a large array of capacitors along with other circuit components
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`needed for memory operation. One such comp