(12) United States Patent
`Tanaka et al.
`
`I 1111111111111111 11111 111111111111111 IIIII IIIII IIIII IIIII 1111111111 11111111
`US006249145Bl
`US 6,249,145 Bl
`Jun.19,2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) LEVEL CONVERSION CIRCUIT AND
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE EMPLOYING THE LEVEL
`CONVERSION CIRCUIT
`
`(75)
`
`Inventors: Kazuo Tanaka, Tokyo; Hiroyuki
`Mizuno, Kokubunji; Rie Nishiyama,
`Akishima; Manabu Miyamoto,
`Kodaira, all of (JP)
`
`(73) Assignees: Hitachi, Ltd.; Hitachi ULSI Systems
`Co., Ltd., both of Tokyo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/209,755
`
`(22) Filed:
`
`Dec. 11, 1998
`
`(30)
`
`Foreign Application Priority Data
`
`Dec. 26, 1997
`
`(JP) ................................................... 9-359273
`
`Int. Cl.7 ................................................ H03K 19/0175
`(51)
`(52) U.S. Cl. ................................. 326/68; 326/68; 326/62;
`326/63
`(58) Field of Search .................................. 326/63, 68, 80,
`326/81, 112, 119, 121, 104, 108; 257/903,
`369
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,559,996 * 9/1996 Fujioka ................................ 395/500
`5,576,639
`11/1996 Park .
`5,659,258 * 8/1997 Tanabe et al.
`......................... 326/68
`5,666,070 * 9/1997 Merritt et al.
`......................... 326/81
`5,939,762 * 8/1999 Lien ..................................... 257/391
`5,952,847 * 9/1999 Plants et al. ........................... 326/80
`FOREIGN PATENT DOCUMENTS
`
`9/1989 (EP) .
`0 334 050
`4-150222 * 5/1992 (JP) .
`4-268818
`9/1992 (JP) .
`* cited by examiner
`Primary Examiner-Michael Tokar
`Assistant Examiner-Vibol Tan
`(74) Attorney, Agent, or Firm-Mattingly, Stanger &
`Malur, P.C.
`(57)
`
`ABSTRACT
`
`In a level conversion circuit mounted in an integrated circuit
`device using a plurality of high- and low-voltage power
`supplies, the input to the differential inputs are provided. In
`a level-down circuit, MOS transistors that are not supplied
`with 3.3 V between the gate and drain and between the gate
`and source use a thin oxide layer. In a level-up circuit, a logic
`operation function is provided.
`
`34 Claims, 27 Drawing Sheets
`
`100
`
`101
`
`outO
`(Q)
`
`102~
`IND-----,
`
`(I)
`
`~-------v~ssf 103
`
`INOB - - - - - - - -~ -
`
`(I)
`
`in1
`in1 b
`
`Micron Ex. 1038, p. 1
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 1 of 27
`
`US 6,249,145 Bl
`
`l"--
`
`201
`
`vss
`
`FIG. 1(a)
`
`PRIOR ART
`
`- - - - - - - - - - - - - .......--------
`
`INO
`
`-0.0-----
`-1 .2 - - -
`·----- 0.0 --------------------------
`
`auto
`
`FIG. 1(b)
`PRIOR ART
`
`Micron Ex. 1038, p. 2
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`U.S. Patent
`
`Jun.19,2001
`
`Sheet 2 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`/LSU
`
`u-203
`
`204"'-
`
`'-..
`(Q)
`
`I
`
`-(I)
`
`vss
`
`in0
`(I)
`
`in0b
`
`OUT0
`(Q)
`
`FIG. 2(a)
`PRIOR ART
`
`in0b -1.2-------... , - - - - - - - - (cid:173)
`in0 -0.0-__, - - - - - - -
`- - -3.3--- --- - - -...--------
`
`OUT0
`
`-0.0----'
`
`FIG. 2(b)
`PRIOR ART
`
`Micron Ex. 1038, p. 3
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`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 3 of 27
`
`US 6,249,145 Bl
`
`100
`
`VDD
`
`101
`
`102~
`I
`
`-
`(Q)
`
`INO
`(I)
`
`vss
`INOB - - - - - - -~
`
`(I)
`
`FIG. 3(a)
`
`auto
`(Q)
`
`INO
`
`-0.0 __ __,
`
`--- 1 2---------- - . - - - - - - - - -
`auto _ o:o---~/
`
`FIG. 3(b)
`
`Micron Ex. 1038, p. 4
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 4 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`300~
`
`/301
`
`302~
`
`r303
`
`LSU
`_/
`
`~..,__---+--- OUTO
`(Q)
`
`-
`(Q)
`
`305
`
`vss
`
`inO-(cid:173)
`(I)
`
`304
`
`inOb
`
`(I)
`
`FIG. 4(a)
`
`inOb
`
`-
`
`1.2 - -~
`
`inO
`
`-0.0----J
`
`OUTO ~:::----------;
`
`FIG. 4(b)
`
`Micron Ex. 1038, p. 5
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 5 of 27
`
`US 6,249,145 Bl
`
`inOb
`
`inO
`
`400~
`
`VDD
`
`401
`
`- - - -4 - - - - OUTO
`
`402
`
`404 /
`
`VSSQ
`
`FIG. 5(a)
`
`inOb -1.2 - - (cid:173)
`
`inO
`
`0.0----J
`
`- - - - 1.2 - - - - - - - - - -
`
`OUTO
`
`- - -2.1------'
`
`FIG. 5(b)
`
`Micron Ex. 1038, p. 6
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 6 of 27
`
`US 6,249,145 Bl
`
`306
`
`VODQ
`
`D.
`~~
`
`300~
`
`/301
`
`302~
`
`~303
`
`OUT0
`
`304
`
`305
`
`VSS
`
`FIG. 6
`
`in0
`
`in0b
`
`Micron Ex. 1038, p. 7
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 7 of 27
`
`US 6,249,145 Bl
`
`VDOQ
`
`330
`
`/301
`
`1303
`
`inOb
`
`inO
`
`304
`
`vss
`
`\
`
`333
`305
`
`OUT0
`
`\_331
`
`FIG. 7(a)
`
`inO
`
`-1.2---------(cid:173)
`
`inOb
`
`--0.0 - -~
`
`- - - -3. 3- - - - - - - - - -
`
`333
`
`OUT0
`
`-0.0 _ __ __,
`
`-3_3 - - - -~+ - -
`
`- - - -0.0- - - - - - - - - - - - - - - - ' - - - - - - - - -
`
`FIG. 7(b)
`
`Micron Ex. 1038, p. 8
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 8 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`500~
`
`502~
`
`/503
`
`--~- 505
`
`vss
`
`509
`
`FIG. 8
`
`in0
`
`506
`
`in0b
`
`in1
`in1 b
`
`Micron Ex. 1038, p. 9
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 9 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`500\
`502~
`
`511
`
`510
`
`inO
`
`506
`
`inOb
`
`508
`
`509
`
`-----<IN1
`
`1-----,
`
`_______ __ ____ __ __ _ __ _ ___ _ _ \ _____ I
`
`\__ 513
`
`FIG. 9
`
`Micron Ex. 1038, p. 10
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 10 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`510
`
`500\.
`502~
`
`506
`
`511
`
`OUTO
`
`I
`I
`
`I
`
`505 1
`507 I
`sag:
`
`I
`I
`
`I
`
`IN1
`
`______ :\_s12
`__________________________ \ ____ _
`
`I
`
`~514
`
`FIG. 10
`
`Micron Ex. 1038, p. 11
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`
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 11 of 27
`
`US 6,249,145 Bl
`
`300~
`
`302~
`
`VDDQ
`
`/301
`303
`/
`
`I
`
`511
`
`510
`
`in0
`
`305
`
`IN1
`
`vss
`
`in0b 1-----------___J
`
`I -----------------------c------
`
`I
`
`515
`
`FIG. 11
`
`Micron Ex. 1038, p. 12
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`
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 12 of 27
`
`US 6,249,145 Bl
`
`510
`
`in0
`
`in0b
`
`VDDQ
`
`300~
`302~
`
`/301
`/303
`
`511
`
`OUTO
`
`IN1
`
`305
`
`vss
`
`313,
`
`- - - - - - - - - - - - - - - - - - - - -~ - - - - - - - -
`516
`
`I
`
`FIG. 12
`
`Micron Ex. 1038, p. 13
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 13 of 27
`
`US 6,249,145 Bl
`
`~------------------------------1
`I
`I
`I
`I
`I
`I
`I
`I
`I
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`521
`
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`. 522
`...+< C>
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`51
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`
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`inOb
`
`I
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`I
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`I
`I
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`513
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`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I •--------------------------c'
`520
`
`FIG. 13
`
`Micron Ex. 1038, p. 14
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 14 of 27
`
`US 6,249,145 Bl
`
`600
`f VDD
`
`601
`
`J-
`
`fVDDQ
`r - - - - - - - - - - - - - - - ,
`I
`I
`-6031-
`I
`I
`I
`I
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`- in0b
`
`IN1
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`I
`I
`I
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`I
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`I
`I
`I
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`
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`I
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`I
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`I
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`I
`I
`I
`I
`I
`
`FIG. 14
`
`Q
`fVDD
`
`602
`
`J-
`
`Micron Ex. 1038, p. 15
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 15 of 27
`
`US 6,249,145 Bl
`
`VDD
`
`701a
`
`VDDQ
`
`VDDQ
`
`603a
`
`PSC
`
`701b
`
`601a
`
`- - 604a
`
`vss
`VDD
`
`vss
`
`602
`
`601b
`
`VDDQ
`
`603b
`
`vss
`VDD
`
`604b
`
`vss
`
`FIG. 15
`
`Micron Ex. 1038, p. 16
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`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 16 of 27
`
`US 6,249,145 Bl
`
`VDD
`
`701a
`
`VDDQ
`
`VDDQ
`
`603a
`
`601a
`
`VBCa
`
`604a
`
`vss
`VDD
`
`vss
`
`602
`
`PSC
`
`701b
`
`VDD
`~702b
`
`601b
`
`VBCb
`
`VDDQ
`
`603b
`
`vss
`VDD
`
`604b
`
`vss
`
`FIG. 16
`
`Micron Ex. 1038, p. 17
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 17 of 27
`
`US 6,249,145 Bl
`
`701a
`
`VDD
`
`/702a
`I /
`
`601a
`
`-- --1.2- ---- - -- -~ - - - - - - - -
`
`701a
`
`-
`
`-2. 1 _ __,
`
`ACTIVE STATE STANDBY STATE
`
`FIG. 17(a)
`
`VDD
`
`702a
`
`701a
`
`601a
`
`-
`
`3.3- - - - - - - - - ~ - - - - - - - -
`
`701a
`
`-0 .0 - - - - '
`
`ACTIVE ST A TE
`
`STANDBY STATE
`
`FIG. 17(b)
`
`Micron Ex. 1038, p. 18
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 18 of 27
`
`US 6,249,145 Bl
`
`VDDQ(3.3v)
`
`VDD(1.2v)
`
`711
`
`701a
`
`VDD
`/702a
`
`VBCa
`
`vss
`
`VDDQ
`
`712
`
`601a
`
`710
`\---v~ss
`712
`(-2.1v)
`
`vss
`
`FIG. 18
`
`Micron Ex. 1038, p. 19
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`

`i,-
`~
`(It
`,1;;;..
`i,(cid:173)
`::0
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`I
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`HIGH-VOLTAGE SECTION vooa+, vsso;
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`: VDD, YSS
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`I
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`
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`: _
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`
`p U
`1
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`'
`' jESD10Hl 01 d
`: ..-----,,________. LS U4f--_
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`)
`L NV 4
`
`Micron Ex. 1038, p. 20
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`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 20 of 27
`
`US 6,249,145 Bl
`
`VDD OR VDDQ
`
`JINV
`
`P14
`
`In
`
`Out
`
`VSS OR VSSQ
`
`FIG. 20(a)
`
`f NAND
`----------< VDDQ
`
`VDD OR
`
`ln1
`
`ln2
`
`Out
`
`VDD OR VDDQ r NOR
`
`VSS OR VSSQ
`
`ln2
`
`FIG. 20(b)
`
`VSSOR
`VSSQ
`
`FIG. 20(c)
`
`Micron Ex. 1038, p. 21
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`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 21 of 27
`
`US 6,249,145 Bl
`
`R2
`
`b
`
`(ESD
`
`a
`
`C
`
`FIG. 20(d)
`
`VDDQ ESD
`j
`.----P16
`
`I
`
`0
`
`N16
`
`VSSQ
`
`FIG. 20(e)
`
`Micron Ex. 1038, p. 22
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`i,-
`~
`(It
`,1;;;..
`i,(cid:173)
`::0
`,I;;..
`N
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`FIG. 21
`
`___ { _______________________ ~-----~
`
`INV1
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`r---------------------,--------------------------------------------------
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`(P-SUB)NMOS: VSSQ, (N-SUB)PMOS: VDDQ
`HIGH-VOLTAGE SECTION VDDQ., vssa,
`
`I _____________________ ----------------
`
`: (N-SUB)PMOS: '{~~-----_1
`1 (P-SUB)NMOS: Vbn
`:
`:voo, VSS
`:
`iow-VOL TAGE SECTION :
`~
`
`....... S10
`
`-
`
`,
`
`Micron Ex. 1038, p. 23
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 23 of 27
`
`US 6,249,145 Bl
`
`INV2
`
`"U"
`
`N1
`
`VDDQ
`
`OG
`
`INV
`
`"L,,
`
`OSP
`
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`
`VSSQ
`
`FIG. 22(a)
`
`VDDQ
`
`OSP ---JI
`
`\..____
`
`FIG. 22(b)
`
`Micron Ex. 1038, p. 24
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 24 of 27
`
`US 6,249,145 Bl
`
`2209
`
`2208
`
`2207
`
`2206
`• • •
`
`2205
`
`2204
`
`2203
`
`2202
`
`TRISTATE
`LOGIC
`OPERATION
`CIRCUIT
`
`TRISTATE
`LOGIC
`OPERATION
`CIRCUIT
`
`LEVEL- LEVEL-
`UP DOWN
`
`LEVEL- LEVEL-
`UP DOWN
`
`PRE-BUFFER
`
`PRE-BUFFER
`
`PULL-UP
`
`PULL-UP
`
`• • •
`
`PROTECTIVE
`CIRCUIT
`
`PROTECTIVE
`CIRCUIT
`
`PMOS
`BUFFER
`
`NMOS
`BUFFER
`
`1/0
`PAD
`
`PMOS
`BUFFER
`
`NMOS
`BUFFER
`
`I
`
`I
`
`1/0
`PAD
`
`J....------------------1f
`
`\_ 2201
`
`FIG. 23
`
`Micron Ex. 1038, p. 25
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 25 of 27
`
`US 6,249,145 Bl
`
`2307
`
`2308
`
`2309
`
`2310
`
`: 2305
`
`2306: 2305
`
`2301
`
`2302
`FIG. 24(a)
`
`VDDQ
`
`2308
`
`VDD
`
`2307
`
`2310
`
`VSSQ
`
`vss
`
`2307
`
`FIG. 24(b)
`
`Micron Ex. 1038, p. 26
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jun.19,2001
`
`Sheet 26 of 27
`
`US 6,249,145 Bl
`
`2407
`
`2408
`
`2409
`
`2410
`
`2411
`
`2401
`
`2402
`
`FIG. 25(a)
`
`VDDQ
`
`2409
`
`) VSSQ
`
`VDD
`
`2407
`/
`
`vss
`
`2407
`
`FIG. 25(b)
`
`Micron Ex. 1038, p. 27
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jun. 19, 2001
`
`Sheet 27 of 27
`
`US 6,249,145 Bl
`
`VDDQ
`
`2409
`
`\
`
`VDD
`
`2407
`I
`
`2409
`~
`
`2409
`~)
`
`VSSQ - - - - -
`
`vss
`
`I
`2407
`
`FIG. 25(c)
`
`Micron Ex. 1038, p. 28
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`US 6,249,145 Bl
`
`1
`LEVEL CONVERSION CIRCUIT AND
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE EMPLOYING THE LEVEL
`CONVERSION CIRCUIT
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to semiconductor
`integrated circuit devices and level conversion circuits, and
`more particularly, to semiconductor integrated circuit
`devices in which a plurality of circuit units driven by a
`plurality of different power supply voltages are formed on a
`single substrate, and to level conversion circuits used in the
`semiconductor integrated circuit devices.
`2. Description of the Related Art
`The trend in manufacturing semiconductor integrated
`circuit devices (such as large-scale integrated circuit
`devices) is to use lower power supply voltages to reduce
`power consumption. Recent integrated circuit devices are
`driven by 1.2 V power supplies, even though input/output
`units (1/0 units), the interfaces with circuits driven by an
`external 3.3 V power supply, are also driven by a 3.3 V
`power supply.
`Additionally, a single semiconductor chip may have two
`or more circuit blocks that are driven by different respective 25
`supply voltages. Such circuit blocks require level conversion
`circuits for raising or lowering voltage levels between circuit
`blocks having different respective supply voltages. FIG. l(a)
`schematically illustrates a circuit diagram of a conventional
`level-down circuit ( a circuit for converting a large-amplitude 30
`signal output by a circuit block operating on a 3.3 V power
`supply, for example, into a small-amplitude signal for input
`to a circuit block operating on a 1.2 V power supply, for
`example), and FIG. 2(a) schematically illustrates a conven(cid:173)
`tional level-up circuit (a circuit for converting a small- 35
`amplitude signal output by a circuit block operating on a 1.2
`V power supply, for example, into a large-amplitude signal
`for input to a circuit block operating on a 3.3 V power
`supply, for example).
`In FIG. l(a), VDDQ represents a 3.3 V input, VDD is a 40
`1.2 V power supply, and VSS a reference, or ground,
`potential. Thus, VDDQ is a large-amplitude signal, and the
`output is a small-amplitude signal based upon the VDD
`potential.
`In FIG. l(a), a P-type MOS (PMOS) transistor 200 and an 45
`N-type MOS (NMOS) transistor 201 are shown, connected
`to receive on their respective gates an input INO having an
`amplitude of 0.0 V when low and 3.3 V when high, for
`example. INO is thus considered to be a large-amplitude
`signal input. The circuit shown in FIG. l(a) outputs a 50
`small-amplitude signal out0 having an output value of 1.2 V,
`for example, based upon the power supply VDD. FIG. l(b)
`illustrates the respective waveforms of IN0 and out0.
`Since, in the PMOS transistor 200 and NMOS transistor
`201, a maximum voltage of 3.3 V may be applied between 55
`gate and source, PMOS transistor 200 and NMOS transistor
`201 are formed with a thick gate oxide layer.
`In FIG. 2(a), the level-up circuit is constituted by PMOS
`transistors 202,203 and NMOS transistors 204,205. Small(cid:173)
`amplitude amplitude input signals in0 and in0b are comple- 60
`mentary dual rail signals. Output signal OUT0 is a large(cid:173)
`amplitude output signal of, for example, 3.3 V, based upon
`power supply VDDQ. MOS transistors 202-205 each have
`a thick gate oxide layer similar to that of the MOS transistors
`200, 201 of FIG. l(a). FIG. 2(b) illustrates the respective 65
`waveforms of input signals in0, in0b and output signal
`OUT0.
`
`2
`In a conventional level-down circuit such as that shown in
`FIG. l(a), the logic threshold is typically VDD/2, or close to
`0.6 V. Large-amplitude input signals, because their ampli(cid:173)
`tudes are relatively large, generally tend to produce noise of
`5 a type such that the ground level fluctuates. When the ground
`level fluctuates more than 0.6 V, the signal is judged
`erroneously to be a high level in the circuit of FIG. l(a),
`resulting in a low-level output at out0. Hence, in the con(cid:173)
`ventional level-down circuit, as the VDD supply decreases
`10 in voltage, the logic threshold becomes lower, and an
`incorrect logic value may be produced at the output out0 in
`the presence of even very small noise.
`In the level-up circuit of FIG. 2(a), when the VDDQ
`power supply is on but the input power VDD is off, the
`15 values of in0 and in0b are undefined, causing a through(cid:173)
`current to flow between VDDQ and VSS. Hence, in a system
`where VDD is produced from VDDQ by a DC-DC
`converter, a heavy load is exerted on the VDDQ power
`supply, causing a phenomenon, in which the VDD power
`20 supply cannot be turned on. If the VDD power supply cannot
`be turned on, in0 and in0b remain undefined, leaving the
`system permanently unable to start normally.
`Not only when the power is turned on, but while the
`VDDQ power supply is on, it is impossible to cut off the
`VDD power supply because the cutoff of the VDD power
`renders the values of in0 and in0b undefined, causing a
`through-current to flow through the VDDQ and resulting in
`a significant increase in power consumption by the system.
`Furthermore, the conventional input/output circuit unit
`that includes an output buffer circuit unit also has a similar
`problem to that discussed above with respect to the level
`conversion circuit unit. When the VDDQ power supply is
`turned on but the VDD power is not, the input signal value
`of the output buffer of the input/output circuit becomes
`undefined, causing a through-current to flow between
`VDDQ and VSS of the output buffer circuit.
`
`SUMMARY OF THE INVENTION
`
`An object of this invention is to provide a level-down
`circuit that does not readily produce an erroneous output in
`the presence of ground level fluctuation in large-amplitude
`input signals, and to provide a semiconductor integrated
`circuit device employing the level-down circuit.
`Another object of this invention is to provide a level
`conversion circuit in which no through-current flows
`between a high-voltage power supply and a ground power
`supply, and to provide a semiconductor integrated circuit
`device employing the level conversion circuit, even when
`the high-voltage power supply is turned on but the low(cid:173)
`voltage power is not.
`Another object of the present invention is to provide a
`semiconductor integrated circuit device including a plurality
`of circuit blocks powered by different respective supply
`voltage levels, and level conversion circuits according to the
`invention for translating voltage levels between the various
`circuit blocks.
`To achieve these and other objects of the invention, and to
`solve problems of the prior art, the present invention
`includes one or more of the following features in the various
`embodiments discussed in greater detail below:
`(1) The input to a level-down circuit is provided differ(cid:173)
`entially;
`(2) In the level-down circuit, MOS transistors that do not
`receive 3.3 V between gate and drain or between gate
`and source have thin gate oxide layers;
`
`Micron Ex. 1038, p. 29
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`US 6,249,145 Bl
`
`3
`(3) A level-up circuit has a logical operation function; and
`(4) An output buffer circuit provided with a level-up
`circuit includes means preventing a through-current
`from flowing through the output buffer when only one
`of the MOS transistors of the output buffer is turned on.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. l(a) and l(b) respectively show a circuit diagram
`of a conventional level-down circuit and its operation wave(cid:173)
`form diagram.
`FIGS. 2(a) and 2(b) respectively show a circuit diagram
`of a conventional level-up circuit and its operating wave(cid:173)
`form diagram.
`FIGS. 3(a) and 3(b) respectively show a level-down
`circuit according to a preferred embodiment of the present
`invention and its operating waveform diagram.
`FIGS. 4(a) and 4(b) respectively show a circuit diagram
`of a preferred embodiment of a level-up circuit of the present
`invention and its operating waveform diagram.
`FIGS. 5(a) and 5(b) respectively show a circuit diagram
`of another embodiment of a level-up circuit of the present
`invention and its operation waveform diagram.
`FIG. 6 is a circuit diagram of a further embodiment of a 25
`level-up circuit of the present invention.
`FIGS. 7(a) and 7(b) respectively show a circuit diagram
`of a further embodiment of a level-up circuit of the present
`invention, and its operating waveform.
`FIG. 8 is a diagram showing a circuit configured by 30
`adding a logic operation function to the level-up circuit of
`FIG. 4(a).
`FIG. 9 shows an example of providing the level conver(cid:173)
`sion circuit of FIG. 8 with an output fixing function.
`FIG. 10 shows another example of applying the level
`conversion circuit of FIG. 8 with an output fixing function.
`FIG. 11 shows a further example of a level-up circuit
`having an output fixing function.
`FIG. 12 shows still another example of a level-up circuit
`having an output fixing function.
`FIG. 13 shows an example of a level-up circuit having an
`output fixing function of a type that holds the level(cid:173)
`converted output.
`FIG. 14 shows a system using a level conversion circuit
`according to the present invention.
`FIG. 15 shows a system using a level conversion circuit
`of this invention when a circuit block comprising low(cid:173)
`threshold MOS transistors is divided into two.
`FIG. 16 shows the system of FIG. 15 with a substrate bias
`control added.
`FIG. 17(a) shows an embodiment for controlling a power
`switch of FIGS. 15 and 16, and FIG. 17(b) shows an
`example of a method of controlling the power switch of
`FIGS. 15 and 16 when a low-threshold MOS transistor is
`used for the power switch.
`FIG. 18 shows an embodiment for generating a gate
`voltage for the embodiment shown in FIG. 17(a).
`FIG. 19 shows an example of an input/output circuit
`connected to the external terminal (pin) of an IC
`(semiconductor integrated circuit) according to a preferred
`embodiment of the present invention.
`FIG. 20(a) shows an example of an INV used in the
`embodiment of FIG. 19, FIG. 20(b) shows an example of a
`NAND circuit used in the embodiment of FIG. 19, FIG.
`20(c) shows an example of a NOR circuit used in the
`
`4
`embodiment of FIG. 19, FIG. 20(d) shows an example of an
`electrostatic protective device used in the embodiment of
`FIG. 19, and FIG. 20(e) shows an example of another
`electrostatic protective device used in the embodiment of
`5 FIG. 19.
`FIG. 21 shows an example of an input/output circuit that
`renders unnecessary circuit portions of FIG. 19 that are
`substantially inoperable.
`FIGS. 22(a) and 22(b) respectively show a further
`10 embodiment of the circuit for preventing a through-current
`from flowing through the output buffers PBl and NBl at the
`time of power supply turn-on, and an operation waveform
`therefor.
`FIG. 23 shows an example of the layout of the input/
`output circuit of FIG. 19.
`FIG. 24 shows an example of the configuration of an
`inter-power supply protective device.
`FIG. 25 shows another example of the configuration of an
`20 inter-power supply protective device.
`
`15
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`In the following description, insulated gate field-effect
`transistors (FETs) and metal-insulator semiconductor FETs
`represented by the metal oxide semiconductor FET
`(MOSFET) are referred to simply as MOS transistors. An
`N-channel MOS transistor whose majority carriers are elec-
`trons is referred to as an NMOS transistor, and a P-channel
`MOS transistor whose majority carriers are holes is referred
`to as a PMOS transistor.
`A "threshold voltage" (Vth) qualitatively denotes the
`voltage difference between the gate and the source when the
`35 drain current starts to flow. Quantitatively, a measured
`threshold voltage can be obtained by plotting several points
`in a MOS transistor saturated region in which the drain
`current is expressed by the square curve of the difference
`between the gate-source voltage and the threshold voltage.
`40 The threshold voltage depends on certain parameters, such
`as the concentration in the semiconductor substrate surface
`where an inversion channel is induced and the thickness of
`the gate insulating layer. Where comparisons of magnitudes
`of threshold voltage values are made in the following
`45 embodiments, it should be understood that both PMOS
`transistors and NMOS transistors operate in enhancement
`mode, and their threshold voltage values are compared as
`absolute values. If process parameters that determine the
`channel conductance ~ are the same, a MOS transistor
`50 having a greater drain current for the same gate-source
`voltage may be considered to have a lower threshold
`voltage, assuming that the channel width W and the channel
`length L are the same.
`Although the source and drain of a MOS transistor are
`determined essentially by the bias of the circuit, in the
`accompanying drawings, the source of a PMOS transistor is
`labeled by an arrow pointing toward the gate electrode, and
`that of an NMOS transistor with an arrow pointing away
`from the gate electrode. An electrode whose bias direction
`60 changes during operation (such as a transmission gate) is
`labeled by a bi-directional arrow. When the source and drain
`are generally noted without any distinction, they are called
`source-drains.
`In many integrated circuits, the gates and source-drains of
`65 MOS transistors that need large conductances are often
`commonly connected (the current paths between the sources
`and drains are connected in parallel) or are distributed
`
`55
`
`Micron Ex. 1038, p. 30
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`US 6,249,145 Bl
`
`5
`equivalently in many cases. In this specification, such MOS
`transistors are represented by a single MOS transistor unless
`otherwise specifically stated. Likewise, where a plurality of
`MOS transistors have current paths between source and
`drain connected in series and gates applied with the same
`signal, such MOS transistors are represented by a single
`MOS transistor in this specification unless otherwise stated.
`FIG. 3(a) shows a circuit diagram of a level-down circuit
`according to a preferred embodiment of the present inven(cid:173)
`tion. FIG. 3(b) illustrates basic operation waveforms of the
`circuit. In FIG. 3(a), 3.3 V (large-amplitude) complementary
`dual rail input signals are represented by IN0 and IN0B. The
`1.2 V (small-amplitude) output signal is denoted by out0.
`Throughout the specification, and particularly with reference
`to FIGS. 1-13, signals denoted by capital letters (IN, OUT) 15
`are 3.3 V (large-amplitude) signals, and signals denoted by
`lower-case letters (in, out) are 1.2 V (small-amplitude)
`signals.
`In FIG. 3(a) NMOS transistors 102, 103 have a thick gate
`oxide layer similar to that of NMOS transistor 201 shown in 20
`FIG. l(a). PMOS transistors 100, 101 have thin oxide layers
`by comparison. Voltages applied between the gate and drain
`and between the gate and source of PMOS transistors 100,
`101 are small-amplitude voltages VDD (1.2 V) at most, and
`thus the PMOS transistors 100, 101 do not require gate oxide 25
`layers having the large dielectric strength of the gate oxide
`layers of NMOS transistors 102, 103, which receive large(cid:173)
`amplitude signals. Hence, the PMOS transistors 100, 101
`have the smaller gate oxide layer thicknesses, and (though
`not limited) lower threshold values than those of NMOS 30
`transistors 102, 103. Using PMOS transistors 100, 101 with
`thin gate oxide layers makes the circuit capable of higher(cid:173)
`speed operation.
`In this embodiment, because the circuit receives differ-
`ential inputs at IN0 and IN0B, erroneous logic levels are not
`output from out0 even in the presence of ground level
`fluctuating noise. Moreover, this circuit is not easily influ(cid:173)
`enced by noise even when VDD is lowered.
`Another advantage of the present embodiment is that the 40
`manufacturing process can be simplified by setting the gate
`oxide layer thickness and threshold voltage of PMOS tran(cid:173)
`sistors 100, 101 equal to those of MOS transistors that form
`the circuit to which the output auto is connected, and by
`setting the gate oxide layer thickness and threshold voltage 45
`of NMOS transistors 102, 103 equal to those of the MOS
`transistors forming a circuit that provides the inputs IN0,
`IN0B. For example, NMOS transistors 102, 103 may be
`output stage MOS transistors of an 1/0 circuit or the MOS
`transistors used in the protective circuit.
`FIG. 4(a) shows an example of a circuit diagram for a
`level-up circuit, and FIG. 4(b) shows example operation
`waveforms for the-circuit of FIG. 4(a). Signals in0 and in0b
`represent complementary dual rail small-amplitude input
`signals of VDD (1.2 V). The circuit provides a 3.3 V 55
`(large-amplitude) output at OUT0.
`PMOS transistors 300, 301, 302, 303 have thick gate
`oxide layers similar to PMOS transistor 200 of FIG. l(a).
`NMOS transistors 304,305 also have thick gate oxide layers
`like that of NMOS transistor 201 of FIG. l(a). As shown in 60
`FIG. 4(b), the logic level of in0 is increased in amplitude for
`output at OUT0. Because of the differential inputs, this
`circuit features strong immunity to noise.
`FIGS. 5(a) and 5(b), like FIGS. 4(a) and 4(b), show a
`level-up circuit diagram and its associated operation wave- 65
`forms. However, while the circuit of FIG. 4(a) converts a 1.2
`V-amplitude signal spanning VDD (1.2 V) to VSS (0 V) into
`
`6
`a 3.3 V-amplitude signal spanning VDDQ (3.3 V) to VSS (0
`V), the circuit of FIG. 5(a) converts a 1.2 V-amplitude signal
`spanning VDD (1.2 V) to VSS (0 V) into a 3.3 V-amplitude
`signal spanning VDD (1.2 V) to VSSQ (-2.1 V). VSSQ is
`5 a negative power supply of -2.1 V. Input signals in0 and
`in0b are small-amplitude complementary dual rail input
`signals. Output OUT0 has a 3.3 V amplitude (large(cid:173)
`amplitude) ranging between 1.2 V and -2.1 V. PMOS
`transistors 400, 401, 402, and 403 are thick gate oxide layer
`10 transistors similar to PMOS 200 of FIG. l(a). NMOS
`transistors 404, 405 are thick gate oxide layer transistors
`similar to NMOS transistor 201 of FIG. l(a).
`As shown in FIG. 5(b), the logic level of in0 is increased
`in amplitude and output to OUT0. Because of the differential
`inputs, this circuit features strong immunity to noise, like
`that of FIG. 4(a).
`Since the circuits of FIGS. 4(a) and 5(a) have a comple-
`mentary relationship, features of the level conversion for
`both embodiments will be described on the basis of FIG.
`4(a) alone. However, such features, including the expansion
`of the voltage range, are equally applicable to the circuit of
`FIG. 5(a), albeit in the negative direction in the circuit of
`FIG. 5(a).
`FIG. 6 illustrates a level-up circuit which is a modification
`of the circuit of FIG. 4(a), to be used at a lower VDD
`voltage.
`FIG. 6 uses an additional PMOS transistor 306 as a
`current source. When the voltage of VDD is decreased with
`VDDQ fixed, the "on" currents (the current existing when
`the potential differences between the source and gate of
`NMOS transistors 304, 305 are VDD) are smaller than the
`"off" currents (the current existing when the potential dif(cid:173)
`ferences be