492
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`Fully Boosted 64K Dynamic RAM with Automatic
`and Self-Refresh
`
`MAKOTO TAPJIGUCHI, TSUTOMU YOSHIHARA, MICHIHIRO YAMADA, KAZUHIRO SHIMOTORI,
`TAKAO NAKANO, AND YOSHIMI GAMOU
`
`Abstract–A novel high-speed low-power 64K dynamic RAM with
`enough margin has been attained using a double polysilicon and 3-#m
`process technologies. To obtain a low soft error rate below 1 X 10%
`errors per device hour without sacrificing the high-speed and low-power
`operation, some novel approaches are proposed in the circuit and device
`desigus.
`In particular,
`fully boosted circuits and the Hi-C cell structure
`with polyailicon bit tine are designed to increase the margin of the single
`5-V power supply 64K dynamic RAM.
`The fabricated device provides a typical access time of 90 ns and an
`operating power of 190 mW at 25°C. Also, the design features of the
`automatic and self-refresh functions on the same chip are described.
`
`I.
`
`INTRODUCTION
`
`T HE dynamic random access memory (RAM) has advanced
`
`rapidly in the last decade from 1K to 64K bit capacities.
`This progress has been realized by the evolution in the device,
`process, and circuit design technologies.
`Since the scaled-down
`et al. [1], one
`device approach was proposed
`by Dennard
`main development
`aim has been the scaled-down MOS structure
`as well as a fine pattern process. However, several technological
`breakthroughs
`[2],
`[3] were needed to establish an industrial
`standard
`64K bit dynamic RAM [4] - [7].
`Especially,
`the
`scaled-down
`approach
`results
`in the soft error problem [8]
`because of a smaller charge capacity
`in the memory cell.
`It
`was reported
`that
`the soft error problem was improved using
`the new techniques
`of the boosted word line circuit,
`the Hi-C
`cell structure
`and the polysilicon bit line [9] -[11].
`This paper presents
`the design of a 64K dynamic RAM oper-
`ated with a single 5-V supply.
`Section H describes
`the fully boosted sense-refresh amplifier
`circuit and the innovative boosted word line circuit which have
`been developed to improve the soft error problem without
`the
`degradation
`of the performance.
`In addition,
`the automatic
`and self-refresh functions, which give a wide application to the
`small memory system, are described. A new initial reset circuit
`for the refresh control circuit has been used to solve a high VCC
`current problem during the initialization when the Vcc supply
`voltage is turned orL
`is given in Section
`A description
`of the process technology
`III.
`In order
`to improve the soft error problem,
`the new cell
`structure, which consists of the Hi-C cell and the polysilicon
`bit
`line,
`is proposed.
`The 3-~m design rule is employed
`to
`achieve a high performance
`and a small die size,
`
`Manuscript received March 5, 1981; revised April 20, 1981.
`The authors are’ with J-S Research and Development Laboratory,
`MitsubishiElectric Corporation, 4-1 Mizuhara,Itami, Hyogo 664, Japan.
`
`‘wL?.!”-vcc L--
`
`!Z5
`
`0~
`
`*C
`
`Oy
`
`Op
`
`Fig. 1.
`
`Sense-refreshamplifier and its timing diagram.
`
`presents
`IV
`Section
`RAM. The soft error
`hour has been achieved.
`
`of the 64K dynamic
`the performance
`rate less than 1 X 10-6 errors per device
`
`II. CIRCUIT DESIGN
`A. Fully Boosted Sense-Refresh Amplifier
`The abbreviated
`sense-refresh amplifier circuit and its timing
`diagram of a 64K dynamic RAM are shown in Fig. 1. In order
`to reduce
`the sensitivity to soft errors
`induced by an alpha-
`particle irradiation
`and to obtain the maximum input signal to
`the sense amplifier,
`the signals of the full-power
`supply voltage
`VCClevel should be written and stored in the memory cell.
`For overcoming
`this problem, main clocks
`related with an
`operation of the sense amplifier are boosted above Vcc level and
`the active pull-up circuit
`for each bit line in the sense amplifier
`circuit
`is used. The cell plate voltage VGG is internally gener-
`ated and boosted
`above *VCCto store the full Vcc level into
`the memory cell.
`In Fig. 1, the bit lines are precharged to Vcc level by the clock
`@p which is greater than Vcc + VTH. OWLand @wD are defined
`as the word line pulse and the dummy word line pulse, respec-
`
`0018-9200/8 1/1000-0492$00.75
`
`01981 IEEE
`
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`TANIGUCH1et al.: 64K DYNAMICRAM WITH AUTO/SELF-REFRESH
`
`493
`
`=81..,’’”--’(F
`
`------
`
`--------
`
`-2.0 L
`0
`
`10
`
`20
`
`30
`
`40
`
`50
`
`60
`
`70
`
`4
`80
`
`Time(n
`see)
`Fig. 3. Simulated waveform of boosted word line clock generator.
`
`:-
`
`+-
`
`‘X=L
`‘= m
`
`‘Xt
`
`‘As
`
`~
`
`Input
`
`Fig. 4. Block diagram of automatic and self-refresh circuit.
`
`The rise time of ‘$WLis
`boosted word line clock generator.
`bootstrap
`circuit and the
`faster
`than that of the conventional
`maximum peak current
`of @x becomes
`smaller
`than that of
`the conventional
`one by 40 percent
`since there is no need for
`charging the capacitor Cl.
`capaci-
`of the switched bootstrap
`The analogous
`technique
`tor circuit has been employed for @p and @Y to obtain a high
`performance.
`
`C. Automatic and Sel$Refresh Circuit
`The automatic
`and self-refresh circuits consist of the refresh
`control
`circuit,
`the refresh address counter
`and the timer cir-
`cuit
`for
`the self refresh function
`as shown in Fig. 4. These
`circuits are controlled by the external REF signal.
`The aut~tic
`refresh operation
`is initiated by bringing the
`external REF signal
`low after all bit
`lines are precharged by
`RAS signal. This mode is considered
`as a standard operation
`,—
`just
`like RAS-only refresh, except
`that additional
`row addresses
`from’ an external
`counter
`are no longer necessary. At the end
`of
`the automatic
`refresh cycle,
`the internal
`refresh address
`counter will be automatically
`incremented.
`low, the 64K dy-
`As long as the external=
`signal
`remains
`namic RAM will
`refresh itself,
`since the internal
`sequence
`repeats
`asynchronously
`every 8-16 us by the internal
`timer
`circuit. This asynchronous
`operation brings much complexity
`to the circuit design.
`In particular,
`the initialization
`of the
`refresh control circuit needs careful consideration.
`
`~CC level clock
`-— —____—
`
`generator
`.——=
`
`Switched
`-————
`
`copacitor
`bootstrap
`————— —___m
`
`line
`Word
`-————7
`
`From
`~Row Oecoder
`
`I
`~
`
`I1
`
`.–––––J
`
`L–.
`
`.––––__–––.
`
`.__;
`
`———-———,-—————J
`Delay
`circuit
`
`IL
`
`–––______J_J
`
`IIL
`
`Fig. 2. Boosted word line clock generator.
`
`signal
`input
`the sense amplifier
`to maximize
`In order
`tively.
`and restore the full high level of F&, @~L, and f#wD are boot-
`strapped.
`The voltage swing of these pulses exceeds greater
`than Vce + VTH.
`The level of the coupler clock OT should be above Vcc + VT~
`before sensing so that Vcc level is successfully transferred from
`the bit
`line to the main flip-flop,
`and OT dips low during the
`initial sensing to isolate the main flip-flop from the bit line with
`a large capacitance.
`In a similar way, the column decoder out-
`put signal @y is also bootstrapped
`and the resulting voltage swing
`than Vcc + VT~ which enables
`becomes greater
`to write the
`full Vcc level
`into the memory
`cell. Thus, most of control
`pulses used in the
`sense amplifier of Fig. 1 has been boot-
`than Vcc + VTH. In particular,
`strapped
`to the level greater
`the novel bootstrap
`circuit, which is described in the following
`Section II-B, has been employed in the clock pulse generators
`of @wL, @wD, $P, and 4Y.
`
`B., Boosted WordLine Clock Generator
`Fig. 2 shows the abbreviated
`boosted word line clock gener-
`ator which consists of the Vcc level clock generator,
`the novel
`switched
`bootstrap
`circuit,
`the delay circuit
`and the row
`decoders.
`a higher voltage level than the supply voltage, a
`To generate
`circuit uses the direct coupling capacitor Cl be-
`conventional
`tween OX and rj~. However, during the time in which $x rises
`to Vcc level, (2’1acts only as a heavy-load capacitor
`to @X. So,
`the rise time of @X becomes
`slow and the large peak current
`flows from @,y to OB through the capacitor C’l.
`In order
`to solve these problems,
`the novel switched boot-
`strap capacitor
`including Cl
`and C2 has been employed
`as
`shown in Fig. 2. During the precharge period,
`the node A is
`to the Vcc - VTH level and the device Q1 isolates
`precharged
`Cl-to-@X path. As @RASgoes high,
`the node A is charged to
`the Vcc level
`through
`the device Q3. As OX rises,
`the node
`B will get charged to” Vcc through the pass transistor Q2. At
`that
`time,
`since the device QI
`is still turned off,
`the capaci-
`tance Cl does not act as the load capacitor
`to @x. After some
`delayed time, d~ goes high and shuts off Q2, Q3, and Qe. The
`node B is isolated from ‘Ox so that when OB goes high,
`the
`node B bootstrapped
`above the level of Vcc + 2 VTH turns on
`the transistor QI strongly.
`Thus @Bboosts ox to higher level
`above Vcc through Cl as the transistor Q1 turns on.
`Fig. 3 shows
`the computer
`simulation waveforms
`
`the
`
`of
`
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`

`494
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`Vcc
`
`Poly Sil
`
`Al word line
`
`=O’’’O’”’’O”)s(H, -C)
`
`GATE OXIDATION
`
`PROCESS
`
`FLOW
`
`Fig. 7. Hi-C cell process sequence.
`
`Fig. 8. Operating waveform of 64K dynamic RAM for 5.0 V and 25”C.
`
`The Hi-C process sequence which is added to the conventional
`process is shown in Fig. 7.
`It requires the additional
`two pro-
`cess steps of both lithography
`and ion implantation.
`The p-
`and n-type doses were determined
`considering the breakdown
`voltage and the refresh characteristics.
`By adopting the Hi-C
`cell structure,
`the storage cell capacitance
`becomes about 30
`percent
`larger than that of the conventional
`one.
`The soft error occurs mainly at the bit
`lines while the sense
`amplifier circuits are operating.
`Therefore,
`the first polysilicon
`layer
`is used for the bit
`line in place of the n+-diffusion layer
`as shown in Fig. 6 to reduce
`the collection
`area of alpha-
`It follows that
`the collection area
`particle-induced
`electrons.
`becomes
`about half and the storage cell capacitance
`becomes
`10 percent
`larger than that of the n+-bit line.
`
`IV. ELECTRICAL CHARACTERISTICS
`A. Access Time and Power Dissipation
`from the memory chip
`Fig. 8 shows the output waveforms
`along with the RAS and CAS signals. The row access time
`the typical condition of Vcc = 5 V and Ta =
`was 90 ns under
`25”C. Fig. 8 also shows the active operating current waveforms
`from Vcc to VSS. The application
`of the switched bootstrap
`gives a lower Vcc peak current, which results
`capacitor
`in
`easier design of the memory
`boards. A typical active power
`of 190 mW at 260 ns cycle time and a standby power of 17
`mW were achieved.
`
`Fig. 6. Cross-sectionalview of Hi-Cmemory cell.
`
`LITHOGRAPHY(1
`
`)
`
`B+ IMPLANTATION
`
`DRIVE -I N(inN2)
`
`LITHOGRAPHY(2)
`
`A’sIMPLANTATION
`
`S? IV E–IN (In N2)
`
`; z
`
`0
`z
`
`t>z
`
`0
`.~.
`
`--l
`
`A
`
`—
`
`.
`
`.
`
`~J
`
`-.!j’-~;~~
`
`!11
`
`Tcc
`
`TGG
`
`~R
`
`to tl
`
`t2t3
`
`Fig,
`
`5. Reset pulse generator circuit
`
`for initial-
`Fig. 5 shows the novel reset pulse generator circuit
`izing the refresh control
`circuit. When the Vcc supply volt-
`age is turned
`on, an excessive Vcc current
`flows during the
`initialization.
`In order
`to prevent
`the imperfect
`initialization,
`the signal @R is selectively fed to the refresh control
`circuit
`(Fig. 4). The gate electrode of the device Q,
`is connected with
`VGG, which is an internally generated voltage supply commonly
`used for
`the memory
`cell plate.
`The transistor Q3 plays an
`important
`role to provide hysteresis characteristics
`as described
`in the following.
`After Vcc is applied at time to, OR starts to rise at time tl
`through
`the pull up device Qg. Then the generator of VGG
`becomes active at time t2.However, during the interval t~ - t3,
`OR continues
`to go high since some delay time is required for
`charging the node A to a high state. When Vec reaches 3.5 V
`(time t,), @R falls rapidly to the low level. The trigger level of
`3.5 V is set by adjusting the size of the transistor
`combination
`Q -Qs
`appropriately.
`And the pulse duration of OR is long
`enough to initialize the refresh control circuit.
`On the other hand,
`the generation of the 4R pulse is prohib-
`ited when the supply voltage is turned off. This is because the
`device Q3 acts as a pull up resistor of the node A. Thus, during
`the minimum Vcc voltage is not
`the memory operation
`cycle,
`limited by this reset circuit.
`
`III. FABRICATION
`
`technology was
`The advanced n-channel double polysilicon
`used to fabricate
`the 64K dynamic RAM. The 3-~m design
`rule was employed
`and the effective channel
`length of 2 pm
`was precisely controlled
`by plasma etching and the arsenic ion
`implantation
`to the source and drain regions.
`The memory cell size was chosen to be 200 Pmz and its cross
`section is schematically
`shown in Fig. 6.
`In order
`to increase
`the storage cell capacitance
`and improve
`the soft error
`rate,
`the doubly implanted Hi-C (high-capacity)
`cell structure
`[11 ]
`was adopted.
`The capacitance of the p-n junction
`formed just
`beneath
`the gate electrode by ion implantations
`is in parallel
`to the gate capacitor
`and contributes
`to the increase of the
`storage cell capacitance.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 19:52:06 UTC from IEEE Xplore. Restrictions apply.
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`
`

`

`TANIGUCHI et al.: 64K DYNAMICRAM WITH AUTO/SELF-REFRESH
`
`495
`
`{,1{,t
`“(.;,
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`‘,:
`
`,,*
`
`PAS’S’”
`
`7 00
`
`(j
`
`()(2
`
`4 00
`
`Fig. 9. Shmoo plot of column addressoaccesstime (tCAC) for varying
`VCCat 75 C.
`
`20
`
`I
`
`1
`
`I
`
`I
`
`I
`
`1
`
`I
`
`1
`
`I
`
`Ta=500C
`
`To=25° C
`
`(5 –
`
`.2
`
`(y 10 —
`
`wz +
`
`5 –
`
`Fig. 10. Interval of internal
`
`timer for self-refresh function versus supplY
`voltage VCC.
`
`Vcc (volt)
`
`Fig. 9 shows a shmoo plot of the cohrmn access time (tcAc)
`as a function of the Vcc. For the worst condition of Vcc =4.5
`V and Ta = 75”C, the column access time was measured to be
`50 ns.
`
`function of Vcc. For the worst case of Vcc =4.5 V and Ta =
`75”C, all the data are refreshed in every 1.8 ms (=14 ps X 128
`cycles). The power dissipation in this mode is only 27 mW at
`Vcc = 5.5 V and Ta = 25”C.
`
`B. Refresh Function
`as described in
`There are two types of the REF functions
`Section II. When the external REF input
`is remained at the
`low level for more than 16 PS during the external RAS input
`being high, the memory chip functions
`in the self-refresh mode.
`This mode makes it possible to maintain the stored data with-
`out an external
`refresh address counter
`for a battery back-up
`mode.
`The interval
`for refreshing the stored data ‘in the self-
`refresh mode
`is determined
`by the timer
`fabricated
`on the
`same chip (Fig. 4).
`Fig. 10 shows the experimental
`
`interval of the timer as a
`
`C. Soft Error Characteristics
`soft
`From the recent
`studies on the alpha-particle-induced
`error,
`it is clear that
`the soft error
`rate is strongly dependent
`on the stored charge level in the memory cell. Theoretically,
`the circuit
`technique
`of the boosted word line leads to more
`effective utilization
`of the stored charge. Therefore,
`the appli-
`cation of the boosted word line is predicted to give significant
`improvement
`in soft errors compared with the unboosted word
`line. To evaluate this effect,
`the pumping signals of the word
`line such as ‘#F and f#IB(Fig. 2) were disabled by cutting these
`signal lines with laser beam. A comparison was made between
`
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`

`496
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO, 5, OCTOBER 1981
`
`104INI
`
`0
`
`(b) unboosted
`
`(a) boosted
`
`103
`
`102
`
`10
`
`1
`
`.<
`
`:
`x
`
`~
`
`k w
`
`0.1
`
`3456789
`
`0
`
`(v)
`Vcc
`Fig. 11. Comparison of soft errors between boosted word line and
`unboosted word line.
`
`106
`
`105
`
`104
`
`source ‘41Am 8.4pCi
`radiation
`1. specimen 5mm
`distance
`Vcc =5. OV
`
`t
`
`1
`
`(a)
`
`I
`i
`
`\ k
`
`%“%7
`.
`
`,,
`
`6
`
`I
`
`1
`
`10
`
`100
`
`1000
`
`tcycle
`
`(,us)
`
`\\
`
`\
`
`103 -
`
`102
`
`10
`
`4 I
`01
`
`Fig. 12. Measured soft error bits of 64K dynamic RAM, dependence
`of cycle time for (a) conventional cell, (b) Hi-C cell with n+-diffused
`bit line, and (c) Hi-C cell with polysilicon bit line.
`
`rodiar, on source 241 Ame.4pc!
`distance
`IO specimen 5mm
`tcycl,
`= Ips
`
`l
`
`(c)
`
`(a)
`
`(b)
`
`106-
`
`105 -
`
`k
`‘- 104
`
`2 103
`.—
`n
`
`:
`
`G
`
`102
`
`10
`
`\
`
`1
`
`3456789
`
`Vcc (v)
`
`Fig. 13. Measured soft error bits of 64K dynamic RAM, dependence
`of Vcc for (a) conventional
`cell, (b) Hi-C cell with n+-diffused bit
`line, and (c) Hi-C cell with polysilicon bit line.
`
`11
`Fig.
`treatment.
`this
`and after
`rate before
`error
`soft
`the
`shows
`the experimental
`results
`on the soft error
`rate between
`the boosted word line and the unboosted
`one. Fig. 11 indicates
`that
`in the
`accelerated
`measurement
`the
`error
`rate
`of
`the
`boosted word line at Vcc = 4.5 V is ten times as small as that
`of the unboosted
`one.
`
`RAM in
`the 64K dynamic
`line,
`the boosted word
`Besides
`bit
`line to
`applies
`the Hi-C cell and the polysilicon
`this paper
`reduction
`soft errors.
`In order
`to verify the soft error
`improve
`line, 64K
`the Hi-C cell and the polysilicon
`bit
`effect with
`dynamic RAM’s with three different
`kinds of memory
`cells
`were fabricated using almost
`the same process;
`the conventional
`
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`
`

`

`TANIGUCH1et al.: 64K DYNAMICRAM WITH AUTO/SELF-REFRESH
`
`497
`
`Fig. 14. Photomicrograph of 64K dynamic RAM .
`
`the Hi-C cell with diffused bit line,
`line,
`cell with diffused bit
`and the Hi-C cell with polysilicon bit line. Figs. 12 and 13 are
`the experimental
`results of the soft error
`rate as a function of
`the cycle time and P& supply voltage,
`respectively. The Hi-C
`cell with polysilicon bit line shows a lower soft error rate,
`that
`is, its error
`rate at Vcc = 4.5 V is 72 times as small as that of
`the conventional
`cell with diffused bit line.
`In addition to those approaches described above, the memory
`chip has been coated with a polyimide
`resin film to enhance
`the reliability
`to the soft error. The system test of the 64K
`dynamic RAM showed the soft error
`rates less than 1 X 10-6
`errors per device hour, which was achieved by the improve-
`ments of the circuit, process, device and coating technologies.
`Fig. 14 shows a microphotograph
`of the chip, which has a
`die size of 4.31 X 7.27 mm2. The performance
`characteristics
`of the 64K dynamic RAM are summarized in Table I.
`
`V. CONCLUSION
`
`and self-
`A single 5 V 64K dynamic RAM with automatic
`refresh functions
`on the same chip was designed and success-
`fi.dly fabricated
`using a double polysilicon
`and 3-IMn process
`technologies.
`The new Hi-C memory cell with the polysilicon bit line, the
`on-chip bias generator
`and the fully boosted circuits such as a
`word line and a cell plate have made a high speed and stable
`dynamic RAM operation with the low soft error rate,
`The 64K dynamic RAM with a die size of 31.3 mmz pro-
`vides a typical access time of 90 ns and an operating power of
`190 mW.
`The system test of the 64K dyanmic RAM showed the soft
`error
`rate less than 1 X 10-6 errors per device hour, which was
`
`TABLE I
`FEATURESOF64K DYNAMICRAM
`
`Process
`
`Technology
`
`3pm rule
`
`n-channel
`
`MOS
`
`Chip Size
`
`Cell
`
`Size
`
`Voltage
`
`Supply
`
`In / Out
`
`level
`
`7.27mm
`
`x 4,31mm
`
`200pm2
`
`5V Single
`
`TTL
`
`Access
`
`/Cycle
`
`Time
`
`90
`
`ns / 230ns
`
`Power Dissipation
`
`190m W
`
`Refresh
`
`128
`
`Cycle
`
`/2mS
`
`Soft
`
`Error
`
`Rote
`
`less
`
`than
`
`1~6/device.
`
`hour
`
`achieved by the improvements
`and coating technologies.
`of the automatic
`The excellent characteristics
`functions on the same chip were performed.
`
`of the circuit, process, device
`
`and self-refresh
`
`ACKNOWLEDGMENT
`
`The authors would like to thank S. Sato and S. Uoya for pre-
`paring samples, Dr. H. Abe, Dr. T. Kate, and Dr. H. Nakata
`for helpful discussions, and Dr. H. Oka for his encouragement.
`
`REFERENCES
`
`[1] R. H. Dennard et al., “Design of ion-implanted MOSFET’S with
`IEEE J. Solid-State Circuits,
`very small physical dimensions:’
`vol. SC-9,pp. 256-268, 1974.
`[2] B. Hoeneisen and C. A. Mead, “Fundamentrd limitation iu micro-
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 19:52:06 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1028, p. 6
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

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`vol. SC-14, pp. 268-274, Apr. 1979.
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`RAM;
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`854, Oct. 1980.
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`in ZSSCC Tech. Dig., 1981, p. 84.
`dancy technique;’
`soft errors
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`in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-
`26, pp. 2-9, Jan. 1979.
`A. F. Tasch et al., “The Hi-C RAM cell concept;
`Electron Devices, vol. ED-25, pp. 33-42, Jan. 1978.
`V. L. Rideout,
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`IEEE Trans.
`
`Japan,
`Makoto Taniguchi was born in Tokyo,
`on May 4, 1944. He received the B.S. degree
`from the Tokyo
`Institute
`of Technology,
`Tokyo, Japan, in 1968.
`From 1968 to 1976 he was engaged in the
`design of logic MOS LSI’S and MOS memories
`at Kitaitami Works, Mitsubishi Electric Cor-
`poration,
`Itami, Japan. Since 1976 he has been
`with the Mitsubishi LSI Development Labora-
`tory, Hyogo, Japan, and has been engaged in
`the design of dynamic MOS memories.
`
`Tsutomu Yoshihara received the B.S. and M.S.
`degrees in physics from Osaka University, Osaka,
`Japan,
`in 1969 and 1971, respectively.
`In 1971 he joined Mitsubishi Electric Corpora-
`tion and has been engaged in development of
`MOS
`process
`and MOS memory
`design
`technologies.
`Mr. Yoshihara is a member of the Institute of
`Electronics
`and Communication Engineers of
`Japan and the Japan Society of Applied Physics.
`
`Michihiro Yamada was born in Japan on Jan-
`uary 10, 1950. He received the B.S. degree in
`applied physics from the University of Tokyo,
`Tokyo, Japan, in 1972.
`In 1972 he joined the Central Research Lab-
`oratories, Mitsubishi
`Electric
`Corporation,
`Amagasaki, Japan.
`In 1973 he started research
`and development
`on charge-coupled
`devices
`(CCD).
`In 1976 he transferred to Mitsubishi’s
`LSI Development Laboratory,
`Itami,
`Japan,
`where he has been involved in the development
`of CCD memories. He is currently working on the development of
`MOS dynamic memories.
`
`,*. ,
`
`Yoshhni Gamou received the B.S. and M.S.
`degrees in electronics engineering from Kyoto
`University, Kyoto,
`Japan,
`in 1959 and 1960,
`respectively.
`In 1960 he joined the Central Research Lab-
`oratories, Mitsubishi
`Electric
`Corporation,
`Amagasaki, Japan, where he was engaged in the
`development
`of magnetic
`drum and striped
`memories.
`In 1966 he transferred to Mitsubishi’s
`Computer Works, where he worked on the sys-
`tem of magnetic core memories and semicon-
`In 1975 he transferred to the Kitaitami Works of
`ductor memories.
`Mitsubishi, where he developed MOS memories.
`In 1976 he joined
`Mitsubishi’s LSI Development Laboratory,
`Itami, Japan. He is presently
`Manager of the Design Development Department and has been involved
`in the development of VLSI MOS memories and logics.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 19:52:06 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1028, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`