IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 5, OCTOBER 1980
`
`865
`
`Paul K. Lane was born
`on De-
`in Olean, NY,
`cember
`8, 1951.
`He received
`the B.S. degree in
`electrical
`engineering
`from the Rochester
`Insti-
`tute of Technology,
`Rochester,
`NY,
`in 1974.
`He
`has
`been with
`the
`IBM Corporation,
`Burlington,
`VT,
`since 1974
`as a Design Engi-
`neer
`in
`both
`current
`and
`advanced
`bipolar
`technologies.
`He has participated
`in the design
`of severaf memory
`and memory
`supports
`chips.
`
`Burlington,
`of
`IGFET,
`
`Since joining
`in 1970.
`VT,
`bipolar,
`and magnetic
`bubble
`
`IBM he has worked
`device design.
`
`in the areas
`
`the B .S. degree in
`received
`J. Houghton
`Russetl
`from the University
`of
`engineering
`electrical
`VT,
`in 1968.
`Burlington,
`Vermont,
`Essex
`He has been with the IBM Corporation,
`Junction,
`since 1968, His circuit
`design respon-
`sibilities
`have included
`both
`bipolar
`and FET
`memory
`and
`special
`application
`bipolar
`sup-
`ports.
`
`Ted A. Selfrktge was born on July 9, 1937. He
`received
`his education
`from The Pennsylvmia
`State University,
`University
`Park, PA.
`VT, since
`He has worked
`at
`IBM, Burlington,
`January
`1966
`as a Draftsman
`and Designer,
`participating
`since
`1971
`in bipolar
`IC layout
`and design.
`
`256K RAM Fabricated with
`A Fault-Tolerant
`Molybdenurn-Polysilicor~
`Technology
`
`IEDA,
`NOBUAKI
`TAKASHI WATANABE,
`TSUNEO MANO, KEN TAKEYA,
`KAZUHIDE
`KIUCHI, EISUKE ARAI, TADAMASA
`OGAWA, AND KAZUO HIRATA
`
`siiicon (Mo-
`paper describes a 256K molybdenum-poly
`Abstracf–This
`cdl. Circuit
`POIY) gate dynamic MOS RAM using a singte transistor
`technologies,
`including a capacitive-coupled
`sense-refresh amptifier and
`a redundant
`circuitry,
`enable the achievement of h@r performance in
`combination wi~ MO-POIYtectrnolosy. Electron-hem dfiect writing
`and dry etching technologies are futty utitiied to make 1 pm accurate
`patterns. The 256K word x 1 bit device is fabricated on a 5.83 mm X
`5.90 mm chip.
`CeU size is 8.05 pm x 8.60 Wm. The additional
`4K
`spare cells and the associated circuits,
`in which newly developed elec-
`trically
`programmable
`elements are used, occupy less than 10 percent
`of
`the whole chip area. The measured access time is 160 ns under
`VDD = 5 V condition.
`
`I.
`
`INTRODUCTION
`
`D YNAMIC MOS random access memories (RAM’s) using a
`
`cell have many advantages such
`single transistor memory
`as high density,
`low power, and low cost.
`In 1977, a proto-
`
`Manuscript
`The authors
`oratory,
`Nippon
`Japan.
`
`revised May 15, 1980.
`11, 1980;
`received March
`Electrical
`Communication
`are with
`the Musashmo
`Telegraph
`and Telephone
`Public Corporation,
`
`Lab-
`Tokyo,
`
`process was re-
`type 64K MOE RAM using a 2 pm fabrication
`ported
`[1].
`Commercial 64K RAM’s will be available in the
`future, MOS RAM bit capacity has increased at a great
`near
`rate. However,
`in order
`to obtain an MOS RAM larger than a
`64K RAM, several problems should be solved. The first prob-
`lem is the lack of
`fine patterning
`technology.
`Although
`1-
`1.5 ~m patterning technology
`is necessary, present photolithog-
`raphy cannot
`realize such a fine pattern precisely. The second
`problem is the high sheet-resistivity
`of polysilicon
`and the n+
`diffused layer.
`In the case of 64K RAM’s, since speed perfor-
`mance degradation is not so clear, both structures of polysili-
`con word-line
`and metal word-line
`are permitted
`[1] - [4].
`However,
`in the case of 256K RAM’s, polysilicon word-line
`cannot be aldopted because of
`large signal propagation
`clelay.
`When the word-line uses metal as an interconnection,
`the bit-
`line is usually made of an n+ diffused layer. Since a diffused
`layer has large sheet-resistance and capacitance,
`this structure
`The last problem is low yield.
`If
`degrades speed performance.
`the same technology
`is used, 256K RAM yield becomes far
`lower
`than 164K RAM yield.
`For
`instance, a 64K yield of 20
`
`0018 -9200/80/1000-0865
`
`$00.75 01980
`
`IEEE
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 1
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`
`

`

`866
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 5, OCTOBER 1980
`
`Fault-
`to a 256K yield of 0.16 percent.
`is equivalent
`percent
`The
`technology may push up the yield drastically.
`tolerant
`in
`RAM’s with
`fault-tolerant
`function
`have been reported
`some papers [5]
`,
`[6]
`. A programmable
`element, which has
`low programming
`voltage and enough current
`to be controlled
`by MOS transistors, has never been obtained.
`Therefore,
`large
`area and/or many controlling
`signals for
`fault-tolerant
`circuitry
`were needed.
`This paper describes a 256K MOS RAM, which has several
`new ideas to solve the above-mentioned
`problems.
`In Section
`II, a highly sensitive and high speed sense-refresh amplifier
`is
`proposed.
`Section III describes the concept of
`fault-tolerant
`technology
`adopted in the 256K RAM. A new programmable
`element
`is discussed in the same section. Section IV describes
`the 256K RAM block diagram and concrete circuits containing a
`sense-refresh amplifier, a spare decoder, and multiplexer.
`Sec-
`tion V describes the 1 pm fabrication
`process using molybde-
`num-polysilicon
`(Mo-poly)
`technology
`and the MOS transistor
`characteristics.
`Section VI shows the experimental
`results.
`
`II. SENSE-REFRESH AMPLIFIER
`
`a single transistor memory cell,
`In a dynamic RAM utilizing
`the signal size is small and an amplifier which includes a flip-
`flop is generally used. The functions
`required in the amplifier
`are sensing and refreshing.
`In other words,
`the ability
`to de-
`tect a small signal and to get high refresh voltage is necessary.
`Furthermore,
`it
`is desirable to achieve a low power and high
`speed amplifier.
`Regarding the power dissipation
`point, no
`amplifier
`operating in partially
`static mode is suitable for LSI
`memories.
`Therefore,
`discussion about a sense-refresh ampli-
`fier should be restricted to the fully dynamic
`circuit.
`The fo-
`cus of attention
`is upon three other points, namely, sensitivity,
`refresh voltage, and speed performance.
`So far,
`two types of
`dynamic amplifiers
`have already been reported. One type of
`amplifier
`has been designed to be highly sensitive. For exam-
`ple,
`it can detect a signal of 30 mV [7]
`. However,
`the opera-
`tion is rather slow since many clocks are used.
`In the amplifier
`of
`the other
`type,
`the capacitor coupling technique has been
`introduced
`to obtain sufficient
`refresh voltage [8]
`. Although
`its sense-refresh
`operation
`can be completed with only one
`clock,
`the sensitivityy is somewhat worse,
`In order
`to correct
`these defects and to combine merits of both, a new sense-
`refresh amplifier
`is proposed, which
`employs
`the improved
`capacitive-coupled
`circuit.
`of a proposed capacitive-coupled
`The fundamental
`circuit
`amplifier
`and its waveforms are shown in Fig. 1(a) and (b), re-
`spectively.
`In addition
`to a flip-flop,
`a pair of coupling ca-
`pacitors
`and switching
`transistors
`are used in the amplifier.
`Nodes N and N’ are connected to the first driving clock @D1
`through the capacitors. These nodes and bit-lines are connected
`through switching transistors Q and Q’. When the signal from
`a memory
`cell appears as the potential difference between two
`bit-lines,
`the amplifier
`is driven by three clocks. Clock @Dl is
`used for both detection and refreshing the cell. @D2is the ac-
`celerating clock and @Bis the refresh control clock.
`sensing and
`The operating time includes two main periods:
`refreshing.
`In the sensing period,
`the first clock @D~ turns on
`transistor QI, which
`discharges common
`source node Nc.
`
`fLJi7
`
`(a)
`
`@B-----’(
`
`SENSE i
`
`&
`
`RI-(I‘;;’I
`
`Fig. 1. Sense-refresh
`
`amplitler.
`
`circuit.
`
`(b) Operating
`
`&J)
`(a) Fundamental
`waveforms.
`
`transistors begin to detect and am-
`the cross-coupled
`Then,
`the bit-line signal. After
`this amplification
`progresses to
`plify
`a certain degree, accelerating transistor Q2 is activated by the
`second clock @Dz. The common source is further discharged
`by Q2, and sensing operation is completed rapidly.
`In general,
`a small conductance of Ql
`is necessary for high sensitivity, and
`the conductance of Qz should be large to accomplish high speed
`sensing. Since these requirements affect each other,
`it
`is neces-
`sary to optimize
`the design. Using simulation, QI
`conduc-
`tance is chosen as one-twentieth
`of the Qz conductance.
`Thus,
`the amplifier
`can detect a signal of *5O mV within
`a 35 ns
`sensing period.
`As soon as the sensing operation is completed,
`circuits such as multiplexer
`can start
`to read the bit-line infor-
`mation without
`refreshing.
`This situation
`assures that short
`access time is easily achieved. However, at the end of
`the sens-
`ing period,
`the potential
`of
`the bit-line, which has received a
`high level signal
`from a selected memory
`cell,
`is not sufficient
`for
`refreshing as shown in Fig.
`l(b).
`In order
`to raise the bit-
`line potential,
`control
`clock OR is applied to switching transis-
`tors Q and Q’. Each bit-line is connected with node N or N’,
`which is previously
`raised up through the capacitor by clock
`@Dl. The high refresh voltage, which depends on the ratio of
`coupling
`capacitance
`to bit-line
`capacitance,
`is obtained dy-
`namically. Moreover, switching transistors controlled by clock
`@B work to prevent an increase in effective bit-line capacitance
`during the sensing period.
`This technique eliminates the de-
`merit of degrading sensitivity by adding additional
`capacitance
`directly
`to the bit-lines.
`the sensing operation is completed
`In the proposed amplifier,
`optimized
`design, both high sen-
`with two clocks.
`Utilizing
`sitivityy and high speed performance
`can be accomplished.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 2
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`
`

`

`MANO et al.: FAULT-TOLERANT
`
`256K RAM
`
`861
`
`COLUMNDECODER
`,-—.
`
`,
`
`‘4
`
`SPARECELL
`Fig. 2. Substitution
`method.
`
`Mo
`
`CVDSi09
`
`Al
`
`(a)
`
`~_.._._J
`
`0)
`
`Fig. 3. Programmable
`
`element
`
`structure.
`
`(a) Layout.
`
`(b) Cross section.
`
`by another clock is in-
`controlled
`circuit
`A capacitive-coupled
`to improve refresh voltage.
`This amplifier
`troduced
`in order
`makes it easy to develop a high performance LSI memory.
`
`111. FAULT -TOLERANT
`
`TECHNOLOGY
`
`improves
`technology
`fault-tolerant
`that
`It has been known
`Recently,
`it was reported
`that multiple
`LSI
`fabrication
`yield.
`word/bit
`line redundancy
`technology
`may
`improve
`LSI RAM
`yield
`drastically
`[9]
`. A schematic
`diagram of a RAM with
`multiple
`word/bit
`line redundancy
`and the substitution
`method
`are shown
`in Fig. 2.
`It contains
`16 fundamental
`cells and 9
`spare cells.
`DXO-DX3
`and DYO-DY3
`are fundamental
`row
`SDX and SDY are spare
`and column
`decoders,
`respectively.
`row and column decoders. The spare cell can be used as a sub-
`stitute
`for
`the defective memory
`cell by programming
`to use
`SDX in place of DX1, or SDY in place of DY2. Programmable
`elements are utilized
`to register an arbitrary
`address in the
`The element
`is desired to have an irreversible
`spare decoder.
`transition
`characteristic
`and to be programmed by using inter-
`nal address signals.
`two 64K RAM’s with multiple word/bit
`In the 1979 ISSCC,
`line redundancy were reported
`[5]
`, [6]. However,
`they had
`to use a laser beam or external address signals for lack of pro-
`grammable
`elements having a low programming
`voltage and
`current.
`Fault-tolerant
`technology using a laser beam required
`both extra hardware and software to program the defective ad-
`dress. The other
`technology
`required many extra pads and a
`large interconnection
`area on the chip to provide a defective
`address to the spare decoder.
`The present
`fault-tolerant
`
`has no such problem,
`
`technology
`
`Fig. 4.
`
`I-V chamcteristics of programmable element. A: before tmmsi-
`tion. B: after transition.
`
`technol-
`
`line redundancy
`although it adopts multiple word/bit
`ogy.
`It employs the following
`three features.
`is carried out
`cell
`1) Substitution
`for
`the defective memory
`electrically
`during the wafer probing period and the repaired
`device is regarcled as a perfect one.
`is adopted, which has low
`2) A new programmable
`element
`and an irreversible
`transi-
`programming
`voltage and current
`tion characteristic.
`Since its programming
`is easily controlled
`by MOS transistors,
`internal address signals can be applied to
`register the defective address.
`cell address is
`3) Since registration
`of
`the defective memory
`accomplished by output
`signals from internal address buffers,
`the number of extra pads necessary for
`registration
`becomes
`very small.
`element and its charac-
`In this sect.icm, a new programmable
`teristics
`are described.
`The layout and cross section of
`the
`new programmable
`element are shown in Fig. 3(a) and (b), re-
`spectively.
`The programmable
`element
`is composed of
`two
`polysilicon
`p-n. diodes and has a lateral n-p-n structure, which
`is constructed
`in the narrow part at the center of
`the top view.
`The narrow part width is 1 ~m. This programmable
`element
`has a low prc)gramming voltage and a current of 11 V and
`7 mA,
`respectively.
`The element has similar programming
`characteristics
`to the previously reported one. which has a ver-
`tical
`type resllstor composed of undoped polysilicon
`[10]
`. The
`lateral n-p-n programmable
`element has two merits.
`One is
`simple structure so that
`introduction
`of the element
`to the LSI
`is easy without
`a major
`fabrication
`process change. The other
`is high resistance before programming,
`owing to the reverse.
`biased p-n junction
`in one side.
`Its initial
`resistance is larger
`than 109 C?. When the voltage and current over the critical
`value are applied to the element,
`its resistance goes down to
`less than 3 X 103 fl. Since the transition is caused by destroy-
`ing the p-n junction,
`it
`is irreversible.
`A permanent and very
`stable registration
`of defective memory
`cell address can be
`accomplishecl.
`the programmable
`of
`Fig. 4 shows two I-V characteristics
`A and B appear before and after
`transition,
`respec-
`element.
`tively.
`They indicate that
`the transition
`occurs at 11 V. The
`programming characteristics are shown in Fig. 5. The resistance
`of
`the programming
`element becomes lower
`in accordance
`with the number of 10 MSwidth programming pulses.
`It
`is suf-
`ficient
`to apply a few pulses for
`the stable registration.
`Since
`the element can be programmed
`during such a short period,
`the time to register
`the defective memory cell address is negli-
`gibly short.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 3
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`IPR2020-01008
`
`

`

`868
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 5, OCTOBER 1980
`
`1~(*N*TIAL“&”~>,@fl)
`
`15K
`
`\k.-
`
`PULSEWIDTH=10jJs
`
`z
`g 10K
`8za
`$
`GUE
`
`5K
`
`()~
`02468
`PROGRAMMINGPULSE NUMBER
`Fig. 5. Programming
`characteristics
`of programmable
`element.
`
`L. —._.
`
`_._.
`
`_.
`
`Fig. 7. 256K RAM circuitry.
`
`Aiy
`
`~
`
`A8y ~
`
`.-
`
`Qi
`Fj
`yf
`
`. .
`
`.-
`
`.-
`
`TO
`MULTIFLEXER
`
`FLG
`
`~ A: Vm/OPEN
`
`b B: Vpp/ VSS
`
`DATA-OUT
`
`‘dDOUT
`BUFFER3$~
`
`48X
`
`m
`
`Fig. 8. Spare column
`
`decoder
`
`circuit.
`
`In order to obtain a high re-
`to detect.
`sense-refresh amplifier
`fresh voltage, coupling capacitance used in the amplifier
`is one-
`third of bit-line capacitance.
`there are
`has 516 sense circuits,
`Since the
`128K block
`133128
`(258 X 516)
`cells in each block.
`Among
`them,
`131072
`(256 X 512) cells in the 512 sense circuits are under
`fundamental
`usage. The remaining 1024 (512 X 2) cells in the
`fundamental
`sense circuits and the 1032 (258 X 4) cells in the
`four other
`sense circuits are under
`redundant
`usage. These
`cells, namely spare cells, are connected with four pairs of bit-
`lines or two word-lines
`in the 128K block, They are shown as
`the dotted area in Fig. 6. When failure bits are found, spare
`cells are substituted
`for defective cells. This substitution
`can
`be achieved during wafer probing by activating a spare decoder,
`in which
`electrically
`programmable
`polysilicon
`elements are
`utilized.
`The general substitution method and the program-
`mable element characteristics
`have already been described in
`Section III. Fig. 8 shows the spare column decoder using these
`elements, which are all connected with terminal B. Under pro-
`15 V pulses are applied to B, Transistor
`gramming conditions,
`Qj
`is also turned on, using selection terminal A.
`The signal
`from the internal address buffer controls the switching transis-
`tor.
`For example,
`in order t o cause the transition
`of program-
`mable element Pi,
`transistor Qj
`is turned on by signal Aty.
`After programming
`is completed,
`terminal A does not need to
`and terminal B is connected with ground pin
`be connected
`V~~.
`Therefore,
`any additional
`package pin is not
`required.
`Row decoder substitution
`is accomplished in the same manner.
`In each 128K block,
`there is one dummy sense circuit, which
`has the same components as the other sense circuit.
`It is placed
`on the opposite side from the row decoder
`in order
`to opti-
`mize the timing of reading clock OR. Since clocks which drive
`all amplifiers are supplied from the row decoder side, the ampli-
`fier in the dummy sense circuit completes its operation slightly
`later
`than the other amplifiers.
`As soon as the operation
`of
`
`Row
`AODRESS
`BLFFERS
`
`~2TK— FL07K—––––––––
`I
`I
`
`–––––_––
`
`.-
`
`m
`
`MULTIPLEXER
`
`(1)
`
`,..
`
`E&[
`
`: T
`
`G
`;
`.:. :1
`
`MEMORY
`ARRAY
`~
`:::.:
`( 128 x 512 )
`,.,.
`+
`~ + :.,
`,,,,,,
`. ...,
`,
`-m ~ . . ...SpA.RE’.TCELL5:::( 1028 ):.:
`w
`D~MY
`CELLS
`~ 1$
`; g
`I
`516 SENSE AMPLIFIERS
`g E
`~ a;
`$ g
`DUMMY CELLS
`.3 ‘0 :: ~pA~~.“:cELLs:,.,(1~29 )j,’ :;:: g g
`,,:.’
`...’...-
`:J :
`E
`MFMORY
`,-.”.,
`ARRAY
`2
`(128 X 512 )
`;:;;
`MULTIPLEXER (II)
`COLUMN DECODER
`
`SPARE
`. ,.
`mw
`1:’:’+n
`DECO+IER
`
`J-
`~1
`
`I
`
`CONTROL
`CIF?JIITR
`?
`I
`SPARE
`CDLUMN I
`OECODER L-
`K“”””il::w=,,
`&uu,
`~
`‘
`
`-
`
`“’”
`
`CONTROL
`CLOCKS
`
`——
`RASCAS k
`
`1-------1I
`
`BUFFERS I
`7-
`‘–’
`E’
`~~k
`d
`I 128K BLOCK
`L—__— ————–——————_——_. ________J
`
`Fig. 6. 256K RAM block
`
`diagram.
`
`circuitry
`Fault-tolerant
`cussed in Section IV.
`
`applied to the 256K RAM is dis-
`
`IV. 256K RAM DESIGN
`
`the designed 256K RAM is shown in Fig.
`A block diagram of
`It
`includes a pair of 128K blocks.
`In addition to the funda-
`6.
`mental memory
`cells,
`the RAM has 4K spare cells. They are
`utilized to obtain redundancy
`in case defects are found in the
`fundamental
`part.
`An improved
`capacitive-coupled
`sense-
`refresh amplifier,
`a dummy
`sense circuit, and a double array
`multiplexer
`are also introduced
`[8].
`The adopted
`organi-
`zation is 256K word X 1 bit.
`The typical
`power supply is
`VDD = 5 V. Refresh requires 256 cycles. All
`inputs and the
`output
`are TTL compatible.
`Fig. 7 shows the circuitry
`for this
`device.
`sense-
`consists of one capacitive-coupled
`The sense circuit
`refresh amplifier,
`two dummy
`cells, and 258 memory cells. A
`pair of bit-lines
`in the sense circuit are placed symmetrically
`on both sides of
`the amplifier.
`That
`is, an array of516
`sense-
`refresh amplifiers are located between memory arrays, as shown
`in Fig. 6. Since each bit-line, which passes across the word-
`lines,
`is composed of
`interconnection metal, effective capaci-
`tance of
`this bit-line becomes smaller than that of
`the diffused
`layer bit-line.
`The ratio of storage capacitance C~ to bit-line
`capacitance CB is more than ~. The signal size is +100 mv,
`under
`the worst conditions.
`This is a sufficient
`value for
`the
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 4
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`IPR2020-01008
`
`

`

`MANO et al.: FAULT-TOLERANT
`
`256K RAM
`
`869
`
`clock OR is generated,
`is completed,
`sense circuit
`the dummy
`and the output buffer.
`Thus, cor-
`which activates multiplexer
`rect read operations are enstired in a wide range of conditions.
`In the double arrays of multiplexer,
`the divided bus-line con-
`figuration
`is used. As shown in Fig. 7, there are three kinds of
`bus-lines used for
`reading. To reduce effective capacitance of
`bus-ii,
`it
`is divided into four parts. The potential of each part
`changes rapidly, according to the information
`on the selected
`bit-line.
`Circuits connected to bus-Bi discharge bus-C, and ac-
`tivate the output
`buffer.
`In writing,
`complementary
`signals
`are transferred
`from the input buffer
`to a couple of selected
`bit-lines through multiplexer.
`
`V. 1 Mm FABRICATION
`MOLYBDENUM-POLYSILICON
`
`PROCESS USING
`TECHNOLOGY
`
`the fol-
`
`MOS RAM,
`and high-density
`a high-speed
`To realize
`lowing
`fabrication
`processes must be developed.
`1) fine pattern
`lithographic
`technology;
`2) etching
`technology,
`which
`realizes
`replication;
`for high speed operation.
`gate technology
`self-align
`3) metal
`electron-beam
`direct writing,
`ln the 256K RAM fabrication,
`dry
`etching,
`and molybdenum-polysilicon
`technologies
`have
`been developed
`[1 1].
`cells in less than a 35 mm2 chip,
`To make 256K bit memory
`fine
`pattern
`formation
`technology
`of
`1 ~
`level
`is neces-
`
`high accurate
`
`pattern
`
`has
`
`process, electron-
`256K RAM fabrication
`In the present
`sary.
`steps. A variable
`is used for
`lithographic
`beam direct writing
`shaped beam exposure system is used in order
`to shorten writ-
`ing time.
`It has a dynamic range of 12.5- 1.0 ~m square beam
`with a 0.1 ~m step. The 256K RAM chip is obtained by stitch-
`ing a 3 X 3 array of 2 mm X 2 mm subfields with alignment
`accuracy of *0.2 #m in all
`lithographic
`steps. Both negative
`and positive
`resists are used, considering
`each writing
`level.
`The negative.
`resist
`is chloromethylated
`polystyrene
`(CMS),
`and the positive resist
`is poly [ 1,1 -dimethyl
`tetrafluoroplopyl
`methacrylate]
`(FPM)
`[10]
`, [11].
`process,
`For dry etching technology
`in the 1 ~m fabrication
`highly accurate pattern replication
`feasibility
`and high etching
`selectivity are required. The etching mask in each etching step
`a high re~istivitv
`to drv etch.hw. An-
`is FPM or CMS which
`isotropic
`etching using the parallel plate electrode system is
`suitable to satisfy the above requirements.
`By optimizing
`the
`etching condition,
`such as reactive gas species, gas flow rate,
`and RF power density, undercutting
`is less than 0.05 pm, and
`sufficient
`etching selectivity
`for underlying
`layers and the re-
`sists is realized.
`technol-
`delay, Mo-poly
`In order
`to reduce the propagation
`ogy has been developed [11 ],
`[14], A molybdenum film as a
`gate electrode has no passivation effect
`in itself.
`Therefore, a
`two step annealing method is developed to decrease sodium
`ions in gate oxide.
`In the 256K RAM fabrication, Mo-poly tech-
`nology allied with an aluminum metallization
`technique is in-
`troduced.
`Fig. 9 shows the memory cell
`layout and the cross-
`sectional view, where the cell size is 8.05 pm X 8.60 #m. Poly-
`silicon is used for plate electrodes and molybdenum is used for
`word-lines.
`Bit-lines consist of an aluminum fdm. Using the
`two level metallization
`system of molybdenum and aluminum,
`
`WORDLINE
`(Me)
`
`COLUMN
`SELECT
`
`‘9
`
`I
`
`(Al)
`
`(a)
`
`~‘ N+
`, P SUBSTRATE
`
`Mo
`
`, T
`
`(b)
`
`Fig. 9. Storage cell structure.
`
`arsenic iort-
`
`the 256K RAM
`
`The
`cell array is obtained.
`a short delay time in the memory
`time constants of word-lines
`and bit-lines
`in the 256K RAM
`are 1 and O.CI1 ns, respectively.
`The other
`fabrication
`technologies used for
`include the foilowing:
`process is used for isolation, where
`1) the selective oxidation
`boron ion-implantation
`is made;
`2) thin gate oxides are made by dry oxidation;
`3) diffused
`layer
`is fabricated
`by high-dose
`implantation;
`glass with high phosphorus penta-oxide
`4) phosphosilicate
`concent
`is used for an intermediate layer.
`Polysilicon
`gate (Si-gate)
`transistors are used in peripheral
`circuits, while molybdenum gate (Me-gate)
`transistors are used
`in memory cells. Although the performance of these transistors
`improves with decreasing dimensions,
`the short channel effect
`becomes more severe.
`the Si-gate transis-
`effect of
`To minimize
`the short-channel
`tors, device parameters, such as gate oxide thickness,
`junction
`depth, and channel-dope
`condition,
`are optimized.
`In the
`256K RAM clesigned, the supply voltage is 5 V, and a threshold
`voltage
`of
`().5 V and threshold
`voltage deviation
`of O.1 V
`are required,,
`The optimized
`device parameters are 1.’2 ~m
`effective chmmel
`length, channel dose of 5 X 1011 cm-2, sub-
`strate doping concentration
`of 3 X 1015 cm-3, 0.25 pm junc-
`tion depth, and 30 nm gate oxide thickness.
`Since the use of
`the electron-beam direct writing and the dry etching technology
`is sufficient
`10 obtain the pattern width accuracy of fO.1 ~m,
`the threshold
`voltage deviation
`of
`the Si-gate transistors
`is
`within *0.05 V.
`cells must be made on
`Me-gate transistors used in memory
`Since Me-gate has a
`the same substrate as Si-gate transistors.
`0.7 V higher work function
`than Si-gate, the threshold voltage
`of
`the Me-gate transistor
`is higher than that of the Si-gate tran-
`.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`870
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 5, OCTOBER 1980
`
`TABLE
`DEVICE PARAMETERS AND
`
`I
`CHARACTERISTICS
`
`Substrate
`
`concentration
`
`Boron
`
`dose
`
`Gate
`
`oxide
`
`thickness
`
`~+
`
`]unction
`
`depth
`
`Effective
`
`channel
`
`length
`
`Threshold
`
`voltage
`
`Si–gate
`
`Me-gate
`
`~ ~ ~015cm-3
`
`3 x ,0’’cm-’
`
`~ ~
`
`~ollcm-z
`
`30
`
`nm
`
`40
`
`run
`
`0.25
`
`pm
`
`0.25
`
`pm
`
`1.2
`
`pm
`
`0.5
`
`v
`
`1.5
`
`1.2
`
`p
`
`v
`
`Subthreshold
`
`leakage
`
`70 mV/dec.
`
`80 mV/dec.
`
`Back-gate
`
`coefficient
`
`0.082
`
`mobility
`
`550
`
`cm2/Vsec
`
`—
`
`Ris
`Pv’E
`
`DIN
`
`‘OUT
`
`Fig. 11. Write/read
`
`operating waveforms
`
`at VDD = 5 V and T= 25°C.
`
`Field
`
`effect
`
`II
`TABLE
`TYPICAL 256K RAM CHARACTERISTICS
`
`Organization
`
`Cell
`
`size
`
`Chip
`
`size
`
`Access
`
`time
`
`cycle
`
`time
`
`256K
`
`word
`
`x
`
`1 bit
`
`8.05
`
`pm x
`
`8.60
`
`pm
`
`5.83
`
`mmx
`
`5.90
`
`mm
`
`100
`
`ns
`
`200
`
`IIS
`
`supply
`
`voltage
`
`+5V
`
`single
`
`operating
`
`power
`
`230 mw at
`
`200
`
`ns
`
`cycle
`
`time
`
`Standby
`
`power
`
`15 mw
`
`Refresh
`
`256
`
`cycles
`
`1/0
`
`interface
`
`TTL
`
`compatible
`
`Fig. 10. 256K RAM microphotograph.,
`
`. To obtain the maximum storage charge in mem-
`[14]
`sister
`ory cells, a gate voltage of 7 V is applied to the Me-gate tran-
`sistors.
`In order not
`to increase the defect density of
`the gate
`oxide at
`the 7 V gate voltage operation,
`an oxide thickness of
`40 nm is adopted for the Me-gate, as described above. Consid-
`ering short-channel
`effects,
`the effective channel
`length of the
`Mo-gate is designed 1.5 pm.
`the transistors used
`of
`Device parameters and characteristics
`in the 256K RAM are summarized in Table 1.
`
`VI. RESULTS
`
`on a 5.83 mm X 5.90 mm
`The 256K RAM was fabricated
`chip using n-channel Mo-poly technology, which was mentioned
`in the previous section. A microphotograph
`of
`this device is
`shown in Fig. 10. The circuit
`locations
`correspond with the
`block diagram in Fig. 6 for
`the most part. The redundant cir-
`cuitry, which includes spare decoders,
`is placed on the left side
`and occupies approximately
`8 percent of
`the whole chip area.
`The area of the 4K bit spare cells is less than 1 percent and can
`be regarded as negligible.
`Write-read
`operating waveforms are shown in Fig. 11. Mea-
`surements were carried
`out under
`a typical
`condition
`of
`V~~ = 5 V. The measured bit has a sequence of write “one,”
`read “one, ” write “zero, ” and read “zero. ”
`The waveforms,
`which appear in the photo,
`correspond to TTL inputs and the
`data output
`signal. Since internal
`clock circuits are designed
`
`read access time is
`to have an excessively wide timing margin,
`160 ns at
`room temperature.
`The sample dissipates less than
`150 mW power
`consumption
`at
`the 400 ns operating cycle.
`Moreover,
`it has been confirmed by simulation that cycle time
`and access time can be reduced to 200 and 100 ns, respectively.
`Under
`this
`condition,
`power dissipation
`becomes 230 mW.
`Typical characteristics are summarized in Table II.
`
`VII. SUMMARY
`
`A high performance 256K RAM was developed using molyb-
`denum polysilicon
`(Mo-poly)
`technology.
`In order
`to obtain
`both high packing density and high speed performance,
`an im-
`proved capacitive-coupled
`sense-refresh amplifier
`is proposed.
`It can detect a signal off 50 mV within a 35 ns sensing period.
`Its high sensitivity
`in combination with
`1 Urn Mo-poly
`tech-
`nology makes it possible to utilize a small memory cell, which
`occupies less than 70 Vm2. Making use of
`the capacitor
`cou-
`pling technique,
`sufficient
`refresh voltage can be obtained. A
`dummy
`sense circuit
`and a divided
`configuration
`of multi-
`plexer
`are also introduced.
`Furthermore,
`fault-tolerant
`tech-
`nology,
`in which the substitution method is used, has been de-
`veloped to improve LSI yield.
`In addition to the fundamental
`256K memory
`cells, 4K spare cells are prepared on the chip.
`Using a new programmable
`element composed of polysilicon,
`spare cells can be substituted for defective cells. The substitu-
`tion is accomplished electrically
`during wafer probing.
`An LSI
`fabrication
`process, employing Mo-poly
`technology,
`has been developed. Electron-beam direct writing technology
`and dry etching technology are fully utilized to make 1 pm ac-
`curate patterns.
`To minimize short channel effects, device pa-
`rameters are optimized for polysilicon-gate
`(Si-gate) transist ors.
`
`Authorized licensed use limited to: Nicole Hughes. Downloaded on May 18,2020 at 20:00:53 UTC from IEEE Xplore. Restrictions apply.
`
`Micron Ex. 1026, p. 6
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`MANO et al.: FAULT-TOLERANT
`
`256K RAM
`
`871
`
`circuits, Si-gate transistors with 1.2pm effective
`In peripheral
`channel
`length are used. On the other hand, molybdenum-gate
`transistors with
`1.5 #m effective
`channel
`length are used in
`memory cells.
`A 256K word X 1 bit RAM was designed with the above-
`mentioned
`circuit
`technologies.
`The RAM was fabricated us-
`ing the developed 1 Mm fabrication
`process. A single transistor
`cell occupies 8.05 Urn X 8.60 Mm. Chip size is 5.83 mm X
`5.90 mm.
`The area of
`the redundant
`circuits is less than 10
`percent of
`the whole chip. Measurements were carried out
`of VDD = 5 V. At
`room tempera-
`under a typical
`condition
`ture, access time is 160 ns.
`
`in
`
`Tsuneo Mano was born in Nagrmo, Japan, on
`April 26, 1947. He received the B. S. and M. S.
`derqees from the Tokyo
`Institute
`of Tech-
`nology,
`Tokyo,
`Japan,
`1970 and :1972,
`respectively.
`He joined the Musashino Electrical Commu-
`nication
`Laboratory,
`Nippon
`Telegraph
`and
`Telephone Public Corporation, Musashinoshi,
`Tokyo,
`Japan,
`in 1972, and worked on the de-
`sign of charg~transfer
`devices. He is presently
`a Staff Engineer
`in the Semiconductor Memory
`Design Section, LSI Memory Development Division, and has been en-
`gaged in reseawh. on the circuit design of MO$ memory.
`Mr. Mano is a member of
`the Institute
`of Electronics and Communi-
`cation Engineers of Japan, and received the Young Engineer Award in
`1978.
`
`ACKNOWLEDGMENT
`
`The authors wish to thank S. ~hara, H. Yoshimura, T. Asa-
`oka, M. Kondo, H. Katsuraki, K. Daido, J, Kate, and K. Matsu-
`yama for their advice and encouragement.
`They are also grate-
`ful
`to the staff of
`the Large Scale Integrated Circuit Memory
`Development Division, Musashino Electrical Communication
`Laboratory,
`for device structure design, circuit design, fabrica-
`tion, and measurement.
`
`REFERENCES
`
`[1]
`
`[2]
`
`[3]
`
`[4]
`
`[5]
`
`[6]
`
`[7]
`
`[8]
`
`[9]
`
`[10]
`
`[11]
`
`[12]
`
`[13]
`
`[14]
`
`in
`
`“A 64K bit dynamic MOS RAM,”
`Ieda,
`E. Arai and N.
`ESSCIRC Dig. Tech. Papers, 1977, pp. 74-75.
`K. Hoffman and R. Losehand,
`“VMOS technology applied to dy-
`namic RAMs?
`IEEE J. Solid-State Circuits, vol. SC-13, pp. 617-
`622, Oct. 1978.
`“A single 5V 64K
`K.
`Itoh, R. Hori, H. Masuda, and Y. Kamigaki,
`dynamic RAM:’
`in ISSCCDig. Tech. Papers, Feb. 1980, pp. 228-
`229.
`L. S. White, N. Hong, D. J. Redwine, and G. R. Mohan Rae, “A
`5V-only 64K dynamic RAM,”
`in ISSCC Dig. Tech. Papers, Feb.
`1980, pp. 230-231.
`R. P. Cenker, D. G. Clemens, W. R. Huber, J. B. Petrizzi, F. J.
`Procyk, and G. M. Trout,
`“A fault-tolerant
`64K dynamic RAM:
`in ZSSCCDig. Tech. Papers, 1979, pp. 150-151.
`R. P. DeSirnone, N. M. Donofrio, B. L. Flur, R. H. Kruggel, and
`H. H. Leung,
`“FET RAMs,”
`in ISSCC Dig. Tech. Papers, 1979,
`pp. 154-155.
`“Single transistor
`N.
`Ieda, Y. Ohmori, K. Takeya, and T. Yano,
`MOS RAM using a short-channel MOS transistor,”
`IEEE J. Solid-
`State Circuits, vol. SC-13, pp. 218-224, Apr. 1978.
`M. Kondo, T. Mano, F. Yanagawa, H. Kikuchi, T. Amazawa, K.
`Kuichi, N.
`Ieda, and H. Yoshimura,
`“A high speed molybdenum
`gate MOS RAM,”
`IEEE J. Solid-State Circuits,
`vol. SC-13, pp.
`611-616, Oct. 1978.
`line redundancy for semicon-
`S. E. Schuster,
`“Multiple word/bit
`ductor memories,”
`IEEE J. Solid-State Circuits, vol. SC-13, pp.
`698-703, Oct. 1978.
`M. Tanimoto,
`J. Murota, Y. Ohmori, and N. Ieda, “A novel MOS
`PROM using a highly resistive poly-Si
`resistor,”
`IEEE Trans. Elec-
`tron Devices,
`to be published.
`F. Yanagawa, K. Kuichi, T. Hosoya, T. Tsuchiya, T. Amazawa,
`and T. Mano,
`“A 1 ~m Mo-poly 64K bit MOS RAM,”
`IEEE J.
`Solid-State Circuits,
`vol. SC-15, pp. 6