United States Patent [19]
`Fujishima
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,586,171
`Apr. 29, 1986
`
`[54] SEMICONDUCTOR MEMORY
`Kazuyasu Fujishima, Itami, Japan
`Inventor:
`[75]
`Mitsubishi Denki Kabushiki Kaisha,
`[73] Assignee:
`Tokyo, Japan
`[21] Appl. No.: 381,584
`May 24, 1982
`[22] Filed:
`Foreign Application Priority Data
`[30]
`Japan .................................. 56-92621
`Jun. 15, 1981 [JP]
`Int. CI.4 ••.•.•.•.••••••••.•.•..•••••••.•.•..•.•••••••• GllC 13/00
`[51]
`[52] U.S. Cl . ...................................... 365/205; 365/63;
`365/208; 365/230
`[58] Field of Search ................... 365/63, 72, 205, 208,
`365/230
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,209,337 9/1965 Crawford ............................ 365/149
`3,678,473 7/1972 Wahlstrom .......................... 365/149
`3,771,148 11/1973 Aneshausley ....................... 365/149
`4,025,907 5/1977 Karp et al ........................... 365/149
`4,160,275 7/1979 Lee et al. ............................ 365/205
`4,287,576 9/1981 Pricer .. : ............................... 365/208
`OTHER PUBLICATIONS
`"A 1-µ,m Mo-Poly 64-kbit MOS RAM", IEEE Journal
`
`of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp.
`667-671.
`"One-Device Cells for Dynamic Random-Access
`Memories: A Tutorial"; IEEE Transactions on Electron
`Devices, Vol. ED-26, No. 6, Jun. 1979, pp. 839-852.
`Primary Examiner-Terrell W. Fears
`Attorney, Agent, or Firm-Lowe Price LeBlanc Becker
`& Shur
`ABSTRACT
`[57]
`A random access type semiconductor memory com(cid:173)
`prises a plurality of word lines (44; 54) of a metal ar(cid:173)
`ranged in parallel, at least first to fourth bit lines (BLl,
`BL2, BLl, BL2) orthogonal to the word lines, a plural(cid:173)
`ity of memory cells (48; 58a, 58b), each of which is
`arranged corresponding to one of cross points between
`each of the word lines and each of the bit lines, a first
`sense amplifier (SAl) connected to the first and third bit
`lines (BLl, BLl) and a second sense amplifier (SA2)
`connected to the second and fourth bit lines (BL2,
`BL2). The first sense amplifier (SAl) amplifies a voltage
`applied to said first or third bit line from a selected first
`memory cell and the second sense amplifier (SA2) am(cid:173)
`plifies a voltage applied to the second or fourth bit line
`from a selected second memory cell.
`
`13 Claims, 9 Drawing Figures
`
`WORD DRIVING CIRCUIT
`.. 'M..9
`DWI WLI WL2 ~ · ·
`
`40
`
`46
`
`SENSE
`
`AMP
`
`SA 2
`
`46
`
`SA4
`
`SENSE
`
`AMP
`
`SA I
`
`46
`
`SENSE
`
`AMP
`
`SA3
`i BL 3 "---,----'
`46
`
`I
`
`Micron Ex. 1025, p. 1
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`IPR2020-01008
`
`

`

`U.S. Patent Apr. 29, 1986
`
`Sheet 1 of 5
`
`4,586,171
`
`FIG. IA
`
`PRIOR ART rli
`
`I
`I
`I
`
`3
`
`2
`
`Fl G. I B
`
`PRIOR ART
`
`3
`
`2
`
`X
`
`N+
`
`y
`
`1.
`I ,_
`TRANSFER
`GATE
`
`.1
`
`\MEMORY
`CAPACITY
`
`p
`
`Micron Ex. 1025, p. 2
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`IPR2020-01008
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`

`

`U.S. Patent Apr. 29, 1986
`
`Sheet2 of5
`
`4,586,171
`
`FIG. 2
`PRrl OR ART
`
`LWL WORD
`
`DRIVING
`
`LO
`rLWLa,
`I BLI
`I
`
`10
`
`CIRCUIT
`RD
`
`RWL
`
`8
`
`3
`
`1 r t
`4
`4 4
`
`6
`
`Micron Ex. 1025, p. 3
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`

`

`U.S. Patent Apr. 29, 1986
`
`Sheet 3 of5
`
`4,586,171
`
`FIG.3A
`PRIOR ART
`
`FIG. 3B
`PRIOR ART
`
`X
`
`y
`
`16
`16
`,I
`f--r-1
`I•
`J
`TRANSFER MEMORY
`CAPACITY
`GATE
`
`Micron Ex. 1025, p. 4
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`IPR2020-01008
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`

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`U.S. Patent Apr. 29, 1986
`
`Sheet4 of5
`
`4,586,171
`
`FIG. 4
`PRIOR ART
`
`WORD DRIVING CIRCUIT
`WL
`
`20
`
`6
`
`SA
`2
`
`14 14
`
`14 14
`
`Fl G. 5
`PRIOR ART
`
`WORD DRIVING CIRCUIT
`WL
`
`30
`
`6
`
`Micron Ex. 1025, p. 5
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`U.S. Patent Apr. 29, 1986
`
`Sheet5 of5
`
`4,586,171
`
`FIG.6
`
`WORD DRIVING CIRCUIT
`· · 'M..9
`DWI WLI WL2 W1.3 · · ·
`
`40
`
`SA3
`i BL 3 ,...._.....-___.
`46
`
`I
`
`SENSE
`
`AMP
`
`SA I
`
`46
`
`SENSE
`
`AMP
`
`0
`
`SENSE
`
`AMP
`
`SA I
`
`56
`
`WORD DRIVING CIRCUIT f 5
`
`51
`
`I BLI
`
`46
`
`SENSE
`AMP'
`
`SA 2
`
`46
`
`SA4
`
`FIG.7
`
`SENSE
`
`AMP
`
`SA2
`
`6
`
`Micron Ex. 1025, p. 6
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`

`

`1
`
`SEMICONDUCTOR MEMORY
`
`4,586,171
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a semiconductor
`memory and more particularly, relates to an arrange(cid:173)
`ment of a memory array of a dynamic random access
`memory.
`2. Description of the Prior Art
`In a typical single transistor type of metal oxide semi(cid:173)
`conductor dynamic random access memory, the binary
`information "l" and "O" corresponds to the presence
`and absence of a charge to be stored in a metal oxide
`semiconductor capacitor, respectively. Such a semicon- l5
`ductor memory is adapted such that a charge stored in
`a metal oxide semiconductor capacitor is transferred to
`a bit line by turning a transfer gate on and a small
`change of the voltage caused at that time in the bit line
`by the presence or absence of the stored charge is de- 20
`tected by a sense amplifying circuit.
`Since a plurality of bit lines and a plurality of word
`lines constituting transfer gates are closely disposed in a
`matrix manner in X and Y directions which are orthog(cid:173)
`onal to each other, selection of materials for these lines 25
`is a very important factor for constituting a memory
`array.
`FIGS. IA and lB are a plan view and a cross sec(cid:173)
`tional view, respectively, for explaining a prior art
`memory cell wherein a bit line is formed of an N + 30
`diffusion region and a word line is formed of a metal.
`The memory cell comprises an N + diffusion region 1
`constituting a bit line, a first polysilicon layer 2 consti(cid:173)
`tuting a cell plate, a second polysilicon layer 3 constitut(cid:173)
`ing a transfer gate, an aluminium layer 4 constituting a 35
`work line, and a contact hole 5 for providing a word
`line signal to the transfer gate. Such structure has a
`shortcoming that the length of the transfer gate may
`often be different from transfer gate to transfer gate
`because self-alignment of the first and second polysili- 40
`con layers 2 and 3 is impossible or very difficult.
`FIG. 2 shows an example ofa memory array which is
`arranged by using memory cells shown in FIG. 1. Such
`a prior art memory array was necessarily of an open bit
`line structure wherein bit lines BL and bit lines BL are 45
`disposed on both sides of the sense amplifier circuit 6,
`respectively. More particularly, such an open bit line
`structure as shown in FIG. 2 comprises a plurality of
`sense amplifiers 6, a plurality of left word lines L WL
`disposed on the left side of the corresponding sense 50
`amplifier, a plurality of right word lines RWL disposed
`on the right side of the corresponding sense amplifiers.
`These word lines L WL and RWL are connected to the
`corresponding memory cell 8. The open bit line struc(cid:173)
`ture further comprises a pair of left dummy cells 7L, a 55
`pair of right dummy cells 7R, a left dummy word line
`LD and a right dummy word line RD. The dummy
`word lines LD and RD are connected to corresponding
`dummy cells 7L and 7R, respectively. The capacity of
`the dummy cells 7L and 7R are approximately half of 60
`the capacity of the memory cell. The contents of the
`memory cells 8 are read out by word signals on the
`word lines LWL and RWL. At the same time, the con(cid:173)
`tents of the dummy cells 7L or 7R are read out by a
`word signal on a dummy word line LD or RD. These 65
`word signals are supplied from a word driving circuit
`10. For example, if and when the information stored in
`the memory cell 8a is read out, word signals are applied
`
`2
`from the word driving circuit 10 to the word line
`LWLa and the dummy word line RD. The outputs
`from the memory cell 8a and the dummy cell 7R are
`differentially amplified and detected by the sense ampli-
`5 fying circuit 6 (SA2). However, such open bit line
`structure has a disadvantage that it erroneously oper(cid:173)
`ates when a common mode noise is applied to only the
`left or right bit line.
`FIGS. 3A and 3B are a plan view and a cross sec-
`10 tional view for explaining another prior art memory cell
`wherein a bit line is formed of an aluminium layer and a
`word line is formed of a polysilicon layer. Such mem(cid:173)
`ory cell comprises an aluminium layer 11 constituting a
`bit line, a first polysilicon layer 12 constituting a cell
`plate, a second polysilicon layer 14 constituting a word
`line and a contact hole 15 connecting a bit line to a
`memory cell. FIG. 4 shows an example of a memory
`array which is arranged by memory cells 18 shown in
`FIG. 3. This example is of a folded bit line structure
`wherein bit lines BL and bit lines BL are disposed on the
`same side of sense amplifying circuits 6. Thus, word
`lines WL, dummy word lines DWI and DW2, bit cells
`18 and dummy cells 17 are also disposed on the same
`side of the sense amplifying circuits 6. It is well-known
`that, as compared with an open bit line structure as
`shown in FIG. 2, the folded bit line structure is immune
`to a common mode noise and thus is suitable for a high
`density random access memory which is necessary to
`detect a small signal. On the other hand, in case where
`word lines 14 are formed of polysilicon layers 3 as
`shown in FIGS. 3 and 4, such folded bit line structure is
`not suitable for fast operation since an RC time constant
`of a polysilicon word line becomes larger than that of an
`aluminium word line. In order to avoid such problems,
`conventionally, a length of word line WL formed of a
`polysilicon layer 14 is made shorter by dividing a mem(cid:173)
`ory array, or a word line is formed of a metal having a
`high melting point, such as Mo. However, in the former
`approach, a chip size becomes very large and in the
`latter approach, mass production is very difficult.
`For the purpose of decreasing imbalance of noise in a
`folded bit line structure, a double cells/I bit or twin cell
`system has been proposed. FIG. 5 shows one example of
`such twin cell system. Such a twin cell system is
`adapted such that no dummy word lines are required
`and that if and when one word line is selected from a
`plurality of word lines WL formed of polysilicon layers
`14, two memory cells 18a and 18b are selected which
`store data in a complementary manner per a signal sense
`amplifying circuit 6, the complementary data from
`these two memory cells 18a and 18b being transferred to
`bit lines BL and bit lines BL through equal bit line
`length and entered to the sense amplifying circuit 6. For
`this reason, the imbalance, such as a delay of signal and
`the like, between a word line and a dummy word line
`can be completely eliminated. Nevertheless, a prior
`example as shown in FIG. 5 is not suitable for a fast
`operation since an RC time constant of a polysilicon
`word line is relatively large.
`SUMMARY OF THE INVENTION
`The present invention comprises a semiconductor
`memory wherein a plurality of word lines are formed of
`a metal and arranged in parallel with each other in a
`predetermined direction, first through fourth bit lines
`are arranged in parallel with each other in a direction
`generally orthogonal to said predetermined direction,
`
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`

`4,586,171
`
`3
`and including a plurality of memory cells. Each of the
`memory cells is arranged corresponding to one of a
`plurality of cross points between each of the word lines
`and each of the bit lines. The semiconductor memory
`further includes a first sense amplifier connected to the 5
`first and third bit lines for amplifying a voltage applied
`to the first or third bit line from a selected first memory
`cell, and a second sense amplifier connected to the sec(cid:173)
`ond and fourth bit lines for amplifying a voltage applied
`to the second or fourth bit line from a selected second to
`memory cell.
`In a preferred embodiment of the present invention,
`the first amplifier is disposed at one end of each bit line
`and the second sense amplifier is disposed at the other
`end of each bit line.
`In a more preferred embodiment of the present inven(cid:173)
`tion, a memory cell connected to the first bit line and a
`memory connected to the third bit line constitute a
`single bit and a memory cell connected to the second bit
`line and a memory cell connected to the fourth bit line 20
`constitute a single bit.
`Accordingly, a principal object of the present inven(cid:173)
`tion is to provide a semiconductor memory comprising
`a memory array of a folded bit line structure wherein a
`word line is formed of a metal so that an RC time con- 25
`stant of a word line can be decreased.
`Another object of the present invention is to provide
`a semiconductor memory which is immune to a com(cid:173)
`mon mode noise and is suitable for fast operation.
`These objects and other objects, features, aspects and 30
`advantages of the present invention will become more
`apparent from the following detailed description of the
`present invention when taken in conjunction with the
`accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. lA and lB are a plan view and a cross sec(cid:173)
`tional view for explaining a prior memory cell wherein
`a bit line is formed of an N + diffusion region and a word
`line is formed of a metal;
`FIG. 2 is a diagram showing a prior memory array
`arranged by using memory cells shown in FIG. 1;
`FIGS. 3A and 3B are a plan view and a cross sec(cid:173)
`tional view for explaining a prior memory cell wherein
`a bit line is formed of a metal and a word line is formed 45
`of a polysilicon;
`FIG. 4 is a diagram showing a prior memory array
`arranged by using memory cells shown in FIG. 3;
`FIG. 5 is a diagram showing a prior example of a
`memory array arranged in a twin cell manner;
`FIG. 6 is a diagram showing a memory array wherein
`word lines are formed of a metal layer and alternate bit
`lines are alternately connected to corresponding alter(cid:173)
`nate sense amplifying circuits disposed on both sides;
`and
`FIG. 7 is a diagram showing an embodiment wherein
`a memory array structure of the present invention is
`applied to a twin cell structure.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`FIG. 6 shows an example of a memory array folded
`bit line structure using a metal word line in accordance
`with the present invention. The present embodiment is
`characterized in that bit lines BL are alternately con(cid:173)
`nected to the left and right sense amplifying circuits 46.
`It can be understood that memory cell information and
`dummy cell information are correctly transferred to a
`
`4
`pair of bit lines BL and BL which are folded with re(cid:173)
`spect to a sense amplifying circuit 46 disposed on a left
`side or a right side by selecting a single word line WL
`and a left or a right dummy word line DWl or DW2.
`More particularly, the FIG. 6 embodiment includes a
`plurality of word lines WL, for example WLl to WLlO,
`which are formed of a metal and are arranged in parallel
`with each other in a vertical direction, and at least first
`through fourth bit lines BLl, BLl, BL2 and BL2 which
`are formed of an N + diffusion region and are arranged
`in parallel with each other in a direction generally or-
`thogonal to the direction of the word lines WL, that is,
`in a horizontal direction. A plurality of memory cells 48
`are formed, each of which is arranged corresponding to
`15 one of cross points between each of the word lines WLl
`to WLl0 and each of the bit lines BLl, BLl, BL2 and
`BL2. Basic structure per se of a memory cell and the
`memory cell array are substantially the same as shown
`in FIGS. 1 and 2 except for the specific connection and
`array in the FIG. 6 embodiment. The basic structure of
`FIG. 6 thus includes contact holes 45 for making
`contact between the metal wordlines WL and transfer
`gates 43 formed in a polysilicon layer. The FIG. 6 em(cid:173)
`bodiment further includes at least first and second sense
`amplifier SAl and SA2, the first sense amplifier SAl
`being disposed on one side of the memory cells and the
`second sense amplifier SA2 being disposed on the other
`side of the memory cells. In the FIG. 6 embodiment, the
`first and third bit lines BLl and BLl are connected to
`the first sense amplifier SAl, whereas the second and
`fourth bit lines BL2 and BL2 are connected to the sec-
`ond sense amplifier SA2. As a matter of course, the
`third amplifier SA3 may be provided on the same side as
`the first sense amplifier SAl and the fourth amplifier
`35 SA4 may be provided on the same side as the second
`sense amplifier SA2, and the like. Correspondingly, the
`fifth and the seventh bit lines BL3 and BL3 are con(cid:173)
`nected to the third sense amplifier SA3, whereas the
`sixth and eighth bit lines BL4 and BL4 (not shown) are
`connected to the fourth sense amplifier SA4. It should
`be noted that a pair of dummy cells 47a and 47b are
`provided between the first and second bit lines BLl and
`BL2 and in the vicinity of the first sense amplifier SAl
`and another pair of dummy cells 47c and 47d are pro(cid:173)
`vided between the third and fourth bit lines BLl and
`BL2 and in the vicinity of the second sense amplifier
`SA2. The pair of dummy cells 47a and 47b are associ(cid:173)
`ated with a dummy word line DW2 and another pair of
`dummy cells 47c and 47d are associated with a dummy
`word line DWl. A word driving circuit 40 is adapted
`such that if and when one of the odd word lines WLl,
`WL3, WL5, ... WL9 is selected, then the dummy word
`line DWl is selected and if and when one of the even
`word lines WL2, WL4, . . . WLlO is selected, the
`dummy word line DW2 is selected.
`In operation, assuming that the word line WL3 is
`selected and thus the dummy word line DWl is selected
`by the word driving circuit 40, an appropriate voltage is
`applied through a hole contact 45 and thus the corre-
`60 sponding transfer gate 43 is enabled. Correspondingly,
`the information stored in the memory cells 48a and 48b
`is transferred to the first and second sense amplfiers
`SAl and SA2, through the bit lines BLl and BL2, re(cid:173)
`spectively, whereas the information stored in the
`65 dummy cells 47c and 47d is transferred to the first and
`second sense amplifiers SAl and SA2, through the bit
`lines BLl and BL2, respectively. As a result, the infor(cid:173)
`mation from the memory cell 48a and the information
`
`40
`
`50
`
`55
`
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`4,586,171
`
`5
`from the dummy cell 47c are differentially amplified and
`detected by the first sense amplifier SAi, while the
`information from the memory cell 48b and the informa(cid:173)
`tion from the dummy cell 47d are also differentially
`amplified and detected by the second sense amplfier
`SA2.
`FIG. 7 shows another embodiment of the present
`invention wherein a folded bit line structure using a
`metal word line of the present invention is applied to a
`two cells/I bit structure or twin cell structure. In this 10
`embodiment, basically, a plurality of bits are provided
`between the first and second bit lines BLl and BL2,
`each bit being structured by a pair of memory cells 58a,
`and a plurality of bits are provided between the third
`and fourth bit lines BLl and BL2, each bit being struc- 15
`tured by a pair of memory cells 58b. If the word driving
`signal is applied to a word line WLn from a word driv(cid:173)
`ing circuit 50, then the data stored in one of the pair of
`memory cells 58a and the data stored in one of the pair
`of memory cells 58b are transferred through the first bit 20
`line BLl and the third bit line BLl, respectively, to the
`first sense amplifier SAi, and the data stored in the
`other of the pair of memory cells 58a and the data
`stored in the other of the pair of memory cells 58b are 25
`transferred through the second bit line BL2 and fourth
`bit line BL2, respectively, to the second sense amplifier
`SA2. The respective sense amplifiers SAi and SA2
`differentially amplify and detect the data. Although the
`FIG. 7 embodiment merely shows two sense amplifiers 30
`and four bit lines, it should be understood that the same
`is by way of illustration and example only. For example,
`it is readily understood that a plurality of bits provided
`between the second and third bit lines may be used in
`combination with another plurality of bits provided 35
`between the fifth and sixth bit lines (not shown), for
`example.
`In the FIG. 7 embodiment, no dummy word line is
`required and thus a problem of imbalance between a
`word line and a dummy word line is not caused. In 40
`addition, since the word line WL is formed of a metal,
`an RC time constant thereof becomes smaller and thus
`is suitable for fast operation. Furthermore, since a pair
`of memory cells 58a and a pair of memory cells 58b
`which respectively constitute a single bit are closely 45
`disposed and the data from the pair of memory cells 58a
`and the data from the pair of memory cells 58b are
`entered to a common sense amplifying circuit 56
`through alternate bit lines BL and BL having equal
`length, it can be understood that a variation of a gate 50
`length in a transfer gate which would be caused by a
`masking shift which is a shortcoming of overlapped
`gate structure as shown in FIG. lB, can be electrically
`balanced. In addition, as another meritorious effect of
`the present embodiment, a variation between the volt- 55
`ages necessary for reading "l" and "O" due to a change
`of a precharge voltage can be compensated, even if, for
`the purpose of quickly transmitting the content of the
`memory cell to the bit lines, the structure of the present
`embodiment is incorporated into an intermediate poten- 60
`tial precharge system in which a precharge voltage for
`a bit line is fed to approximately VDD/2.
`As described in the foregoing, in accordance with the
`structures of the memory arrays as shown in FIGS. 6
`and 7 to which the present invention is applied, a dy- 65
`namic random access memory can be obtained which is
`immune to a commmon mode noise, and have a good
`balance and in addition, is suitable for a fast operation.
`
`6
`Although the present invention has been described
`and illustrated in detail, it is clearly understood that the
`same is by way of illustration and example only and is
`not to be taken by way of limitation, the spirit and scope
`5 of the present invention being limited only by the terms
`of the appended claims.
`What is claimed is:
`1. A semiconductor folded bit line memory for a
`plurality of bits comprising:
`a plurality of word lines comprised of a metal and
`arranged in parallel with each other in a predeter-
`mined direction,
`at least first through fourth sequentially arranged bit
`lines arranged in parallel with each other and form(cid:173)
`ing a plurality of folded bit line pairs in a direction
`generally orthogonal to said predetermined direc-
`tion,
`a plurality of memory cells, each of which is arranged
`in correspondence with one of a plurality of cross
`points between each of said word lines and said bit
`lines,
`each of said bits being structured as an interconnected
`pair of first and second ones of said memory cells
`having signal path connections to said first and
`third bit lines or to said second and fourth bit lines
`for redundant storage of data in a complementary
`manner;
`first and second sense amplifying means connected to
`said first and third bit lines and to said second and
`fourth bit lines, respectively, thereby forming said
`first and third bit lines into one pair of folded bit
`lines and forming said second and fourth bit lines
`into another pair of folded bit lines, said sense am(cid:173)
`plifying means operable for amplifying a signal
`applied to said respective bit lines from selected
`first and second memory cells.
`2. A semiconductor memory in accordance with
`claim 1 wherein said first sense amplifying means is
`disposed at one end of each bit line and said second
`sense amplifying means is disposed at the other end of
`each bit line.
`3. A semiconductor memory in accordance with
`claim 1 including dummy bit structures each having a
`pair of dummy memory cells connected via different bit
`lines to different sense amplifying means.
`4. A multi-bit folded bit line memory structure com-
`prising:
`a plurality of two-cell bit structures;
`a plurality of sense amplifiers, alternate amplifiers
`located at opposite ends of a plurality of bit lines;
`each sense amplifier sensing signals on a correspond(cid:173)
`ing pair of alternate bit lines;
`said bit structures arranged in a plurality of sets;
`differing cells of each of said bit structures of any
`single set having signal path connections to a par(cid:173)
`ticular pair of corresponding bit lines connected to
`different ones of a single pair of sense amplifiers.
`5. A multi-bit folded bit line memory structure com-
`prising:
`a plurality of folded bit line pairs;
`a plurality of two-cell bit structures;
`a plurality of sense amplifiers having corresponding
`terminals connected to opposite ends of alternate
`ones of a plurality of corresponding sequential bit
`lines thereby forming said folded bit line pairs as
`pairs of alternate ones of said corresponding bit
`lines;
`said bit structures arranged in two sets,
`
`Micron Ex. 1025, p. 9
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`4,586,171
`
`10
`
`15
`
`7
`differing cells of a first set of bit structures having
`signal path connections to consecutive core(cid:173)
`sponding bit lines connected to different sense
`amplifiers, respectively; and
`differing cells of a second set of bit structures hav- 5
`ing signal path connections to consecutive oppo(cid:173)
`site bit lines connected to different sense amplifi(cid:173)
`ers, respectively;
`at least one bit line connected to cells of bit struc(cid:173)
`ture of different sets.
`6. A twin cell multi-bit folded bit line memory struc-
`ture including:
`a plurality of folded bit line pairs;
`at least 4 interleaved bit lines;
`two memory cells per bit;
`a pair of sense amplifying means associated with said
`bit lines;
`each of said sense amplifying means exclusively con(cid:173)
`nected to a pair of alternate bit lines thereby form-
`ing said folded bit line pairs as pairs of alternate
`ones of said bit lines;
`said two memory cells of each bit having signal path
`connections to consecutive ones of said bit lines
`connected to different sense amplifying means.
`7. A memory structure in accordance with claim 6
`including dummy bit structures each having a pair of
`dummy memory cells connected via different bit lines
`to different sense amplifying means.
`8. A semiconductor folded bit line memory for a 30
`plurality of bits comprising:
`a plurality of word lines comprised of a metal and
`arranged in parallel with each other in a predeter(cid:173)
`mined direction,
`a plurality of folded bit line pairs formed of at least 35
`first through fourth bit lines sequentially arranged
`in parallel with each other in a direction generally
`orthogonal to said predetermined direction,
`a plurality of memory cells, each of which is arranged
`in correspondence with one of a plurality of cross 40
`points between each of said word lines and said bit
`lines,
`each of said bits being structured as an interconnected
`pair of first and second ones of said memory cells
`having signal path connections to said first and 45
`third bit lines or to said second and fourth bit lines;
`
`8
`said word lines further comprising transfer gate
`means connected to pairs of said memory cells,
`first and second sense amplifying means having signal
`path connections to said first and third bit lines and
`to said second and fourth bit lines, respectively,
`thereby forming said first and third bit lines into
`one pair of folded bit lines and forming said second
`and fourth bit lines into another pair of folded bit
`lines, said sense amplifying means operable for
`amplifying a signal applied to said respective bit
`lines from selected first and second memory cells
`connected directly thereto,
`said first and second sense amplifying means disposed
`at opposite ends of said bit lines.
`9. A semiconductor folded bit line memory structure
`as recited in claim 8 further comprising transfer gate
`means formed in a polysilicon layer and
`contact means for providing contact between said
`metal word lines and said transfer gate means.
`10. A semiconductor folded bit line memory structure
`as recited in claim 6, further comprising a plurality of
`word lines comprised of a metal and arranged substan(cid:173)
`tially perpendicularly to said bit lines,
`transfer gate means formed in a polysilicon layer and
`contact means for providing contact between said
`metal word lines and said transfer gate means.
`11. A semiconductor folded bit line memory structure
`as recited in claim 5, further comprising a plurality of
`word lines comprised of a metal and arranged substan(cid:173)
`tially perpendicularly to said bit lines,
`transfer gate means formed in a polysilicon layer and
`contact means for providing contact between said
`metal word lines and said transfer gate means.
`12. A semiconductor folded bit line memory structure
`as recited in claim 4, further comprising a plurality of
`word lines comprised of a metal and arranged substan(cid:173)
`tially perpendicularly to said bit lines,
`transfer gate means formed in a polysilicon layer and
`contact means for providing contact between said
`metal word lines and said transfer gate means.
`13. A semiconductor folded bit line memory structure
`as recited in claim 1 further comprising transfer gate
`means formed in a polysilicon layer and
`contact means for providing contact between said
`metal word lines and said transfer gate means.
`* * * * *
`
`20
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`25
`
`50
`
`55
`
`60
`
`65
`
`Micron Ex. 1025, p. 10
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`