United States Patent [19J
`Sung
`
`I 1111111111111111 11111 lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US005858831A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,858,831
`Jan. 12, 1999
`
`[54]
`
`PROCESS FOR FABRICATING A HIGH
`PERFORMANCE LOGIC AND EMBEDDED
`DRAM DEVICES ON A SINGLE
`SEMICONDUCTOR CHIP
`
`[75]
`
`Inventor: Janmye Sung, Yang-Mei, Taiwan
`
`[73]
`
`Assignee: Vanguard International
`Semiconductor Corporation,
`Hsin-Chu, Taiwan
`
`[21]
`
`Appl. No.: 31,683
`
`[22]
`
`Filed:
`
`Feb. 27, 1998
`
`[51]
`[52]
`[58]
`
`[56]
`
`Int. Cl.6
`........................ H0lL 21/8242; HOlL 21/20
`U.S. Cl. ............................................. 438/241; 438/396
`Field of Search ..................................... 438/241, 396,
`438/210, 303, 275, 152
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,260,226
`5,292,677
`5,296,402
`5,371,026
`5,395,784
`5,554,557
`5,612,214
`5,668,035
`5,668,036
`5,716,862
`5,750,426
`
`....................... 438/210
`11/1993 Sawanda et al.
`3/1994 Dennison ................................ 438/396
`3/1994 Ryou ....................................... 438/152
`12/1994 Hayden et al.
`......................... 438/275
`3/1995 Lu et al.
`................................... 437/52
`9/1996 Koh ......................................... 438/396
`3/1997 Arima ..................................... 438/241
`9/1997 Fang et al. .............................. 438/239
`9/1997 Sune ........................................ 438/253
`2/1998 Ahmad et al. .......................... 438/303
`5/1998 Rajkanan et al. ....................... 438/210
`
`5,759,889
`
`6/1998 Sakao ...................................... 438/241
`
`Primary Examiner-John F. Niebling
`Assistant Examiner-Christopher Lattin
`Attorney, Agent, or Firm-George 0. Saile; Stephen B.
`Ackerman
`
`[57]
`
`ABSTRACT
`
`A process for creating a region of high performance logic
`devices, and a region of low cost memory devices, on a
`single semiconductor chip, has been developed. The process
`features CMOS logic devices, comprised of polycide gate
`structures, residing on a thin silicon dioxide gate insulator
`layer. An N type polysilicon layer, used as part of a polycide
`structure, is used with the N channel CMOS devices, while
`a P type polysilicon layer, is used with the P channel CMOS
`devices. DRAM memory devices are comprised of polycide
`gate structures, featuring only an N type polysilicon layer,
`on a silicon dioxide gate insulator layer, that is thicker than
`the gate silicon oxide layer used with the high performance
`logic devices. A minimum of additional photolithographic
`masking procedures is used to improve the performance of
`the logic region, one mask to allow specific polycide gate
`structures to be created with either P type or N type
`polysilicon, and another additional mask used to allow
`different gate insulator layers to be formed in each specific
`region. A large angle, ion implantation procedure, is used to
`form lightly doped source and drain regions, under the
`silicon nitride spacers on the sides of polycide gate
`structures, in both logic and DRAM memory regions.
`
`24 Claims, 20 Drawing Sheets
`
`50
`
`J
`
`1816
`
`17
`20b 281816
`
`17
`
`20b 28
`
`60
`
`J
`
`34
`
`29
`
`2
`6
`
`Micron Ex. 1023, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 1 of 20
`
`5,858,831
`
`N
`
`•
`
`Micron Ex. 1023, p. 2
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 2 of 20
`
`5,858,831
`
`N
`
`<.O
`
`.-
`
`0
`<.O~
`
`0
`I [ )~
`
`•
`
`Micron Ex. 1023, p. 3
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 3 of 20
`
`5,858,831
`
`CX)
`
`0
`I f )~
`
`•
`
`,-
`
`Micron Ex. 1023, p. 4
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 4 of 20
`
`5,858,831
`
`,- 0
`0
`,- ,- CJ)
`
`N
`
`0
`CJ)
`
`v
`
`r-,...
`
`•
`~
`~
`~
`
`0
`lf) ~ N
`,-
`
`>
`
`,-
`
`N
`,-
`
`0
`,- 0
`, - ,- CJ)
`
`Micron Ex. 1023, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 5 of 20
`
`5,858,831
`
`lO
`
`..----
`
`..----
`
`CX)
`
`0
`0)
`
`..----
`
`0
`lO ~
`
`0
`L ( )~
`
`N
`
`lO
`
`N
`
`•
`
`0
`0)
`
`..----
`
`Micron Ex. 1023, p. 6
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 6 of 20
`
`5,858,831
`
`<.D
`
`.....
`
`N
`
`N
`
`0
`LO~
`
`.D
`m
`
`.....
`
`•
`
`0
`m
`
`Micron Ex. 1023, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 7 of 20
`
`5,858,831
`
`.0
`I")
`
`N
`
`N
`
`•
`
`(.)
`0)
`
`Micron Ex. 1023, p. 8
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 8 of 20
`
`5,858,831
`
`(!)
`
`.....
`
`N
`
`CX)
`
`0
`I . ( )~
`
`•
`
`u
`O')
`
`Micron Ex. 1023, p. 9
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 9 of 20
`
`5,858,831
`
`0
`lO ~
`
`N
`
`CX)
`
`0
`LO~
`
`m CX) I' lO .0
`.--- .---
`.--- .--- m
`
`•
`
`Micron Ex. 1023, p. 10
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 10 of 20
`
`5,858,831
`
`N
`
`CX)
`
`.0
`I"')
`.....
`
`<.O
`
`0
`<.O~
`
`I'--.
`
`0
`.0
`LO ~ 0
`N
`
`...............
`
`I'--. <.O
`.0
`CX)
`............... 0)
`
`•
`
`.0
`0
`N
`
`I'--. <.O (.)
`CX)
`.- .-.-Ol
`
`.---
`
`Micron Ex. 1023, p. 11
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 11 of 20
`
`5,858,831
`
`0
`{() ~
`
`N
`
`OC)
`
`..0
`0
`N
`~------f==:::i:;n-K""'rr
`.--
`~ - - - -
`0
`LO~ OC> _ _.
`
`'u..-1.....---..l
`
`N
`N
`
`•
`
`Micron Ex. 1023, p. 12
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 12 of 20
`
`5,858,831
`
`0
`( ( )~
`
`0
`L i )~
`
`.----
`(()
`.----
`CX)
`.----
`
`..........
`
`.0
`I"')
`.----
`
`v
`
`I"--
`
`...--..
`Cl..
`..........
`...--.. c.o
`+N
`Cl..
`..........
`r--.
`N
`
`C\2
`
`~
`
`•
`l)
`~
`~
`
`CX) I"-- lO U
`.----
`.---- .---- 0)
`
`Micron Ex. 1023, p. 13
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 13 of 20
`
`5,858,831
`
`0
`(D ~
`
`0
`0
`NOO
`,-
`I'
`,- (D
`
`.D ,-
`0)
`
`.0
`0
`N
`I'
`,-
`(D
`.----
`CX)
`.----
`
`0
`I . [ )~
`
`.0
`0
`N
`I'
`..--
`(D
`,-
`CX)
`,-
`
`CX)
`N
`
`N
`
`CX)
`
`.D
`I'"')
`,-
`
`(D
`
`...__..
`
`.D
`I'"')
`,-
`u
`0)
`
`...__..
`-w
`+N
`a..
`...__..
`r---.
`N
`
`Cf)
`""
`
`•
`~
`"--i
`~
`
`Micron Ex. 1023, p. 14
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 14 of 20
`
`5,858,831
`
`0)
`N
`
`0
`(0 ~
`
`0
`0
`NCX)
`, -
`~
`,- (0
`
`, -
`
`.0
`0)
`
`0
`LO~
`
`~
`..----
`(0
`, -
`CX)
`,-
`
`..----
`(0
`..----
`CX)
`..----
`
`N
`
`CX)
`
`.0
`I")
`..----
`
`.0
`I")
`, -
`
`u
`O')
`~ .........
`0..
`......... c.o
`+N
`0..
`r--.
`N
`
`~
`
`~
`"""
`
`•
`l:)
`~
`~
`
`Micron Ex. 1023, p. 15
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jan. 12, 1999
`
`Sheet 15 of 20
`
`5,858,831
`
`0)
`N
`
`.-
`
`lD
`
`.-
`
`0
`I")
`
`0
`lD ~
`
`.0
`0
`NCX)
`.-
`
`I'--
`.---- lD
`.-
`
`.-
`
`.-
`lD
`.-
`CX)
`.----
`
`N
`
`,-..
`
`z ..__
`.---
`I"')
`
`CX)
`
`.0
`0)
`
`.0
`I")
`.----
`
`.0
`I")
`.----
`~ u
`
`0)
`
`..__
`,-.. t.O
`+N
`a..
`..__
`r--.
`N
`
`lO
`""
`•
`l)
`~
`~
`
`Micron Ex. 1023, p. 16
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`~
`~
`00
`....
`00
`Ul
`00
`....
`Ul
`
`0
`N
`0 ....,
`'"""' O'I
`~ ....
`'JJ. =(cid:173)~
`
`\0
`\0
`'"""'
`\0
`
`~
`
`'"""' N
`~ =
`
`~
`
`2
`
`31 (N)
`
`13b 9b 8
`
`6
`
`F JG. 16
`
`26(P) 9c 13b
`
`27(P+) / 7 / 4
`
`1
`
`6
`
`13b
`
`29
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`J
`
`60
`
`J
`
`50
`
`Micron Ex. 1023, p. 17
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`~
`~
`00
`....
`00
`Ul
`00
`....
`Ul
`
`0
`N
`0 ....,
`'"""'
`-..J
`~ ....
`'JJ. =(cid:173)~
`
`\0
`\0
`'"""'
`\0
`'"""' ~N
`?
`~
`~
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`2
`
`31 (N)
`
`1 3b 9b 8
`
`6
`
`FIG. 17
`26(P) 9c 1 3b
`
`27(P+)/ 7
`
`1
`
`6
`
`13b
`
`29
`
`34
`
`l ~//2
`
`If' /I/ /I
`
`\
`
`I
`33
`
`35
`
`36
`
`J
`60
`
`1,7 20b 3435
`
`20b/281816
`
`29 J
`
`7
`
`50
`
`28
`
`1816~
`
`Micron Ex. 1023, p. 18
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`~
`~
`00
`....
`00
`Ul
`00
`....
`Ul
`
`0
`N
`0 ....,
`'"""' 00
`~ ....
`'JJ. =(cid:173)~
`
`\0
`\0
`'"""'
`\0
`'"""' ~N
`?
`~
`~
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`1
`
`6
`
`13b
`
`29
`
`34
`
`2
`
`33
`
`J
`
`60
`
`FIG. 18
`
`26(P) 9c 13b
`
`27(P+)/ 7
`
`34
`
`20b 28
`
`7
`
`20b 2818 1 6 \
`
`7
`1.
`
`18 16
`
`J
`
`50
`
`Micron Ex. 1023, p. 19
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`~
`~
`00
`....
`00
`Ul
`00
`....
`Ul
`
`0
`N
`0 ....,
`'"""'
`\0
`~ ....
`'JJ. =(cid:173)~
`
`\0
`\0
`'"""'
`\0
`'"""' ~N
`?
`~
`~
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`1
`
`6
`2
`
`13b
`
`29
`
`34
`
`31(N)
`
`J
`
`60
`
`FIG. 19
`
`26(P) 9c 1 3b
`
`27(P+)/ 7 I 4
`
`29
`
`34
`
`20b 28
`
`7
`
`20b 281816\
`
`7
`
`18161.
`
`J
`
`50
`
`Micron Ex. 1023, p. 20
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`~
`~
`00
`....
`00
`Ul
`00
`....
`Ul
`
`~ ....
`'JJ. =-~
`
`0
`N
`0 ....,
`0
`N
`
`\0
`\0
`'"""'
`\0
`'"""' ~N
`?
`~
`~
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`6
`2
`
`13b
`
`I
`
`\
`
`F JG. 20
`
`13b
`
`I
`
`I
`
`JJ I\ J I I
`
`I
`
`f
`
`I I
`
`I\ 1111\ I \\
`
`1111 \ \ I I
`
`4-\--\
`
`I I, '\I -r-29
`
`34
`
`II, ,I I
`
`I I'-,I I
`
`.
`
`I I, '-I I
`
`I I
`
`I
`
`I
`
`I I
`
`11
`
`.I I
`
`r J I I
`
`I\ I .A
`
`f I
`
`44
`
`41
`
`60 J 40
`
`46 43 45 42 J
`
`50
`
`'\.I 17'"-ri '" "' ~ '" I > I
`
`I "J t;,,\-\,1 I '
`
`I>
`
`I
`
`' '
`
`I
`
`I
`
`I I
`
`I I
`
`I /1 I !-,+-bl II\
`
`11-,+~ .. n 1/1
`
`28
`29-I
`
`I
`
`Micron Ex. 1023, p. 21
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`5,858,831
`
`1
`PROCESS FOR FABRICATING A HIGH
`PERFORMANCE LOGIC AND EMBEDDED
`DRAM DEVICES ON A SINGLE
`SEMICONDUCTOR CHIP
`BACKGROUND OF THE INVENTION
`(1) Field of the Invention
`This invention relates to methods used to fabricate semi(cid:173)
`conductor devices, and more specifically a process used to
`fabricate high performance logic devices and low cost
`memory devices, on a single semiconductor chip.
`(2) Description of Prior Art
`The semiconductor industry is continually striving to
`increase device performance, while still maintaining, or
`even reducing the cost of these same devices. Micro(cid:173)
`miniaturization or the ability to create semiconductor
`devices with sub-micron features, has allowed the
`performance, and the cost objectives, to be partially realized.
`The use of sub-micron features result in a decrease in
`performance degrading, parasitic capacitances, thus allow(cid:173)
`ing performance improvements to be realized. In addition
`the use of sub-micron features allows smaller semiconductor
`chips to be created, with the smaller chips still offering
`device densities comparable to device densities achieved
`with larger chips, thus allowing a greater number of chips to
`be realized from a specific size starting semiconductor
`substrate, thus reducing processing costs.
`Another direction taken by the semiconductor industry, in
`an attempt to reduce cost while still improving device
`performance, has been the integration of logic devices, and
`memory devices, on the same semiconductor chip. This
`integration improves performance by decreasing undesirable
`delays that occur between memory devices, located on one
`semiconductor chip, and logic devices, located on a different
`chip. In addition the processing costs for integrating
`memory and logic devices on the same semiconductor chip,
`are reduced due to the sharing of specific process steps, used
`to fabricate both types of devices.
`Efforts have been ongoing by the semiconductor industry,
`in attempting to incorporate both logic and memory require(cid:173)
`ments on a single semiconductor chip. Dennison, in U.S.
`Pat. No. 5,292,677, describes a process for integrating
`complimentary metal oxide semiconductor, (CMOS),
`devices, with dynamic random access memory, (DRAM),
`devices, on a single semiconductor chip. However that
`invention does not share as many processing steps needed to
`realize significant cost reductions, nor does it offer a process
`needed for high performance logic devices. This invention
`will describe an integrated process, which features high
`performance CMOS devices, realized via many innovations
`such as the use of gate insulator layers, thinner than the gate
`insulator layers used for the DRAM devices. It will also
`feature the use of conductive silicide layers for source and
`drain regions of the CMOS devices, formed using a process
`sequence that reduces a possible bridging mechanism
`between gate structures and substrate. In addition this new
`process, for forming high performance logic, and embedded
`memory devices, on a single semiconductor chip, will be
`practiced using many process sequences, shared by both
`type devices, with the addition of only two photolitho(cid:173)
`graphic masking procedures, added to the CMOS logic
`process sequence, which enables improved performance of
`the logic region to be realized while and still achieve cost
`reductions.
`
`SUMMARY OF THE INVENTION
`It is an object of this invention to provide a process for
`fabricating high performance CMOS logic devices, and
`embedded DRAM memory devices, on the same semicon(cid:173)
`ductor chip.
`
`2
`It is another object of this invention to use only one
`additional photolithographic masking procedure, to allow
`formation of a thin gate insulator layer for the high perfor(cid:173)
`mance CMOS devices, while a thicker gate insulator layer is
`5 used for the embedded DRAM memory devices.
`It is still another object of this invention to again add only
`one photolithographic masking procedure, to create a P type,
`polysilicon, for the polycide gate structure, used with the P
`channel CMOS devices, while creating N type, polysilicon,
`10 for the polycide gate structures, used with the N channel
`CMOS devices, and with the embedded DRAM memory
`devices.
`It is still yet another object of this invention to use a
`process to eliminate salicide, (Self ALigned metal
`15 siliCIDE), bridging, between gate and substrate, by a pro(cid:173)
`cess sequence which only forms metal silicide on exposed
`source and drain regions.
`In accordance with the present invention a fabrication
`process is described for integrating high performance
`20 CMOS logic devices, and embedded DRAM memory
`devices, on a single semiconductor chip. After formation of
`P well regions for both the embedded DRAM devices, and
`N channel CMOS devices, as well as the formation of an N
`well region, for the P channel CM OS devices, a deep, N type
`25 layer, is formed in the semiconductor substrate, in the
`DRAM region, to isolate a subsequent DRAM cell from the
`underlying substrate. After creation of a thin gate insulator
`layer, for the CMOS devices, and a thicker gate insulator
`layer, for the DRAM devices, an undoped polysilicon layer
`30 is deposited, followed by creation of shallow trench isola(cid:173)
`tion regions, used to separate subsequent P channel and N
`channel CMOS devices, in the logic region of the semicon(cid:173)
`ductor chip, as well as separating the memory region of
`embedded DRAM devices, from the high performance logic
`35 region comprised of CMOS devices. A process sequence,
`using only one photolithographic masking procedure is next
`used to N type dope the polysilicon region to be used for the
`DRAM devices, as well as the polysilicon region, to be used
`for N channel CMOS, while doping the polysilicon region
`40 used for the P channel CMOS devices, P type. Silicon nitride
`capped, polycide gate structures, comprised of titanium
`silicide on N type, or P type polysilicon, are next formed,
`followed by creation of silicon nitride spacers, on the sides
`of the polycide gate structures, only in the CMOS logic
`45 region of the semiconductor chip. An ion implantation
`procedure, using a large tilt angle, and low dose, is used to
`create N type, lightly doped source and drain regions, under
`silicon nitride spacers, for N channel CMOS devices, fol(cid:173)
`lowed by a higher dose, lower tilt angle, procedure, used to
`50 create N type, heavily doped source and drain regions, for
`the same N channel CMOS device. A similar ion implanta(cid:173)
`tion sequence is used to create the P type, lightly doped
`source and drain, and the P type, heavily doped source and
`drain regions, for the P channel CMOS devices. Metal
`55 silicide is next formed on the exposed source and drain
`regions, in the CMOS region, of the semiconductor chip.
`A silicon oxide layer is next deposited, planarized, and
`removed in areas between polycide gate structures, in the
`DRAM region. After formation of silicon nitride spacers, on
`60 the sides of the polycide gate structures in the DRAM
`region, ion implantation procedures are performed, using a
`large tilt angle implant, to create N type, lightly doped
`source and drain regions, again under silicon nitride spacers.
`Polysilicon plugs are next formed between polycide gate
`65 structures, in the DRAM region of the semiconductor chip.
`Another silicon oxide layer is deposited and patterned to
`create a storage node opening, exposing the top surface of a
`
`Micron Ex. 1023, p. 22
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`5,858,831
`
`3
`polysilicon plug. A stacked capacitor structure is formed in
`the storage node opening, in the silicon oxide layer, over(cid:173)
`lying and contacting the polysilicon plug, in the DRAM
`region. An insulator layer is next deposited, followed by
`photolithographic and dry etch procedures, used to open
`contact holes and via holes to the stacked capacitor, and bit
`line regions, in the DRAM region, as well as to the gate, and
`source and drain regions in the CMOS logic region. Metal
`deposition, followed by removal of unwanted metal, are
`employed to form the metal contact structures, in the contact
`and via holes, followed by additional metal deposition and
`patterning, used to create metal interconnect structures, for
`both the DRAM memory devices, and for the CMOS logic
`devices.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The object and other advantages of this invention are best
`described in the preferred embodiment with reference to the
`attached drawings that include:
`FIGS.1-20, which schematically, in cross-sectional style,
`illustrates key stages of fabrication used to construct the
`CMOS devices, used for high performance logic, and the
`embedded DRAM devices, used for low cost memory, on a
`single semiconductor chip.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The fabrication process used to create high performance
`logic regions, and low cost memory regions, on a single
`semiconductor chip will now be covered in detail. The
`DRAM device described in this invention is comprised of N
`channel transfer gate transistors. If desired, this invention
`can be used to create DRAM device, comprised of P channel
`transfer gate transistors. This can be accomplished by cre(cid:173)
`ating an N well region, in the P type semiconductor
`substrate, and creating P type lightly doped, and P type
`heavily doped source and drain regions.
`FIG. 1, shows region 50, of semiconductor substrate 1, to
`be used for fabrication of high performance CMOS logic
`devices, while region 60, of semiconductor substrate 1, will
`be used for embedded DRAM memory device. A P type,
`single crystalline silicon substrate 1, having a <100> crys(cid:173)
`tallographic orientation is used. A photolithographic mask(cid:173)
`ing procedure, using photoresist shape 3, is used as a mask
`to allow N well region 4, to be formed only in openings in
`photoresist shape 3, in logic region 50, via ion implantation
`of phosphorous and arsenic. A high energy boron, ion
`implantation procedure, allows formation of P well regions
`2, in regions of semiconductor substrate 1, underlying
`photoresist shape 3, in DRAM region 60, as well as in an
`area of logic region 50, with P well regions 2, needed for N
`channel CMOS devices. The high energy boron implants are
`located deep into semiconductor substrate 1, in regions
`unprotected photoresist, under N well regions 4, and do not
`influence device characteristics. Photoresist shape 3, is
`removed using plasma oxygen ashing and careful wet
`cleans.
`FIG. 2, shows the formation of a deep, N type region 6,
`used to isolate DRAM region 60, from semiconductor
`substrate 1. This is performed using thick photoresist shape
`5, greater then 5.0 uM in thickness, protecting logic region
`50, from a high energy phosphorous ion implantation
`procedure, performed at an energy between about 1 to 2
`Me V, at a dose between about 1E12 to 1E13 atoms/cm2
`,
`creating isolating deep N type region 6. In addition, a
`threshold adjust, ion implantation procedure, using boron, at
`
`5
`
`4
`an energy between about 1 to 10 Ke V, and at a dose between
`about lEll to 1E12 atoms/cm2
`, is used to alter the channel
`doping characteristics near the surface of semiconductor
`substrate 1, in DRAM region 60. The threshold adjust
`region, created in DRAM region 60, is not shown in the
`drawings, but is used to create DRAM devices with higher
`threshold voltages than the N channel CMOS devices that
`will be subsequently created in logic region 50.
`After removal of thick photoresist shape 5, via plasma
`10 oxygen ashing and careful wet cleans, a thin silicon dioxide
`layer is thermally grown, to a thickness between about 20 to
`40 Angstroms, on semiconductor substrate 1. A photoresist
`shape, (not shown in the drawings, and one of the two
`additional masking steps added to the process to improve
`15 logic performance), is used to mask DRAM region 60, from
`a wet etch procedure used to remove the thin silicon dioxide
`layer from logic region 50. After removal of the photoresist
`shape, using plasma oxygen ashing and careful wet cleans,
`another thermal oxidation procedure is performed, in an
`20 oxygen - steam ambient, creating silicon dioxide gate insu(cid:173)
`lator layer 7, in logic region 50, at a thickness between about
`40 to 60 Angstroms, while the same thermal oxidation
`procedure results in a silicon dioxide gate insulator layer 8,
`comprised partially of the previously used thin silicon oxide
`25 layer, with a final thickness now between about 50 to 70
`Angstroms. This is schematically shown in FIG. 3.
`An undoped polysilicon layer 9a, is next deposited using
`low pressure chemical vapor deposition, (LPCVD),
`procedures, to a thickness between about 800 to 1200
`30 Angstroms. A silicon oxide layer 10, is then deposited via
`LPCVD or plasma enhanced chemical vapor deposition,
`(PECVD), procedures, to a thickness between about 100 to
`300 Angstroms, followed by a deposition of a silicon nitride
`layer 11, deposited using LPCVD or PECVD procedures, to
`35 a thickness between about 1200 to 2000 Angstroms. A
`photoresist shape 12, is used as a mask allowing an aniso(cid:173)
`tropic RIE procedure to create shallow trenches 13a, using
`CHF3 as an etchant for silicon nitride layer 11, for silicon
`oxide layer 10, for gate insulator layer 7, and for gate
`40 insulator layer 8, while using Cl2 as an etchant for undoped
`polysilicon layer 9a, and for semiconductor substrate 1.
`Shallow trenches 13a, schematically shown in FIG. 4, are
`created to a depth of between about 3000 to 5000
`Angstroms, in semiconductor substrate 1. After removal of
`45 photoresist shape 12, via plasma oxygen ashing and careful
`wet cleans, a silicon oxide layer is deposited, via high
`density plasma chemical vapor deposition, (HDPCVD)
`procedures, completely filling shallow trenches 13a. A
`chemical mechanical polishing, (CMP), procedure is used to
`50 remove unwanted silicon oxide, from the top surface of
`silicon nitride layer 11, followed by the removal of silicon
`nitride layer 11, and silicon oxide layer 10, via a wet etch
`procedure, using buffered HF for silicon oxide layer 10, and
`using a hot phosphoric acid for silicon nitride layer 11,
`55 resulting in insulator filled, shallow trench isolation, (STI),
`regions, 13b, schematically shown in FIG. 5.
`A silicon nitride layer 14, is next deposited using LPCVD
`or PECVD procedures, to a thickness between about 1000 to
`1500 Angstroms. A photoresist shape, (not shown in the
`60 drawings, and the second mask added to the process for
`logic performance improvement), is used as a mask to allow
`removal of silicon nitride layer 14, in DRAM region 60, and
`in the area of logic region 50, to be used for N channel
`CMOS devices. After removal of the masking photoresist
`65 shape, via plasma oxygen ashing and careful wet cleans, a
`POC13 procedure is used to dope exposed regions of
`undoped polysilicon layer 9a, and creating N type polysili-
`
`Micron Ex. 1023, p. 23
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`5,858,831
`
`5
`con layer 9b, in DRAM region 60, as well as in logic region
`50, to be used for N channel CMOS devices. The furnace
`POC13 procedure was chosen for polysilicon doping, rather
`then an ion implantation procedure, which can damage
`underlying gate insulator layers. The result of this procedure
`is schematically shown in FIG. 6. A silicon oxide layer 15,
`is thermally grown, on N type doped, polysilicon layers 9b,
`to a thickness between about 300 to 600 Angstroms, allow(cid:173)
`ing removal of silicon nitride layer 14, via use of a hot
`phosphoric acid solution. A blanket, boron ion implantation
`procedure is used, at an energy between about 0.5 to 1 Ke V,
`and at a dose between about 1E15 to 5E15 atoms/cm2
`,
`resulting in exposed, undoped polysilicon layer 9a, in an
`area of logic region 50, to be used for subsequent P channel
`CMOS devices, to be converted to P type polysilicon layer
`9c, with a surface concentration between about 0.75 to
`1.25E21 atoms/cm3
`• The N type dopant concentration for N
`type polysilicon layer 9b, is between about 0.75 to 1.25E22,
`and therefore even if N type polysilicon layer 9b, was
`subjected to the boron ion implantation procedure, the level 20
`of P type compensation still would not be enough to convert
`N type polysilicon layer 9b. This is schematically shown in
`FIG. 7.
`After removal of silicon oxide layer 15, via a wet etch
`procedure, a titanium nitride layer 16, is deposited using R.F.
`sputtering procedures, to a thickness between about 80 to
`120 Angstroms, followed by the deposition of a titanium
`disilicide layer 17, deposited using R.F. sputtering proce(cid:173)
`dures to a thickness between about 750 to 1250 Angstroms,
`and finally a silicon nitride layer 18, is deposited using
`PECVD or LPCVD procedures, to a thickness between
`about 1500 to 2500 Angstroms. The result of these deposi(cid:173)
`tions is schematically shown in FIG. 8. Photoresist shapes
`19, are next employed as a mask, allowing polycide gate
`structures to be formed. Polycide, (titanium disilicide on
`polysilicon), structures, capped with silicon nitride, are
`formed via anisotropic RIE procedures, using CHF 3 as an
`etchant for silicon nitride layer 18, and using Cl2 as an
`etchant for titanium disilicide layer 17, for titanium nitride
`layer 16, and for the polysilicon layers. Polycide structures
`in DRAM region 60, and in the area of the logic region 50,
`used for N channel CMOS devices, are comprised with N
`type polysilicon layer 9b, while the polycide structure, in the
`area of the logic region 50, used for P channel CMOS
`devices, is comprised with P type polysilicon layer 9c. This
`is schematically shown in FIG. 9.
`After removal of photoresist shapes 19, via plasma oxy(cid:173)
`gen ashing and careful wet cleans, a composite layer of
`underlying silicon oxide, and overlying silicon nitride, are
`deposited using PECVD or LPCVD procedures. The thin
`silicon oxide layer, about 100 Angstroms in thickness, is not
`shown in the drawings, and is used to separate silicon nitride
`layer 20a, from direct contact with silicon or polysilicon
`regions. Silicon nitride layer 20a, shown schematically in
`FIG. 10, in DRAM region 60, is deposited to a thickness
`between about 600 to 1000 Angstroms. A photoresist shape
`21, is used as a mask to protect silicon nitride layer 20a,
`from an anisotropic RIE procedure, performed in logic
`region 50, via use of CHF3 as an etchant, creating silicon
`nitride spacers 20b, on the sides of the polycide structures,
`in logic region 50. The spacers are actually composite
`spacers of silicon nitride on silicon oxide, however to avoid
`complexity it will be identified as silicon nitride spacers 20b.
`This is schematically shown in FIG. 10.
`After removal of photoresist shape 21, via plasma oxygen
`ashing and careful wet cleans, photoresist shape 22, is
`created, and used as a block out mask, allowing lightly
`
`6
`doped, and heavily doped, source and drain regions to be
`established in logic region 50, in an area used for the N
`channel CMOS devices. First an N type, lightly doped
`source and drain region 23, is created via ion implantation
`5 of arsenic or phosphorous ions, at an energy between about
`30 to 50 Ke V, and at a dose between about 1E13 to 3E13
`atoms/cm2
`. This implantation procedure is performed using
`a tilt angle between about 30° to 40°, to allow placement of
`the implanted N type species, under silicon nitride spacers
`10 20b. An N type, heavily doped source and drain region 24,
`is than formed by ion implantation of arsenic or
`phosphorous, at an energy between about 30 to 50 Ke V, at
`a dose between about 1E15 to 5E15 atoms/cm3
`, and using a
`angle between about O to 7°. Regions of exposed silicon
`15 dioxide gate insulator layer 7, not covered by the polycide
`gate structure, is removed using a wet etch procedure. The
`result of these procedures is schematically illustrated in FIG.
`11.
`A similar process sequence is next employed to create
`both lightly doped, and heavily doped, P type source and
`drain regions, in logic region 50, in an area used for P
`channel CMOS devices. After removal of photoresist shape
`22, via plasma oxygen ashing and careful wet cleans,
`photoresist shape 25, is formed, and used as a block out
`25 mask, allowing ion implantation only to be performed in
`regions where P channel CMOS devices are to be created.
`First a P type, lightly doped source and drain region 26, is
`formed via ion implantation of boron, at an energy between
`about 0.5 to 1.0 Ke V, at a dose between about 1E13 to 3E13
`30 atoms/cm2
`, and at an implant angle between about 30° to
`45°, allowing the P type, lightly doped source and drain
`region 26, to be located in semiconductor substrate 1, below
`silicon nitride spacers 20b. Next a P type, heavily doped
`source and drain region 27, is formed via ion implantation
`35 of boron, at an energy between about 0.5 to 1.0 Ke V, at a
`dose between about 1E15 to 5E15 atoms/cm2
`, at an implant
`angle between about 0° to 7°. Regions of exposed silicon
`oxide gate insulator layer 7, not covered by the polycide gate
`structure, is removed using a wet etch procedure. The result
`40 of these process steps is schematically shown in FIG. 12.
`After removal of photoresist shape 25, using plasma
`oxygen ashing and careful wet cleans, titanium disilicide
`layer 28, is formed on source and drain regions, exposed in
`logic region 50. First a titanium layer is deposited, using an
`45 R.F. sputtering procedure, to a thickness between about 300
`to 600 Angstroms. A rapid thermal anneal, (RTA),
`procedure, is next employed, at a temperature between about
`600° to 700° C., for a time between about 60 to 90 sec, in
`an N2 ambient, to convert titanium to titanium silicide layer
`50 28, in regions in which titanium interfaced silicon, or
`exposed P type, and N type, source and drain regions. In
`regions in which titanium interfaced silicon nitride spacers
`20b, silicon nitride layer 20a, or silicon oxide filled shallow
`trench 13b, titanium remains unreacted, and is selectively
`55 removed using a 5:1:1 solution of H 20-NH40H-H20 2 .
`This is shown schematically in FIG. 13. This procedure,
`creating titanium silicide only in source and drain regions,
`while using previously deposited titanium disilicide layer
`17, for the polycide gate structure, avoids a possible bridg-
`60 ing mechanism that can occur when the metal silicide is
`formed for both the gate and the source and drain regions,
`during the same procedure.
`FIG. 14, schematically shows the formation of silicon
`oxide layer 29, in spaces between polycide gate structures,
`65 in logic region 50. First silicon oxide layer 29, is deposited
`using PECVD or LPCVD procedures, to a thickness
`between about 5000 to 8000 Angstroms. A CMP procedure
`
`Micron Ex. 1023, p. 24
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`5,858,831
`
`7
`is used to planarize silicon oxide layer 29, creating a smooth
`top surface topography. Photoresist shape 30, is next used as
`a block out mask, allowing silicon oxide layer 29, to be
`selectively removed from DRAM region 6