(12) United States Patent
`Leung et al.
`
`I 1111111111111111 11111 111111111111111 IIIII IIIII 1111111111111111 IIII IIII IIII
`
`US006642098B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,642,098 B2
`Nov. 4, 2003
`
`(54) DRAM CELL HAVING A CAPACITOR
`STRUCTURE FABRICATED PARTIALLY IN A
`CAVITY AND METHOD FOR OPERATING
`SAME
`
`(75)
`
`Inventors: Wingyu Leung, Cupertinno, CA (US);
`Fu-Chieh Hsu, Saratoga, CA (US)
`
`(73) Assignee: Monolithic System Technology, Inc.,
`Sunnyvale, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`DE
`EP
`EP
`EP
`JP
`JP
`JP
`
`5,789,291 A
`5,963,838 A
`5,986,947 A
`6,009,023 A
`6,104,055 A
`6,352,890 Bl
`
`8/1998 Sung
`10/1999 Yamamoto et al.
`11/1999 Choi et al.
`12/1999 Lu et al.
`8/2000 Watanabe
`3/2002 Sutcliffe
`
`FOREIGN PATENT DOCUMENTS
`
`4034169 Al
`0460694 A2
`0493659 A2
`0632462 A2
`03259566
`07094596
`08063964
`
`5/1991
`12/1991
`7/1992
`1/1995
`11/1991
`4/1995
`3/1996
`
`OTHER PUBLICATIONS
`
`(21) Appl. No.: 10/374,917
`
`(22) Filed:
`
`Feb.25,2003
`
`(65)
`
`Prior Publication Data
`
`US 2003/0151071 Al Aug. 14, 2003
`
`Related U.S. Application Data
`
`( 60) Division of application No. 10/033,690, filed on Nov. 2,
`2001, now Pat. No. 6,573,548, which is a continuation-in(cid:173)
`part of application No. 09/772,434, filed on Jan. 29, 2001,
`now Pat. No. 6,468,855, which is a continuation-in-part of
`application No. 09/427,383, filed on Oct. 25, 1999, now Pat.
`No. 6,509,595, which is a continuation-in-part of application
`No. 09/332,757, filed on Jun. 14, 1999, now Pat. No.
`6,147,914, which is a continuation-in-part of application No.
`09/134,488, filed on Aug. 14, 1998, now Pat. No. 6,075,720.
`
`Int. Cl.7 ............................................ HOlL 21/8242
`(51)
`(52) U.S. Cl. ....................................................... 438/241
`(58) Field of Search .................................. 438/241, 239
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,198,995 A
`5,267,201 A
`5,297,104 A
`5,371,705 A
`5,377,139 A
`5,394,365 A
`5,416,034 A
`5,600,598 A
`5,694,355 A
`5,703,827 A
`
`3/1993 Dennard et al.
`11/1993 Foss et al.
`3/1994 Nakashima
`12/1994 Nakayama et al.
`12/1994 Lage et al.
`2/1995 Tsukikawa
`5/1995 Bryant
`2/1997 Skjaveland et al.
`12/1997 Skjaveland et al.
`12/1997 Leung et al.
`
`A 768k Embedded DRAM for 1.244Gb/s ATM Switch in a
`0.8 µm Logic Process; 1996 IEEE Int'l. Solid-State Circuits
`Conference (2 pgs.).
`An Embedded DRAM Module using a Dual Sense Amplifier
`Architecture in a Logic Process; 1997 IEEE Int'l. Solid(cid:173)
`State Circuits Conference (3 pgs.).
`Chapter 4-Transistor Current Sources and Active Loads;
`Analysis And Design Of Analog Integrated Circuits; pp.
`330-333 by P.R. Gray et al.
`
`Primary Examiner-David Nelms
`Assistant Examiner---Quoc Hoang
`(74) Attorney, Agent, or Firm-Bever, Hoffmann & Harms,
`LLP; E. Eric Hoffman
`
`(57)
`
`ABSTRACT
`
`A memory system that includes a dynamic random access
`memory (DRAM) cell including an access transistor and a
`capacitor structure fabricated in a semiconductor substrate.
`The capacitor structure is fabricated by forming a cavity in
`a shallow trench isolation region, thereby exposing a side(cid:173)
`wall region of the substrate below the upper surface of the
`substrate. A dielectric layer is formed over the upper surface
`and the sidewall region of the substrate. A polysilicon layer
`is formed over the dielectric layer and patterned to form a
`capacitor electrode of the capacitor structure that extends
`over the upper surface and the sidewall region of the
`substrate. The capacitor electrode is partially recessed below
`the upper surface of the substrate. The polysilicon layer is
`also patterned to form the gate electrode of the access
`transistor.
`
`11 Claims, 32 Drawing Sheets
`
`3051
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`
`Micron Ex. 1022, p. 1
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 1 of 32
`
`US 6,642,098 B2
`
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`(PRIOR ART)
`
`Micron Ex. 1022, p. 2
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 2 of 32
`
`US 6,642,098 B2
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`Micron Ex. 1022, p. 3
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 3 of 32
`
`US 6,642,098 B2
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`Micron Ex. 1022, p. 4
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 4 of 32
`
`US 6,642,098 B2
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`
`Micron Ex. 1022, p. 5
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 5 of 32
`
`US 6,642,098 B2
`
`p
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`
`Micron Ex. 1022, p. 6
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 6 of 32
`
`US 6,642,098 B2
`
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`Micron Ex. 1022, p. 7
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 7 of 32
`
`US 6,642,098 B2
`
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`Micron Ex. 1022, p. 8
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 8 of 32
`
`US 6,642,098 B2
`
`3000 ~
`
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`
`Micron Ex. 1022, p. 9
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 9 of 32
`
`US 6,642,098 B2
`
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`
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`Micron Ex. 1022, p. 10
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 10 of 32
`
`US 6,642,098 B2
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`Micron Ex. 1022, p. 11
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 11 of 32
`
`US 6,642,098 B2
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`Micron Ex. 1022, p. 12
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 12 of 32
`
`US 6,642,098 B2
`
`49
`
`48
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`
`Micron Ex. 1022, p. 13
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 13 of 32
`
`US 6,642,098 B2
`
`48
`
`P-
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`Micron Ex. 1022, p. 14
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 14 of 32
`
`US 6,642,098 B2
`
`54
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`Micron Ex. 1022, p. 15
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 15 of 32
`
`US 6,642,098 B2
`
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`Micron Ex. 1022, p. 16
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`U.S. Patent
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`Nov. 4, 2003
`
`Sheet 16 of 32
`
`US 6,642,098 B2
`
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`Micron Ex. 1022, p. 17
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`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 17 of 32
`
`US 6,642,098 B2
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`401
`
`N-
`
`P-
`
`\406L
`
`42
`
`41
`
`FIG.4N
`
`408
`
`FIG.40
`
`408A
`
`P-
`
`407
`
`FIG. 4P
`
`FOX
`45
`
`FOX
`45
`
`Micron Ex. 1022, p. 18
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 18 of 32
`
`US 6,642,098 B2
`
`+ + + + + + + + + + + + + + + + + + + + + + + + + + +
`411
`
`400 ~
`
`P-
`
`408A
`
`P-
`
`413
`
`P-
`
`414
`
`N-
`
`P-
`
`FIG.4O
`
`FOX
`45
`
`400
`
`P+
`
`+ i'f + + i + + + + + + + + + + + + + + + + + i +ii
`
`415
`
`P+
`
`417
`
`P-
`
`400 ~
`
`415
`
`P+
`
`417
`
`41
`
`FIG.4R
`
`420
`
`409A
`
`406A
`
`FOX
`45
`
`409A
`
`406A
`
`FOX
`45
`
`P-
`
`41
`
`FIG. 4S
`
`Micron Ex. 1022, p. 19
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 19 of 32
`
`US 6,642,098 B2
`
`421
`
`P-
`
`41
`
`FIG. 4T
`
`421
`
`400 ~
`
`415
`
`P+
`
`417
`
`400 ~
`
`415
`
`422
`
`P+
`
`417
`
`P-
`
`41
`
`FIG. 4U
`
`400 ~ 423
`
`P-
`
`FIG. 4V
`
`FOX
`45
`
`FOX
`45
`
`Micron Ex. 1022, p. 20
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 20 of 32
`
`US 6,642,098 B2
`
`' - - - - J
`
`~--,
`I
`I
`I
`I
`
`~ J._ __ ~_-___ J _
`i I
`
`,. - - - - - - I
`
`I
`I
`~ - - J
`
`.--- -,
`I
`
`_,
`
`~I i I
`
`00
`
`' - - - - . J
`
`'-----~ -_-, II'-----L -_-J
`
`Micron Ex. 1022, p. 21
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 21 of 32
`
`US 6,642,098 B2
`
`~ - - . J
`
`~ - - . J
`
`,----------- -
`- - -,
`
`~--,
`
`co
`
`___ .J
`
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`
`>< v
`
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`u...
`
`I
`I
`I
`I
`I
`
`I 1--
`
`_ _ _ J
`
`._ -
`
`-
`
`J
`
`Micron Ex. 1022, p. 22
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 22 of 32
`
`US 6,642,098 B2
`
`""
`
`401
`
`N-
`
`P-
`
`P-
`
`431
`
`N-
`
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`
`~
`,, ,
`'-
`
`/408
`
`t
`
`P-
`
`407
`
`430
`
`~
`
`"406A
`
`FOX
`45
`
`41
`
`FIG.4Y
`
`FIG. 4Z
`
`FIG. 4AA
`
`Micron Ex. 1022, p. 23
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 23 of 32
`
`US 6,642,098 B2
`
`500 ~
`
`VCCB
`
`ROWADDR
`DECODER
`fil.Q.
`
`502
`
`501
`
`303
`
`WL
`
`505
`
`504
`
`503
`
`VSSB
`
`FIG. 5
`
`Micron Ex. 1022, p. 24
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 24 of 32
`
`US 6,642,098 B2
`
`WL
`X
`32
`
`WL
`X
`32
`
`WL
`X
`32
`
`VCCB
`
`~
`
`VCCB
`VOLTAGE
`GENERATOR
`800
`
`WORD LINE DRIVER
`500
`
`WORD LINE DRIVER
`500
`• •
`•
`WORD LINE DRIVER
`500
`
`WL
`
`WL
`
`• • •
`
`WL
`
`WL
`
`WL
`
`•
`• •
`WL
`
`•
`•
`•
`
`WL
`
`WL
`
`•
`• •
`WL
`
`WORD LINE DRIVER
`500
`
`WORD LINE DRIVER
`500
`•
`•
`•
`WORD LINE DRIVER
`500
`
`•
`• •
`
`WORD LINE DRIVER
`500
`
`WORD LINE DRIVER
`500
`•
`•
`•
`WORD LINE DRIVER
`500
`
`
`
`-- ~
`
`-- - -- - •
`
`
`• •
`
`-
`
`VBBS
`VOLTAGE
`GENERATOR
`900
`
`VBBS
`
`VSSB
`COUPLING VSSB
`CIRCUIT
`700
`
`600 __.
`
`~
`
`VSSB
`COUPLING VSSB
`CIRCUIT
`700
`
`•
`• •
`
`-
`
`VSSB
`COUPLING VSSB
`CIRCUIT
`700
`
`FIG. 6
`
`Micron Ex. 1022, p. 25
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`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 25 of 32
`
`US 6,642,098 B2
`
`700
`
`VSSB
`
`711
`
`712
`
`713
`
`714
`
`704
`
`ROWADDR Xi#
`DECODER 1 - - - - 1
`510
`
`N1
`
`701
`
`N2
`
`703
`
`702
`
`VBBS
`
`FIG. 7
`
`Micron Ex. 1022, p. 26
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 26 of 32
`
`US 6,642,098 B2
`
`Xi#
`
`N1
`
`N2
`
`VSSB
`
`Vdd
`
`ov
`
`ov
`
`VCCB
`
`WL303
`
`ov
`
`-Vdd
`
`VBBS
`
`v~
`
`VBBS
`
`FIG. 8
`
`I
`
`Micron Ex. 1022, p. 27
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 27 of 32
`
`US 6,642,098 B2
`
`800,900
`\
`
`CLK
`
`-
`...
`INT#
`EXT/
`-
`
`RING
`OSCILLATOR
`801
`
`·~
`
`- CHARGE PUMP
`.
`802
`
`Vboost
`
`-
`
`INHIBIT
`
`CHARGE PUMP
`CONTROL
`803
`
`~
`
`-
`
`VREF
`
`--
`
`FIG. 9A
`(PRIOR ART)
`
`Vboost+
`
`901
`✓
`
`Vdd
`
`)02
`
`922
`
`IREF
`
`INHIBIT#
`
`V d d~
`
`911
`
`912
`
`INHIBIT
`
`921
`---1
`
`vss
`
`FIG. 98
`(PRIOR ART)
`
`Vboost-
`
`FIG. 9C
`(PRIOR ART)
`
`Micron Ex. 1022, p. 28
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 28 of 32
`
`US 6,642,098 B2
`
`1000 \
`
`VCCB
`
`(FROM CHARGE PUMP)
`
`1001
`
`VREFP
`
`1002
`
`1004
`
`1005
`
`INHIBIT
`
`(TO RING OSC.)
`
`FIG. 10
`
`1104
`
`1105
`
`VREFN
`
`1101
`
`V
`(FROM CHARGE PUMP) __ ss_s_~
`
`FIG. 11
`
`INHIBIT#
`(TO RING OSC.)
`
`Micron Ex. 1022, p. 29
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`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 29 of 32
`
`US 6,642,098 B2
`
`~----------------- ------,
`1004~
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`1201
`
`1203
`
`1202
`
`1204
`
`1206
`
`I
`I
`I
`I
`I
`I
`
`:
`
`I
`I
`I
`I
`I
`______ I
`
`FIG. 12
`
`~--------------------- --,
`1104~
`I
`
`V
`
`1203
`
`1201
`
`1202
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`_________________________ I
`
`1204
`
`FIG. 13
`
`Micron Ex. 1022, p. 30
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 30 of 32
`
`US 6,642,098 B2
`
`--------------------------
`1
`1005 ~
`
`1401
`
`1411
`
`: 1421
`
`1403
`
`1414
`
`L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
`
`FIG. 14
`
`1 ------------------
`1105~
`
`1501
`
`1401
`
`1411
`
`I
`I
`: 1421
`I
`I
`I
`I
`I
`Vss
`:
`L ____________________________ _
`I
`
`FIG. 15
`
`Micron Ex. 1022, p. 31
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 31 of 32
`
`US 6,642,098 B2
`
`1600~
`
`1201
`
`1203
`
`---,
`
`I
`I
`I
`I
`I
`I
`I
`
`1204
`
`1206
`
`I
`I
`I
`I
`I
`
`~-----------------
`
`FIG. 16
`
`- - - j
`
`IREFP1
`
`Vdd
`
`r-------------------------------
`1700~
`
`1501
`
`1403
`
`I
`I
`I 1401
`I
`I
`I
`I
`I
`I
`: 1411
`I
`I
`I
`I
`I
`I 1421
`I
`I
`I
`I
`I
`I
`I
`I
`L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
`
`FIG. 17
`
`Micron Ex. 1022, p. 32
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`
`

`

`U.S. Patent
`
`Nov. 4, 2003
`
`Sheet 32 of 32
`
`US 6,642,098 B2
`
`1800
`
`I - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
`~B - - - - - - -~
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`1803
`
`1802
`
`N2
`
`1801
`
`N1
`
`1811
`
`1812
`
`1813
`
`1814
`
`L
`
`ROWADDR
`DECODER
`1610
`
`1601
`
`VBBC_I
`
`----,
`
`501
`
`303
`
`WL
`
`Vdd
`L ___________ __ __ _ __ ___ _
`
`vss I
`I
`
`1602
`
`503
`
`VBBS _
`
`___,
`
`FIG. 18
`
`Micron Ex. 1022, p. 33
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`
`

`

`US 6,642,098 B2
`
`1
`DRAM CELL HAVING A CAPACITOR
`STRUCTURE FABRICATED PARTIALLY IN A
`CAVITY AND METHOD FOR OPERATING
`SAME
`
`RELATED APPLICATIONS
`
`The present application is a divisional of commonly
`owned U.S. patent application Ser. No. 10/033,690, "DRAM
`CELL HAVING A CAPACITOR STRUCTURE FABRI(cid:173)
`CATED PARTIALLY IN A CAVITY AND METHOD FOR
`OPERATING SAME", by Winyu Leung and Fu-Chieh Hsu,
`filed Nov. 2, 2001, which is a continuation-in-part of com(cid:173)
`monly owned U.S. Pat. No. 6,468,855, "REDUCED
`TOPOGRAPHY DRAM CELL FABRICATED USING A
`MODIFIED LOGIC PROCESS AND METHOD FOR
`OPERATING SAME", by Wingyu Leung and Fu-Chieh
`Hsu, which is a continuation in part of commonly owned
`U.S. Pat. No. 6,509,595, "DRAM CELL FABRICATED
`USING A MODIFIED LOGIC PROCESS AND METHOD
`FOR OPERATING SAME" by Wingyu Leung and
`Fu-Chieh Hsu, which is a continuation in part of commonly
`owned U.S. Pat. No. 6,147,914, "ON-CHIP WORD LINE
`VOLTAGE GENERATION FOR DRAM EMBEDDED IN
`LOGIC PROCESS" by Wingyu Leung and Fu-Chieh Hsu,
`which is a continuation-in-part of commonly owned U.S.
`Pat. No. 6,075,720, "MEMORY CELL FOR DRAM
`EMBEDDED IN LOGIC" by Wingyu Leung and Fu-Chieh
`Hsu.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to Dynamic Random Acces(cid:173)
`sible Memory (DRAM). Moreover, the present invention
`relates to DRAM fabricated by slightly modifying a con(cid:173)
`ventional logic process. This invention further relates to the
`on-chip generation of precision voltages for the operation of
`DRAM embedded or fabricated using a conventional logic
`process.
`2. Related Art
`FIG. lAis a schematic diagram of a conventional DRAM
`cell 100 that is fabricated using a conventional logic process.
`FIG. lB is a cross sectional view of DRAM cell 100. As used
`herein, a conventional logic process is defined as a semi(cid:173)
`conductor fabrication process that uses only one layer of
`polysilicon and provides for either a single-well or twin-well
`structure. DRAM cell 100 consists of a p-channel MOS
`access transistor 1 having a gate terminal 9 connected to
`word line 3, a drain terminal 17 connected to bit line 5, and
`a source terminal 18 connected to the gate 11 of a p-channel
`MOS transistor 2. The connection between source terminal
`18 and the gate 11 undesirably increases the layout area of
`DRAM cell 100. P-channel transistor 2 is configured to
`operate as a charge storage capacitor. The source and drain
`19 of transistor 2 are commonly connected. The source, 55
`drain and channel of transistor 2 are connected to receive a
`fixed plate bias voltage VPP- The VPP voltage is a positive
`boosted voltage that is higher than the positive supply
`voltage V aa by more than a transistor threshold voltage V,.
`As used herein, the electrode of the charge storage capaci- 60
`tor is defined as the node coupled to the access transistor,
`and the counter-electrode of the charge storage capacitor is
`defined as the node coupled to receive a fixed plate bias
`voltage. Thus, in DRAM cell 100, the gate 11 of transistor
`2 forms the electrode of the charge storage capacitor, and the 65
`channel region of transistor 2 forms the counter-electrode of
`the charge storage capacitor.
`
`10
`
`2
`To improve soft-error-rate sensitivity of DRAM cell 100,
`the cell is fabricated in an n-well region 14, which is located
`in a p-type substrate 8. To minimize the sub-threshold
`leakage of access transistor 1, n-well 14 is biased at the VPR
`5 voltage (at n-type contact region 21). However, such a well
`bias increases the junction leakage. As a result, the bias
`voltage of n-well 14 is selected such that the sub-threshold
`leakage is reduced without significantly increasing the junc(cid:173)
`tion leakage. When storing charge in the storage capacitor,
`bit line 5 is brought to the appropriate level (i.e., V dd or V ss)
`and word line 3 is activated to turn on access transistor 1. As
`a result, the electrode of the storage capacitor is charged. To
`maximize the stored charge, word line 3 is required to be
`driven to a negative boosted voltage V bb that is lower than
`the supply voltage V ss minus the absolute value of the
`15 threshold voltage (V,p) of access transistor 1.
`In the data retention state, access transistor 1 is turned off
`by driving word line 3 to the V aa supply voltage. To
`maximize the charge storage of the capacitor, the counter
`electrode is biased at the positive boosted voltage Vpp· The
`20 plate voltage VPP is limited by the oxide breakdown voltage
`of the transistor 2 forming the charge storage capacitor.
`DRAM cell 100 and its variations are documented in U.S.
`Pat. No. 5,600,598, entitled "Memory Cell and Wordline
`Driver For Embedded DRAM in ASIC Process," by K.
`25 Skj ave land, R. Township, P. Gillingham (hereinafter
`referred to as "Skjaveland et al."), and "A 768 k Embedded
`DRAM for 1.244 Gb.s ATM Switch in a 0.8 um Logic
`Process," P. Gillingham, B. Hold, I. Mes, C. O'Connell, P.
`Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H.
`30 Chow, Digest of ISSCC, 1996, pp. 262-263 (hereinafter
`referred to as "Gillingham et al.). Both Skjaveland et al. and
`Gillingham et al. describe memory cells that are contained
`in an n-well formed in a p-type substrate.
`FIG. 2 is a schematic diagram of a word line control
`35 circuit 200 including a word line driver circuit 201 and a
`word line boost generator 202 described by Gillingham et al.
`Word line control circuit 200 includes p-channel transistors
`211-217, inverters 221-229, NAND gates 231-232 and
`NOR gate 241, which are connected as illustrated. Word line
`40 driver 201 includes p-channel pull up transistor 211, which
`enables an associated word line to be pulled up to the V aa
`supply voltage. P-channel pull down transistors 212-217 are
`provided so that the word line can be boosted down to a
`negative voltage (i.e., -1.SV) substantially below the nega-
`45 tive supply voltage V ss· However, the p-channel pull down
`transistors 212-217 have a drive capability much smaller
`(approximately halt) than an NMOS transistor of similar
`size. As a result, the word line turn on of Gillingham et al.
`is relatively slow(> 10 ns). Furthermore, in the data retention
`50 state, word line driver 201 only drives the word line to the
`V aa supply voltage. As a result, the sub-threshold leakage of
`the access transistor in the memory cells may not be
`adequately suppressed.
`DRAM cells similar to DRAM cell 100 have also been
`formed using n-channel transistors fabricated in a p-type
`well region. To maximize stored charge in such n-channel
`DRAM cells during memory cell access, the associated
`word line is driven to a voltage higher than the supply
`voltage V aa plus the absolute value of the threshold-voltage
`(V,n) of the access transistor. In the data retention state, the
`n-channel access transistor is turned off by driving the word
`line to V 55 supply voltage (0 Volts). To maximize the charge
`storage of the capacitor in an n-channel DRAM cell, the
`counter electrode is biased at a plate voltage V bb that is
`lower than the V 55 supply voltage.
`A prior art scheme using n-channel DRAM cells includes
`the one described by Hashimoto et al. in "An Embedded
`
`Micron Ex. 1022, p. 34
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`

`3
`DRAM Module using a Dual Sense Amplifier Architecture
`in a Logic Process", 1997 IEEE International Solid-State
`Circuits Conference, pp. 64-65 and 431. A p-type substrate
`is used, such that the memory cells are directly in contact
`with the substrate and are not isolated by any well structure. 5
`In the described design, substrate bias is not permitted.
`Moreover, application of a negative voltage to the word line
`is not applicable to ASI Cs that restrict substrate biasing to be
`zero. Consequently, the architecture achieves a negative
`gate-to-source voltage (Vgs) by limiting bit line swing. The 10
`negative V gs voltage reduces sub-threshold leakage in the
`memory cells. Hashimoto et al. fails to describe the structure
`of the word line driver.
`It would therefore be desirable to have a word line driver
`circuit that improves the leakage currents in DRAM cells
`fabricated using a conventional logic process. Moreover, it
`would be desirable to have improved methods for biasing
`DRAM cells fabricated using a conventional logic process.
`
`SUMMARY
`
`Accordingly, the present invention provides a memory
`system that includes a dynamic random access memory
`(DRAM) cell, a word line, and a CMOS word line driver
`fabricated using a conventional logic process. In a particular
`variation of this embodiment, the DRAM cell includes an
`access transistor having a thin gate oxide and a capacitor
`structure having a thick gate oxide of the type typcially used
`in high voltage 1/0 devices.
`In other embodiments of the present invention, a DRAM
`cell is fabricated by slightly modifying a conventional logic
`process. In one such embodiment, the DRAM cell is fabri(cid:173)
`cated by fabricating a crown electrode and a plate electrode
`of the DRAM cell substantially in a recessed area below the
`surface of a silicon wafer. The crown and plate electrodes are
`fabricated prior to the formation of the gate electrode of the
`access transistor. The recessed area can be formed by
`etching into a buried field oxide layer. The recessed area in
`the field oxide is located adjacent to an exposed portion of
`the silicon wafer. The crown electrode is formed over the
`recessed area of the field oxide and the exposed portion of
`the silicon wafer. Out-diffusion from the crown electrode
`causes a doped contact region to be formed in the previously
`exposed portion of the silicon wafer. The crown electrode
`includes a base region located at the bottom of the recessed
`area, and sidewalls that extend up walls of the recessed area.
`A dielectric layer is located over the crown electrode. The
`plate electrode is located over the dielectric layer, thereby
`completing the capacitor of the DRAM cell. The plate
`electrode extends over the base region and the sidewalls of
`the crown electrode.
`After the capacitor has been formed, a gate dielectric layer
`for the access transistor is thermally grown. The access
`transistor is then formed over the gate dielectric using
`conventional logic process steps. The access transistor is
`positioned such that the source of the access transistor is
`continuous with the doped contact region, thereby coupling
`the access transistor to the capacitor. The configuration of
`the storage electrode and the plate electrode advantageously
`results in a DRAM cell having a high capacitance, a small 60
`layout area and a reduced surface topography. This configu(cid:173)
`ration further requires only minimal modifications to a
`conventional logic process. More specifically, two addi(cid:173)
`tional masking steps and two additional polysilicon layers
`are used to form the capacitor. The temperature cycles 65
`associated with the capacitor formation do not subsequently
`affect the formation of N+ and P+ shallow junctions or the
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`4
`formation of salicide during fabrication of the access tran(cid:173)
`sistor. In addition, the internal node of the capacitor is
`substantially free of salicide for reduced leakage current.
`In a variation of this embodiment, the crown electrode and
`the gate electrode are both formed from the same polysilicon
`layer.
`In yet another embodiment of the present invention, the
`DRAM cell includes a capacitor structure that extends into
`a cavity formed in a field dielectric layer, thereby giving the
`capacitor structure a relatively large surface area and a
`relatively small layout area. In one embodiment, adding only
`one masking step to a conventional logic process, the
`capacitor structure is fabricated as follows. A field dielectric
`layer (e.g., field oxide) is formed in a semiconductor sub-
`15 strate having a first conductivity type. The field dielectric
`layer extends below an upper surface of the semiconductor
`substrate. A cavity is formed in the field dielectric layer by
`etching the field dielectric layer through an opening in a
`mask. The cavity extends below the upper surface of the
`20 substrate. A threshold adjustment implant can then be
`optionally performed through the opening of the same mask,
`thereby forming a threshold adjustment region in the sub(cid:173)
`strate. The threshold adjustment region extends along the
`upper surface of the substrate, and along the exposed surface
`25 of the cavity.
`The mask is removed and a gate dielectric layer is formed
`over the resulting structure. The standard polysilicon gate
`layer is then formed over the gate dielectric layer, wherein
`a portion of the polysilicon layer fills the inside of the cavity.
`30 The polysilicon layer is then patterned to form a capacitor
`electrode of the capacitor structure, and a gate electrode of
`the access transistor. The capacitor electrode has a section
`that extends over the upper surface of the substrate, and a
`section that extends into the cavity. In one embodiment, the
`35 gate dielectric layer can have different compositions under
`the gate electrode and under the capacitor electrode.
`The word line driver is controlled to selectively provide a
`positive boosted voltage and a negative boosted voltage to
`the word line, thereby controlling access to the DRAM cell.
`A positive boosted voltage generator is provided to gen(cid:173)
`erate the positive boosted voltage, such that the positive
`boosted voltage is greater than the V aa supply voltage but
`less than the V aa supply voltage plus one diode voltage drop
`45 (V) of about 0.6 Volts.
`Similarly, a negative boosted voltage generator is pro(cid:173)
`vided to generate the negative boosted voltage, such that the
`negative boosted voltage is less than the V ss supply voltage,
`but greater than the V ss supply voltage minus one diode
`50 voltage drop (V) of about 0.6 Volts.
`A coupling circuit is provided between the word line
`driver and one of the positive or negative boosted voltage
`generators. For example, if the DRAM cell is constructed
`from PMOS transistors, then the coupling circuit couples the
`55 word line driver to the negative boosted word line generator.
`When the DRAM cell is being accessed, the coupling circuit
`couples the word line driver to the negative boosted voltage,
`thereby turning on the p-channel access transistor of the
`DRAM cell.
`Conversely, if the DRAM cell is constructed from NMOS
`transistors, then the coupling circuit couples the word line
`driver to the positive boosted word line generator. When the
`DRAM cell is being accessed, the coupling circuit couples
`the word line driver to the positive boosted voltage, thereby
`turning on then-channel access transistor of the DRAM cell.
`The positive boosted voltage generator includes a charge
`pump control circuit that limits the-positive boosted voltage
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`40
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`Micron Ex. 1022, p. 35
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
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`US 6,642,098 B2
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`10
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`5
`to a voltage less than V aa plus one diode voltage drop, Vj.
`Similarly, the negative boosted voltage generator includes a
`charge pump control circuit that limits the negative boosted
`voltage to a voltage greater than V ss minus one diode
`voltage drop, Vj. In a particular embodiment, the positive 5
`boosted voltage and the negative boosted voltage are refer(cid:173)
`enced to transistor threshold voltages.
`In deep sub-micron logic processes having transistors
`with gate lengths equal to or less than 0.15 microns, the
`threshold voltage of the thin oxide transistors is less than 0.5
`Volts. This threshold voltage is less than the P-N junction
`voltage of about 0.6 Volts. During a restore or write
`operation, the negative boosted voltage is applied to the gate
`of the access transistor (i.e., the cell word line) through an
`n-channel driver transistor, which is formed in a p-type 15
`substrate. The negative boosted voltage helps to charge the
`storage capacitor to a voltage substantially close to the V ss
`supply voltage during the restore or writ