United States Patent [19J
`Wu et al.
`
`I 1111111111111111 11111 111111111111111 1111111111 11111 lllll 111111111111111111
`US005998251A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,998,251
`Dec. 7, 1999
`
`[54] PROCESS AND STRUCTURE FOR
`EMBEDDED DRAM
`
`Primary Examiner-Joni Chang
`Attorney, Agent, or Firm-Rabin & Champagne, P.C.
`
`[75]
`
`Inventors: H.J. Wu, Hsinchu; Shih-Wei Sun,
`Taipei; Jacob Chen, Hsinchu;
`Tri-Rung Yew, Hsinchu Hsien, all of
`Taiwan
`
`[73] Assignee: United Microelectronics Corp.,
`Hsinchu, Taiwan
`
`[21] Appl. No.: 08/975,492
`
`[22] Filed:
`
`Nov. 21, 1997
`
`[30]
`
`Foreign Application Priority Data
`
`Jul. 19, 1997 [TW]
`
`Taiwan ................................. 86110245
`
`Int. Cl.6
`................................................. HOlL 21/8242
`[51]
`[52] U.S. Cl. ............................................. 438/241; 438/253
`[58] Field of Search ............................ 438/238, 239-241,
`438/253, 254, 396, 397
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,399,890
`5,644,151
`5,719,079
`5,879,981
`5,920,775
`
`........................... 257/306
`3/1995 Okada et al.
`... ... ... ... ... .... ... ... ... 257 /306
`7 /1997 Izumi et al.
`2/1998 Yoo et al.
`............................... 438/238
`3/1999 Tanigawa ................................ 438/241
`7/1999 Koh ......................................... 438/241
`
`FOREIGN PATENT DOCUMENTS
`
`0 337 436
`03136361
`03205866
`96/26544
`
`10/1989
`6/1991
`9/1991
`8/1996
`
`European Pat. Off ..
`Japan.
`Japan.
`WIPO.
`
`[57]
`
`ABSTRACT
`
`An integrated circuit device having both an array of logic
`circuits and an array of embedded DRAM circuits is pro(cid:173)
`vided using a process that avoids some of the most signifi(cid:173)
`cant processing challenges for embedded DRAM integra(cid:173)
`tion. Transfer FETs and wiring lines are provided for the
`embedded DRAM circuits and FETs are provided for the
`logic portions of the device in an initial phase of the process.
`The gate electrodes and source/drain regions of the logic
`FETs are subjected to a salicide process at this initial phase
`and a thick planarized oxide layer is provided over both the
`embedded DRAM regions and the logic circuit regions.
`Capacitors and logic interconnects are next formed using
`common etching, titanium nitride deposition and tungsten
`deposition steps. Contact vias are formed to expose each of
`the source drain regions of the DRAM transfer FETs and to
`expose select conductors within the logic circuits. A titanium
`nitride layer is deposited over the device and within the
`various contact vias through the planarized oxide layer. A
`capacitor dielectric layer is provided over the device and
`then the capacitor dielectric layer is selectively removed
`from at least the contact vias that become bit line contacts
`and logic interconnects. A layer of tungsten is deposited and
`patterned to provide upper capacitor electrodes and to com(cid:173)
`plete the bit line contacts and logic interconnects. This first
`level tungsten layer also can provide bit line wiring. The ½
`V cc potential for the upper capacitor electrodes can be
`provided to the circuit using a level of interconnect wiring
`also used by the logic circuits.
`
`44 Claims, 8 Drawing Sheets
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`180
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`170
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`182
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`170
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`162
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`100
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`100
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`Micron Ex. 1021, p. 1
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 1 of 8
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`5,998,251
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`24
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`26
`22
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`10
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`16
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`26 18 14
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`20
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`32
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`30
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`34 38
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`12
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`28
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`40
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`10
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`FIG. 1 -- Prior Art
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`52
`50
`48
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`16
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`12
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`10
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`FIG. 2 -- Prior Art
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`46
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`32
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`30
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`34 38
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`40
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`10
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`Micron Ex. 1021, p. 2
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 2 of 8
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`5,998,251
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`52
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`50 48
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`16
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`12
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`FIG. 3 -- Prior Art
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`52
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`50 48
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`54
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`14
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`30
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`40
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`34
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`12.
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`10
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`54
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`68
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`12
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`28
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`40
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`FIG. 4 -- Prior Art
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`12.
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`10
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`Micron Ex. 1021, p. 3
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 3 of 8
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`5,998,251
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`114
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`116
`112
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`130
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`114
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`116
`112
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`106
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`120
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`118
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`128
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`100
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`FIG. 5
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`106
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`104
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`120
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`126
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`118
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`128
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`100
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`FIG. 6
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`124
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`102
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`100
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`124
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`102
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`100
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`Micron Ex. 1021, p. 4
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 4 of 8
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`5,998,251
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`106
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`104
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`120
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`132
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`102
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`118
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`FIG. 7
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`106
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`104
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`120
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`124 134
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`118
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`128
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`100
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`FIG. 8
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`Micron Ex. 1021, p. 5
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 5 of 8
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`5,998,251
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`106
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`146
`t
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`104
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`148
`t
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`150 120
`t
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`138
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`140
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`134 142
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`144
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`100
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`FIG. 9
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`106 152 146
`t
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`104
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`148
`t
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`150 120
`t
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`136
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`138
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`140
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`134 142
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`144
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`100
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`FIG. 10
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`Micron Ex. 1021, p. 6
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 6 of 8
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`5,998,251
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`106 152 146 154 104
`'V
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`148
`'V
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`150 120
`'V
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`100
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`FIG. 11
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`100
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`106 152 146 156 104
`'V
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`148
`'V
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`150 120
`'V
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`102
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`FIG. 12
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`138
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`140
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`134 142
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`144
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`100
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`Micron Ex. 1021, p. 7
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 7 of 8
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`5,998,251
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`166
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`164
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`158 160
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`162
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`100
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`138
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`140
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`134 142
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`144
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`100
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`FIG. 13
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`172
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`174
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`~---~w~---~--~wr-----~
`
`170
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`160
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`170
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`100
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`138
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`140
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`134 142
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`144
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`100
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`FIG. 14
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`Micron Ex. 1021, p. 8
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`U.S. Patent
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`Dec. 7, 1999
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`Sheet 8 of 8
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`5,998,251
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`182
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`170
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`138
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`140
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`134 142
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`144
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`180
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`170
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`100
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`FIG. 15
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`180
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`182 184
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`160
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`162
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`138
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`140
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`134 142
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`144
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`100
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`FIG. 16
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`Micron Ex. 1021, p. 9
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`5,998,251
`
`1
`PROCESS AND STRUCTURE FOR
`EMBEDDED DRAM
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`Aspects of the present invention relate to the formation of
`integrated circuit devices that incorporate both an array of
`memory cells and an array of logic circuits on a single chip
`or substrate in a process flow sharing processing steps in
`common between the formation of the memory array and the
`logic array. Other aspects of the invention relate to an
`integrated circuit incorporating embedded memory dedi(cid:173)
`cated to logic circuits formed on the chip with the memory.
`2. Description of the Related Art
`For some data processing applications, it has become
`desirable to provide integrated circuit devices that incorpo(cid:173)
`rate on the same chip both arrays of memory cells and arrays
`of high speed logic circuits like those typically used in
`microprocessors or digital signal processors. It might, for
`example, be desirable to provide an array of dynamic
`random access memory cells within the integrated circuit
`device to provide dedicated, comparatively high speed
`access to a significant amount of data storage for the logic
`circuits of the integrated circuit device. Applications that
`could benefit from the provision of such embedded DRAM
`include logic circuits that process large amounts of data,
`such as graphics processors. Use of embedded memory
`might also reduce the number of pins or input/output ter(cid:173)
`minals required by the integrated circuit device. Providing
`both high speed logic circuits and embedded DRAM on the
`same chip requires that certain aspects of the process flow
`used for making the chip be dedicated to the formation of
`logic circuits and that other aspects be dedicated to the
`formation of memory cells. FIGS. 1-4 illustrate a portion of 35
`a process flow that might be used to provide embedded
`DRAM on an integrated circuit device that includes high
`speed logic circuits.
`FIG. 1 illustrates at an intermediate processing stage an
`integrated circuit device that will include embedded DRAM
`and an array of logic circuits. On the left side of the
`illustrated device is an exemplary DRAM cell and on the
`right side of the illustrated device is an exemplary logic FET
`that makes up part of a logic circuit. Other circuitry for
`performing input/output (1/0) functions for the integrated
`circuit device would typically be included, but is not shown
`here. The embedded DRAM cell, when complete, will
`include a transfer or pass field effect transistor (FET)
`coupled to a charge storage capacitor. The transfer FET acts
`as a switch for selectively coupling the lower electrode of 50
`the charge storage capacitor to a bit line so that charges,
`representative of data, can either be read from or stored to
`the charge storage capacitor. The embedded DRAM and
`logic circuits of the integrated circuit device are formed on
`a single silicon substrate 10, which typically has at least a 55
`surface layer of P-type material. Device isolation regions 12
`are provided as necessary across the surface of the device.
`The illustrated device isolation regions 12 may be field
`oxide regions formed in a modified local oxidation of silicon
`(LOCOS) process or may be shallow trench isolation (STI) 60
`devices consisting of trenches filled with oxide by chemical
`vapor deposition (CVD). The illustrated cross section of the
`embedded DRAM cell includes a section through a transfer
`FET 14 and through an adjacent wiring line structure 16. The
`wiring line structure 16 is typically an extension of the gate 65
`electrode structures for adjacent DRAM cells and so has an
`almost identical structure to the illustrated gate electrode
`
`2
`structure. The gate electrode structure includes a gate elec(cid:173)
`trode 20 including at least a lower layer of doped polysilicon
`provided on gate oxide layer 18. Most typically, the wiring
`line conductor 22 also includes at least a lower layer of
`5 doped polysilicon formed on the field oxide isolation region
`12. A capping oxide layer 24 is provided early in processing
`to protect the gate electrode 20 and wiring line conductor 22.
`Oxide spacer structures 26 are provided on either side of the
`gate electrode and wiring lines, typically by CVD silicon
`10 oxide deposition followed by an etch back process. Oxide
`spacer structures 26 provide lateral protection to the gate
`electrode and wiring line during processing and might also
`be used in the formation of lightly doped drain (LDD)
`structures for the source and drain regions of the transfer
`15 FETs. Source/drain regions 28 are formed by self-aligned
`ion implantation of N-type dopants on either side of the gate
`electrode 20 to complete the transfer FET 14.
`Portions of the logic circuitry, schematically illustrated on
`the right of FIGS. 1-4, are formed nearly contemporane-
`20 ously with the formation of the transfer FETs of the DRAM
`array. Depending on design choices, some processing steps
`may be shared between the embedded DRAM and logic
`formation processes or wholly distinct processes might be
`used for forming the DRAM and logic circuits. The exem-
`25 plary FET 30 of the logic circuit is formed on a gate oxide
`layer 32 and includes a polysilicon gate electrode 34. It is
`generally preferred to not provide a silicide layer over the
`polysilicon gate electrode layer 34 at the illustrated stage of
`the manufacturing process. Instead, self-aligned silicide
`30 ("salicide") process is used to complete the FE Ts of the logic
`circuit at a later stage in the manufacturing process. Oxide
`spacers 38 are formed on either side of the gate electrode 34
`and are typically used in defining an LDD structure for the
`source/drain regions 40 of the logic FETs.
`After formation of the FETs for the DRAM array and the
`logic array, it is typical to provide a thick oxide layer 42 over
`the entire substrate 10. The oxide layer is deposited to a
`sufficient thickness to both cover the various device struc(cid:173)
`tures and to provide a sufficient thickness for the planariza-
`40 tion of the oxide layer 42. Planarization of the oxide layer 42
`is important to improve the process latitude for the photo(cid:173)
`lithography and etching steps used to form the lower elec(cid:173)
`trode of the charge storage capacitor. After provision of the
`planarized oxide layer, a via 44 is formed through the
`45 planarized oxide layer to expose the source/drain region 28
`to which the charge storage capacitor of the illustrated
`DRAM cell will be connected. Doped polysilicon is pro(cid:173)
`vided within via 44 to form a vertical interconnect 46
`between the source/drain region 28 and the lower electrode
`48 of the charge storage capacitor. The lower electrode 48 of
`the charge storage capacitor is typically formed from several
`layers of doped polysilicon. For the design rules typically
`used in modem processes, it is important to provide a three
`dimensional crown or fin capacitor structure for the lower
`electrode 48 so that it has sufficient surface area to provide
`a sufficient level of charge storage for the capacitor. Such a
`crown or fin structure is necessary to ensure that the charge
`storage capacitor of the DRAM cell stores a sufficiently
`large charge to facilitate data reading and writing operations
`as well as to ensure that the stored charge remains on the
`charge storage capacitor for an acceptable amount of time
`without requiring a refresh operation. Formation of the
`charge storage capacitor continues by providing a capacitor
`dielectric 50 consisting of the three layer oxide/nitride/oxide
`structure known as ONO over the lower capacitor electrode
`48. An upper electrode 52 is formed by providing another
`layer of doped polysilicon which is patterned in a manner
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`5,998,251
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`3
`conventional to DRAM arrays. The completed charge stor(cid:173)
`age capacitor is shown in FIG. 2.
`After completion of the charge storage capacitor, a mask
`such as photoresist mask 54 is provided over the FIG. 2
`device to cover the embedded DRAM array and to expose
`the oxide layer 42 over the array of logic circuitry. Etching
`is performed to remove the thick oxide layer 42 from above
`the logic circuitry, resulting in the structure shown in FIG.
`3. Processing continues on the logic FET 30 to form a
`silicide layer 66 over the gate electrode 34 and silicide layers 10
`68 over the source/drain regions 40, as shown in FIG. 4. The
`silicide layers 66, 68 reduce the resistivity and contact
`resistance of the gate electrode and the source/drain regions.
`Typically, the silicide layers are formed in a self-aligned
`silicide ("salicide") process in which a layer of a refractory 15
`metal such as titanium is deposited over the exposed poly(cid:173)
`silicon gate electrode and the exposed silicon source/drain
`regions. An initial anneal is performed to convert a portion
`of the deposited metal layer to a metal silicide. An etch is
`performed to remove unreacted metal and then a second 20
`anneal is performed to achieve a low resistivity for the metal
`silicide layers 66, 68 on the gate electrode 34 and source/
`drain regions 40. Processing continues to provide a typically
`multi-layer interconnect structure dedicated to the logic
`circuitry (not shown). Further processing completes the 25
`integrated circuit device which includes both logic circuitry
`and embedded DRAM circuitry.
`To date, providing embedded DRAM for the logic circuits
`of an integrated circuit device to enhance the performance of
`the logic circuits and the device as a whole has been an
`expensive process which exhibits undesirably low yields for
`the desired integrated circuit device. It is accordingly desir(cid:173)
`able to provide a better process for forming embedded
`DRAM integrated circuit devices.
`
`SUMMARY OF THE PREFERRED
`EMBODIMENTS
`
`4
`iting a metal layer over the logic FETs, annealing the metal
`layer to react the metal layer with portions of the logic FETs;
`removing portions of the metal layer after the step of
`annealing the metal layer, and then forming the first insu-
`lating layer.
`A different, more detailed aspect of the invention removes
`the capacitor dielectric layer from within the second opening
`and the third opening to allow those openings to be used for
`forming bit line contacts and logic contacts, respectively.
`Further to this aspect of the invention, the second conductive
`layer is provided within the second opening and the third
`opening so that the second conductive layer is in contact
`with the first conductive layer within the second opening and
`within the third opening. From a different perspective,
`embodiments of the invention may provide the first conduc(cid:173)
`tive layer within the third opening so that the first conductive
`layer is in contact with the at least one conductor within the
`third opening.
`In a still further aspect of this most recent feature, the
`method may deposit a second insulating layer over the
`second conductive layer and may provide a fourth opening
`through the second insulating layer to expose the upper
`capacitor electrode and a fifth opening through the second
`insulating layer to expose a portion of the second conductive
`layer connected to the at least one conductor. Contacts are
`formed by depositing a third conductive layer within the
`fourth and fifth openings and over the second insulating
`layer and then patterning the third conductive layer to form
`a wiring line connecting the upper capacitor electrode to a
`30 reference potential through the fourth opening and to form
`a logic wiring line connected to the at least one conductor.
`In a different aspect of the present invention, the first
`conductive layer is patterned before the capacitor dielectric
`35 layer is provided and the edges of the lower capacitor
`electrode are covered by the capacitor electric layer. In this
`aspect, the edges of the upper capacitor electrode extend
`laterally beyond the edges of the lower capacitor electrode.
`
`Embodiments of the present invention provide a method
`of making an integrated circuit device including both 40
`embedded DRAM circuits and logic circuits on a single
`substrate. The method includes the steps of providing a
`substrate, providing transfer FETs in and on embedded
`DRAM circuit regions of the substrate and providing logic
`FETs in and on logic circuit regions of the substrate. A first 45
`insulating layer is provided over the transfer FETs and over
`the logic FETs. First and second openings are defined
`through the first insulating layer to expose the first and
`second source/drain regions, respectively, of at least one of
`the transfer FETs and a third opening is defined to expose at 50
`least one conductor within the logic circuit. A first conduc(cid:173)
`tive layer is provided over the first insulating layer, extend(cid:173)
`ing into the openings to contact the first source/drain region
`of the one transfer FET so that the first conductive layer lines
`and does not fill the first opening. A capacitor dielectric layer 55
`is provided within the first opening. A second conductive
`layer is provided within the first opening and the first
`conductive layer and the second conductive layer are pat(cid:173)
`terned to laterally define a lower and an upper capacitor
`electrode, respectively, of an embedded DRAM charge 60
`storage capacitor.
`A particular aspect of the invention forms the embedded
`DRAM charge storage capacitor without use of high tem(cid:173)
`perature processing steps.
`Some embodiments of the invention include the steps of
`selectively covering the transfer FETs with a protective
`dielectric layer while leaving the logic FETs exposed, depos-
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1-4 illustrate steps in a conventional process for
`forming an embedded DRAM integrated circuit device.
`FIGS. 5-15 illustrate steps in a preferred process for
`forming an integrated circuit device in accordance with
`preferred embodiments of the present invention.
`FIG. 16 illustrates an alternate configuration of a capaci(cid:173)
`tor particularly preferred for an embedded DRAM cell.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`There are a variety of constraints on the conventional
`process illustrated in FIGS. 1-4 for providing embedded
`DRAM and logic circuits within an integrated circuit formed
`on a single chip. The process used to uncover the FE Ts of the
`logic circuitry after formation of the DRAM capacitor, that
`is, the process which removes oxide layer 42 and converts
`the FIG. 2 structure into the FIG. 3 structure, is a particular
`source of problems. Oxide layer 42 is made thick to achieve
`the desired level of planarization and to sufficiently protect
`the various memory and logic circuits during the etching
`steps used to form the crown or fin structure of the lower
`electrode 48 of the charge storage capacitor. Because the
`oxide layer 42 tends to be thick, removal of the oxide layer
`65 42 from above the logic circuits requires a prolonged etching
`process. The polysilicon gate electrode 34 extends above the
`source/drain regions 40 of the substrate by about 2000 A
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`and, quite possibly, by as much as 4000---5000 A. Etching to
`remove the oxide layer 42 therefore must continue through
`one thickness of oxide over the gate electrode of the logic
`FET and a greater thickness of oxide over the source/drain
`regions. The etching process must be continued until the 5
`source/drain regions 40 are exposed, so that the effect of
`removing the oxide layer 42 is to expose the gate electrode
`to the etching process for undesirable period of time while
`etching continues to expose the source/drain regions 40.
`Thus, the etching process inevitably leads to loss of poly-
`silicon from the gate electrode and damage to the gate
`electrode and gate oxide from the plasma etching process.
`Polysilicon loss and gate electrode processing damage has
`been observed to reduce the performance and yields of logic
`circuits in embedded DRAM integrated circuit devices.
`One alternative to the lengthy etching process used to 15
`expose the source/drain regions of the logic FETs of the
`logic circuits shown in FIG. 3 is to complete formation of the
`logic FETs before forming the charge storage capacitors of
`the embedded DRAM array. For example, the FETs of the
`logic circuit might be completed before the thick oxide layer 20
`42 is provided over the FIG. 1 structure, thereby eliminating
`the need to perform a blanket etch to expose the gate and
`source/drain regions of the logic FETs at the same time. This
`strategy has previously proven unworkable, however.
`Completion of the logic FETs of the logic circuit requires 25
`that the silicide layers 66, 68 be provided on the gate
`electrode 34 and source/drain regions 40, respectively. The
`metals provided in these silicide layers 66, 68 typically
`diffuse rapidly through silicon during high temperature
`processing steps. Such high temperature processing steps are 30
`required in the formation of the DRAM charge storage
`capacitors because aspects of the nitride deposition process
`and the subsequent oxidation process used in forming the
`ONO capacitor dielectric require that the device be heated to
`temperatures in excess of 700° C. Such high temperature 35
`processes can create a wide array of problems for the silicide
`layers 66, 68 and may render inoperative the FETs 30 of the
`logic circuit.
`Particularly preferred embodiments of the present inven(cid:173)
`tion address these and other problems by forming the logic 40
`circuitry of embedded DRAM circuits, including salicide
`processing, before the charge storage capacitors of the
`DRAM array are completed. After the salicide process for
`the logic FETs is finished, the charge storage capacitors of
`the embedded DRAM array are formed using appropriate 45
`low temperature processing steps. By forming the charge
`storage capacitors after the transistors of the logic circuitry
`are completed, there is typically no need to etch through a
`thick oxide layer to expose the gate electrodes of the logic
`FETs for further processing. There will consequently be a 50
`reduced likelihood of damaging the gate electrodes of the
`logic FE Ts during processing. Preferred embodiments of the
`present invention address the conventional problems with
`forming charge storage capacitors after the completion of
`salicided logic FETs by limiting high temperature process- 55
`ing steps subsequent to the salicide process. The primary
`difficulty with forming DRAM charge storage capacitors
`subsequent to performing salicide processing of the logic
`FETs is the high speed at which titanium and other metals
`used in salicide processes diffuse through the silicon sub- 60
`strate at the temperatures conventionally used for capacitor
`formation. This rapid diffusion can produce the "spiking"
`phenomena which has been observed to be a major source of
`leakage from source/drain regions and can render affected
`FETs unusable. Spiking and other rapid diffusion phenom- 65
`ena can be avoided if high temperature processing steps are
`avoided after salicide processing steps.
`
`6
`In the present context, the term high temperature process(cid:173)
`ing step means a processing step performed at a temperature
`sufficiently high to allow significant levels of transport
`through the silicon substrate of the metal or other materials
`used in the salicide process to reduce the conductivity of the
`gate electrodes or the source/drain regions of the logic FE Ts.
`For example, when titanium is the metal used in the salicide
`process, a high temperature processing step is one in which
`titanium readily diffuses through silicon. Typically, that will
`mean that a processing step performed at a temperature in
`excess of approximately 700° C. will be considered to be a
`high temperature processing step when titanium is the metal
`of concern. Those of skill in the art will appreciate that the
`temperature at which metals begin rapidly diffusing is a
`familiar processing parameter in the two stage annealing
`processes conventionally used in salicide formation. In the
`first stage of such a two stage salicide process, it is necessary
`to maintain the device below a critical temperature to avoid
`bridging phenomena. In a similar manner, this discussion
`identifies a high temperature processing step as one of
`sufficient temperature and duration to cause metal diffusion
`or spiking to occur to a sufficient extent to introduce leakage
`from the charge storage node. Also like the salicide process,
`the definition of what is a high temperature processing step
`will vary for the particular metals used in the salicide
`process and the particular geometry of the logic FETs.
`High temperature processing steps are avoided in the
`formation of the charge storage capacitors by selecting
`appropriate constituent materials for the capacitor electrodes
`and dielectric layer and by selecting appropriate processing
`steps for depositing and shaping those materials. In a par(cid:173)
`ticularly preferred embodiment of the present invention, the
`charge storage capacitors of the embedded DRAM array
`have metallic electrodes deposited in low temperature pro(cid:173)
`cesses and use a high dielectric constant material, also
`provided in a low temperature process, as the capacitor
`dielectric. For example, the lower electrode of the charge
`storage capacitor might be formed from titanium nitride, the
`capacitor dielectric might be tantalum pentoxide and the
`upper capacitor electrode might be tungsten. Each of these
`materials can be deposited in a chemical vapor deposition
`(CVD) process at an appropriately low temperature so as to
`not interfere with the quality of the salicided surfaces of the
`logic FETs.
`Sufficient capacitance is provided for the DRAM charge
`storage capacitor both by using a high dielectric constant
`material as the capacitor dielectric and by providing addi(cid:173)
`tional charge storage surface area through the physical shape
`of the lower capacitor electrode. The lower capacitor elec(cid:173)
`trode is preferably formed by providing a planarized dielec(cid:173)
`tric layer over the transfer FET of the embedded DRAM cell,
`forming a contact via to expose one of the source/drain
`regions of the FET, and conformally depositing a layer of a
`conductor such as titanium nitride to line the contact via.
`Preferably, the thickness of the deposited layer is substan(cid:173)
`tially thinner than the radius of the contact via so that the
`layer of conductor does not fill in the contact via. This
`process forms a lower capacitor electrode with a cylindrical
`cup shape that provides sufficient surface area to allow the
`capacitor to have an adequate capacitance without the addi(cid:173)
`tional process complexity required to provide a fin or crown
`capacitor electrode structure. A particularly preferred aspect
`of the present invention is that the upper capacitor electrode
`is formed as part of a tungsten plug formation process that
`is also used in forming contacts and interconnects for the
`logic circuits. This combines processes necessary to both the
`DRAM and logic circuits in a very natural manner that
`
`Micron Ex. 1021, p. 12
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`5,998,251
`
`7
`simplifies the overall process flow, improves yields and
`reduces costs. These processes are not conventionally com(cid:173)
`bined because capacitor electrodes are typically polysilicon
`and even highly doped polysilicon is too resistive to be used
`as interconnect plug or interconnect wiring lines for the high
`speed logic circuits.
`Most preferably, the charge storage capacitors of the
`embedded DRAM array have a lower electrode of titanium
`nitride and an upper capacitor electrode of tungsten. Tung(cid:173)
`sten plug interconnects are provided both for the bit line
`contacts of the embedded DRAM array and the source/drain
`and gate contacts of the logic circuitry. Most preferably,
`titanium nitride is used as the barrier or adhesion layer for
`the tungsten plug formation process so that the tungsten
`plugs will have a titanium nitride layer lining the intercon- 15
`nect via and a tungsten plug filling the rest of the via. Thus,
`the capacitor structure differs from the bit line contacts and
`other tungsten plug interconnects found in the logic circuitry
`in that the capacitor has a dielectric layer between the
`titanium nitride layer which forms the lower capacitor 20
`electrode and the tungsten plug which forms the upper
`capacitor electrode. The similarities between the capacitor
`and interconnect structures allows the greater use of com(cid:173)
`mon processing steps in the formation of the DRAM array
`and the logic circuitry.
`Other, more specific aspects of the present invention are
`believed to also present advantages for the manufacture of
`logic circuits including embedded DRAM or other types of
`embedded memory. For example, because the upper capaci(cid:173)
`tor electrode includes a metal formed concurrently with
`portions of the logic circuit's interconnect structure, the ½
`V cc reference potential for the upper capacitor electrode can
`be supplied to an array of upper capacitor electrodes using
`a level of metal wiring lines already made necessary by the
`interconnect structure required by the logic circuitry. This
`use of common wiring line layers further reduces the num(cid:173)
`ber of additional processing steps required to provide
`embedded DRAM to a logic circuit, which is an important
`factor in making embedded DRAM logic circuits manufac(cid:173)
`turable and economical. In another specific aspect of the
`present invention, the titanium nitride layer or similar layer
`of conductive material that forms the lower capacitor elec(cid:173)
`trode extends onto the planarized surface of the interlayer
`dielectric which covers the transfer FET and charge storage
`node. The surface and edges of the lower capacitor electrode
`are covered by a layer of capacitor dielectric and then the
`tungsten upper electrode is formed so that the edges of the
`upper electrode extend beyond the edges of the lower
`electrode. By enclosing the edges of the lower electrode in
`this manner, there is a reduction in the sidewall leakage for
`the capacitor. These and other aspects of the present inven(cid:173)
`tion are now described in greater detail with reference to
`FIGS. 5-16.
`Aspects of the present invention are described with ref(cid:173)
`erence to a particular example of a processing circuit incor- 55
`porating on a single chip embedded DRAM, high speed
`logic circuitry and, as required, 1/0 circuitry capable of
`operating at higher voltages than the logic circuitry. Such
`higher operating voltage 1/0 circuits are desirable when th