Brent Keeth 0 R. Jacob Baker
`
`Circuit Design
`
`
`
`IEEE Press Series on
`Microelectronic Systems
`
`Stuart K. Tewksbury and Joe E. Brewer.
`Series Editors
`
`Micron Ex. 1018, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`|PR2020-01008
`
`Micron Ex. 1018, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`DRAM CIRCUIT DESIGN
`
`----
`
`,,
`
`Micron Ex. 1018, p. 2
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`IEEE Press
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`Books of Related Interest from the IEEE Press
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`A Selected Reprint Volume
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`IEEE Order No. PP5748
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`ISBN 0-7803-3496-5
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`EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple
`Mark I. Montrose
`1999
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`Edited by Vojin G. Oklobdzija
`A Selected Reprint Volume
`1999
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`560 pp
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`Integrated Circuits for Wireless Communications
`Edited by Asad A. Abidi, Paul R. Gray, Robert G. Meyer
`A Selected Reprint Volume
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`688 pp
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`CMOS: Circuit Design, Layout, and Simulation
`R. Jacob Baker, Harry W. Li, David E. Boyce
`IEEE Order No. PC5689
`944 pp
`1998
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`ISBN 0-7803-3416-7
`
`Micron Ex. 1018, p. 3
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`DRAM CIRCUIT DESIGN
`
`A Tutorial
`
`Brent Keeth
`Micron Technology, Inc.
`Boise, Idaho
`
`R. Jacob Baker
`Boise State University
`Micron Technology, Inc.
`Boise, Idaho
`
`IEEE Solid-State Circuits Society, Sponsor
`
`IEEE Press Serles on
`Mlcroelectronic Systems
`
`•
`Stuart K. Tewksbury and Joe E. Brewer, Series Editors
`
`IEEE
`PRESS
`. .
`The Institute of Electrical and Electronics Engineers, Inc., New York
`
`Micron Ex. 1018, p. 4
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`This book and other books may be purchased at a discount
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`Printed in the United States of America.
`
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`7
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`6
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`5
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`1
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`ISBN 0-7803-6014-1
`IEEE Order No. PC5863
`
`Library of Congress Cataloging-in-Publication Data
`
`Keeth, Brent, 1960-
`DRAM circuit design : a tutorial I Brent Keeth, R. Jacob Baker.
`p.cm.
`"IEEE Solid-State Circuits Society, sponsor."
`Includes bibliographical references and index.
`ISBN 0-7803-6014-1
`I. Semiconductor storage devices Design and construction. I. Baker, R. Jacob, 1964-
`II. Title
`
`TK7895.M4 K425 2000
`621.39'732--dc21
`
`00-059802
`
`Micron Ex. 1018, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Contents
`
`Preface ................................................... xi
`
`Acknowledgments ........................................ xiii
`
`List of Figures ............................................ xv
`
`Chapter 1 An Introduction to DRAM
`1.1 DRAM Types and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`1.1.1 The lk DRAM (First Generation) .................... 1
`1.1.2 The 4k-64 Meg DRAM (Second Generation) ........... 7
`1.1.3 Synchronous DRAMs (Third Generation). . . . . . . . . . . . . 16
`1.2 DRAM Basics ....................................... 22
`1.2.1 Access and Sense Operations. . . . . . . . . . . . . . . . . . . . . . . 26
`1.2.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`1.2.3 Opening a Row (Summary) ........................ 31
`1.2.4 Open/Folded DRAM Array Architectures. . . . . . . . . . . . . 33
`
`Chapter 2 The DRAM Array
`2.1 The Mbit Cell ........................................ 35
`2.2 The Sense Amp ...................................... 46
`2.2.1 Equilibration and Bias Circuits . . . . . . . . . . . . . . . . . . . . . 46
`2.2.2 Isolation Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
`2.2.3 Input/Output Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`2.2.4 Nsense- and Psense-Amplifiers ..................... 50
`2.2.5 Rate of Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`2.2.6 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`2.2. 7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`
`Vil
`
`Micron Ex. 1018, p. 6
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`
`

`

`viii
`
`Contents
`
`2.3 Row Decoder Elements ................................. 57
`2.3.1 Bootstrap Wordline Driver ......................... 58
`2.3.2 NOR Driver ..................................... 60
`2.3.3 CMOS Driver ................................... 61
`2.3.4 Address Decode Trees ............................. 62
`2.3.5 Static Tree ...................................... 62
`2.3.6 P&E Tree ....................................... 63
`2.3. 7 Predecoding ..................................... 64
`2.3.8 Pass Transistor Tree .............................. 65
`2.4 Discussion ........................................... 65
`
`Chapter 3 Array Architectures
`3 .1 Array Architectures .................................... 69
`3 .1.1 Open Digitline Array Architecture ................... 69
`3.1.2 Folded Array Architecture ......................... 79
`3.2 Design Examples: Advanced Bilevel DRAM Architecture ..... 87
`3.2.1 Array Architecture Objectives ....................... 88
`3 .2.2 Bilevel Digitline Construction ....................... 89
`3.2.3 Bilevel Digitline Array Architecture .................. 93
`3.2.4 Architectural Comparison .......................... 98
`
`~
`
`Chapter 4 The Peripheral Circuitry
`4.1 Column Decoder Elements ............................. 105
`4.2 Column and Row Redundancy .......................... 108
`4.2.1 Row Redundancy ............................... 110
`4.2.2 Column Redundancy ............................. 113
`
`Chapter 5 Global Circuitry and Considerations
`5.1 Data Path Elements ................................... 117
`5.1.1 Data Input Buffer ................................ 117
`5.1.2 Data Write Muxes ............................... 121
`. ;_ .. .
`5.1.3 Write Driver Circuit ............................. 122
`5.1.4 Data Read Path ................................. 124
`5 .1.5 DC Sense Amplifier (DCSA) ...................... 125
`5.1.6 Helper Flip-Flop (HFF) ........................... 127
`5.1.7 Data Read Muxes ......................... : . .... 129
`5.1.8 Output Buffer Circuit ............................ 129
`5.1.9 Test Modes ............................... · ..... 131
`
`Micron Ex. 1018, p. 7
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`
`

`

`Contents
`
`ix
`
`5 .2 Address Path Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
`· 5.2.1 Row Address Path .............................. 133
`5.2.2 Row Address Buffer. ............................ 133
`5.2.3 CBR Counter .................................. 134
`5.2.4 Predecode Logic ................................ 135
`5.2.5 Refresh Rate ................................... 135
`5.2.6 Array Buffers .................................. 137
`5.2.7 Phase Drivers .................................. 137
`5.2.8 Column Address Path ............................ 138
`5.2.9 Address Transition Detection ...................... 139
`5.3 Synchronization in DRAMs ............................ 142
`5 .3 .1 The Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
`5.3.2 The Basic Delay Element. ........................ 144
`5 .3 .3 Control of the Shift Register . . . . . . . . . . . . . . . . . . . . . . 145
`5.3.4 Phase Detector Operation ......................... 146
`5.3.5 Experimental Results ............................ 147
`5.3.6 Discussion .................................... 149
`
`Chapter 6 Voltage Converters
`6.1 Internal Voltage Regulators ............................ 155
`6.1.1 Voltage Converters .............................. 155
`6.1.2 Voltage References .............................. 156
`. 6.1.3 Bandgap Reference .............................. 161
`6.1.4 The Power Stage ................................ 162
`6.2 Pumps and Generators ................................ 166
`6.2.1 Pumps ......................................... 167
`6.2.2 DVC2 Generator. ............................... 174
`6.3 Discussion ......................................... 174
`
`Appendix . .......................................... 177
`
`Glos~ary ........................................... 189
`
`Index .............................................. 193
`
`About the Authors ................................... 199
`
`Micron Ex. 1018, p. 8
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`

`

`List of Figures
`
`Chapter 1 An Introduction to DRAM
`
`I ,024-bit DRAM functional diagram .................... 2
`1. I
`I,024-bit DRAM pin connections ....................... 3
`1.2
`Ideal address input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
`I .3
`Layout of a I ,024-bit memory array ..................... 4
`1.4
`Ik DRAM Read cycle ................................ 5
`I .5
`Ik DRAM Write cycle ............................... 6
`1.6
`Ik DRAM Refresh cycle .............................. 6
`1. 7
`3-transistor DRAM cell ............................... 7
`1.8
`Block diagram of a 4k DRAM ......................... 9
`1.9
`4,096-bit DRAM pin connections ....................... 9
`1. I 0
`I. I I Address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 0
`1. I2
`I-transistor, I-capacitor (1 TIC) memory cell ............. I I
`Row ofN dynamic memory elements ................... 12
`1.I3
`1.I4
`Page mode ........................................ I5
`I.I5
`Fast page mode .................................... I6
`.I.I6 Nibble mode ...................................... I6
`I. I 7
`Pin connections of a 64Mb SDRAM with I 6-bit I/O ....... 17
`1.I8 Block diagram of a 64Mb SDRAM with I6-bit I/O ........ I9
`1. I 9
`SD RAM with a latency of three ....................... 2 I
`
`xv
`
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`

`

`xvi
`
`List of Figures
`
`1.20 Mode register ...................................... 23
`1.21
`1T1C DRAM memory cell ........................... 24
`1.22 Open digitline memory array schematic ................. 25
`1.23 Open digitline memory array layout .................... 25
`Simple array schematic .............................. 26
`1.24
`Cell access waveforms ............ · ................... 27
`1.25
`1.26 DRAM charge-sharing ............................... 28
`1.27
`Sense amplifier schematic ............................ 28
`1.28
`Sensing operation waveforms ......................... 29
`Sense amplifier schematic with 1/0 devices .............. 30
`1.29
`1.30 Write operation waveforms ........................... 31
`1.31 A folded DRAM array ............................... 33
`
`Chapter 2 The DRAM Array
`
`2.1 Mbit pair layout .................................... 36
`2.2
`Layout to show array pitch ........................... 36
`Layout to show 8F2 derivation ......................... 38
`2.3
`2.4
`Folded digitline array schematic ....................... 39
`2.5
`.Digitline twist schemes .............................. 40
`2.6 Open digitline array schematic ........................ 41
`2.7 Open digitline array layout ........................... 42
`2.8
`Buried capacitor cell process cross section ............... 43
`2.9
`Buried capacitor cell process SEM image ................ 43
`2.10
`Buried digitline mbit cell layout ....................... 43
`2.11
`Buried digitline mbit process cross section ............... 44
`2.12 Buried digitline mbit process SEM image ................ 45
`2.13
`Trench capacitor mbit process cross section .............. 45
`2.14
`Trench capacitor mbit process SEM image ............... 46
`2.15
`Equilibration schematic .............................. 47
`
`Micron Ex. 1018, p. 10
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`
`

`

`List of Figures
`
`xvii
`
`Equilibration and bias circuit layout .................... 48
`2.16
`1/0 transistors ..................................... 50
`2.17
`Basic sense amplifier block ........................... 51
`2.18
`Standard sense amplifier block ........................ 53
`2.19
`Complex sense amplifier block ........................ 53
`2.20
`Reduced sense amplifier block ........................ 53
`2.21
`2.22 Minimum sense amplifier block ....................... 54
`2.23
`Single-metal sense amplifier block ..................... 55
`2.24 Waveforms for the Read-Modify-Write cycle ............ 56
`Bootstrap wordline driver ............................ 59
`2.25
`2.26
`Bootstrap operation waveforms ....................... 59
`2.27 Donut gate structure layout ........................... 60
`2.28 NOR driver ....................................... 61
`2.29
`CMOS driver ...................................... 62
`2.30
`Static decode tree .................................. 63
`2.31
`P&E decode tree ................................... 64
`2.32
`Pass transistor decode tree ............................ 65
`
`Chapter 3 Array Architectures
`
`Open digitline architecture schematic ................... 71
`3 .1
`3.2 Open digitijne 32-Mbit array block ..................... 73
`3 .3
`Single-pitch open digitline architecture ......... ~ ....... 7 6
`3 .4 Open digitline architecture with dummy arrays ........... 77
`Folded digitline array architecture schematic . . . . . . . . . . . . . 80
`3 .5
`3.6
`Folded digitline architecture 32-Mbit array block ......... 84
`3. 7 Development of bilevel digitline architecture ............. 90
`3.8 Digitline vertical twisting concept ..................... 90
`Bilevel digitline architecture schematic ................. 92
`3.9
`3 .10 Vertical twisting schemes ............................ 93
`
`Micron Ex. 1018, p. 11
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`

`xviii
`
`List of Figures
`
`3 .11
`3.12
`3.13
`
`Plaid 6F2 mbit array ................................. 94
`Bilevel digitline array schematic ....................... 95
`Bilevel digitline architecture 32-Mbit array block. ......... 97
`
`Chapter 4 The Peripheral Circuitry
`
`4.1
`4.2
`4.3
`4.4
`4.5
`4.6
`4.7
`
`Column decode ................................... 107
`Column selection timing ............................ 107
`Column decode: P &E logic .......................... 109
`Coiumn decode waveforms .......................... 110
`Row fuse block ................................... 112
`Column fuse block ................................. 115
`8-Meg x 8-sync DRAM poly fuses .................... 116
`
`Chapter 5 Global Circuitry and Considerations
`
`Data input buffer .................................. 118
`5 .1
`Stub series terminated logic (SSTL) ................... 119
`5.2
`5.3 Differential amplifier-based input receiver .............. 120
`Self-biased differential amplifier-based input buffer. ...... 121
`5.4
`5.5
`Fully differential amplifier-based input buffer ........... 121
`5.6 Data Write mux ................................... 123
`5.7 Write driver ...................................... 124
`110 bias circuit .................................... 125
`5.8
`110 bias and operation waveforms ..................... 126
`5.9
`5.10 DC sense amp .................................... 127
`5.11 DCSA operation waveforms ......................... 128
`5.12 A helper flip-flop .................................. 128
`5.13 Data Read mux ..................................... 130
`5.14 Output buffer ..................................... 131
`5.15
`Row address buffer ................................ 134
`5 .16 Row address predeco~de circuits ....................... 13 6
`
`Micron Ex. 1018, p. 12
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`
`

`

`List of Figures
`
`xix
`
`Phase decoder/driver ............................... 138
`5.17
`Column address buffer ............................. 139
`5.18
`Equilibration driver ................................ 140
`5.19
`Column predecode logic ............................ 141
`5.20
`SDRAM CLK input and DQ output ................... 142
`5.21
`5.22 Block diagram for DDR SDRAM DLL ................ 143
`5.23 Data timing chart for DDRDRAM .................... 144
`Phase detector used in RSDLL . . . . . . . . . . . . . . . . . . . . . . . 145
`5 .24
`5.25
`Symmetrical delay element used in RSDLL ............. 146
`5.26 Delay line and shift register for RSDLL ................ 146
`5.27 Measured rms jitter versus input frequency ............. 148
`5.28 Measured delay per stage versus V cc and temperature .... 148
`5.29 Measured ICC versus input frequency ................. 149
`5 .30
`Two-way arbiter as a phase detector ................... 150
`5.31
`Circuit for generating shift register control. ............. 150
`5.32 A double inv:erter used as a delay element .............. 151
`5.33
`Transmission gates added to delay line ................. 151
`5.34
`Inverter implementation ............................ 152
`5.35
`Segmenting delays for additional clocking taps .......... 152
`
`Chapter 6 Voltage Converters
`
`Ideal regulator characteristics ........................ 157
`6.1
`6.2 Alternative regulator characteristics ................... 158
`6.3
`Resistor/diode voltage reference ...................... 159
`6.4 Voltage regulator characteristics ...................... 159
`6.5
`Improved voltage reference .......................... 161
`6.6
`Bandgap reference circuit ........................... 162
`6.7
`Power op-amp .................................... 163
`6.8
`Power stage ...................................... 164
`
`Micron Ex. 1018, p. 13
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`

`xx
`
`List of Figures
`
`6.9
`
`6.10
`
`6.11
`
`6.12
`
`Regulator control logic ............................. 166
`
`Simple voltage pump circuit ......................... 168
`
`Veep pump ....................................... 169
`
`VBB pump ........................................ 169
`
`6.13
`
`6.14
`
`Ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
`V ccP regulator .................................... 170
`VBB regulator ..................................... 170
`V ccP differential regulator ........................... 173
`V BB differential regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4
`Simple DVC2 generator. ............................ 175
`6.18
`6.19 DVC2 generator ................................... 176
`
`6.15
`
`6.16
`
`6.17
`
`Micron Ex. 1018, p. 14
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Chapter
`1
`
`An Introduction to DRAM
`
`Dynamic random access memory (DRAM) integrated circuits (ICs) have
`existed for more than twenty-five years. DRAMs evolved from the earliest
`1-kilobit (Kb) generation to the recent 1-gigabit (Gb) generation through
`advances in both semiconductor process and circuit design technology. Tre(cid:173)
`mendous advances in process technology have dramatically reduced feature
`size, permitting ever higher levels of integration. These increases in integra(cid:173)
`tion have been accompanied by major improvements in component yield to
`ensure that overall process solutions remain cost-effective and competitive.
`Technology improvements, however, are not limited to semiconductor pro(cid:173)
`cessing. Many of the advances in process technology have been accompa(cid:173)
`nied or enabled by advances in circuit design technology. In most cases,
`advances in one have enabled advances in the other. In this chapter, we
`introduce some fundamentals of the DRAM IC, assuming that the reader
`has a basic background in complementary metal-oxide semiconductor
`(CMOS) circuit design, layout, and simulation [1].
`
`1.1 DRAM TYPES AND OPERATION
`
`To gain insight into how modern DRAM chips are designed, it is useful to
`look into the evolution of DRAM. In this section, we offer an overview of
`DRAM types and modes of operation.
`
`1.1.1 The 1 k DRAM (First Generation)
`
`We begin our discussion by looking at the 1,024-bit DRAM (1,024 x
`1 bit). Functional diagrams and pin connections appear in Figure 1.1 and
`Figure 1.2, respectively. Note that there are 10 address inputs with pin
`labels R 1-R 5 and C 1-C 5 • Each address input is connected to an on-chip
`address input buffer. The input buffers that drive. the row (R) and column
`
`1
`
`Micron Ex. 1018, p. 15
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`IPR2020-01008
`
`

`

`2
`
`Chap. 1 An Introduction to DRAM
`
`(C) decoders in the block diagram have two purposes: to provide a known
`input capacitance ( CJN) on the address input pins and to detect the input
`address signal at a known level so as to reduce timing errors. The level
`V TRJP, an idealized trip point around which the input buffers slice the input
`signals, is important due to the finite transition times on the chip inputs
`(Figure 1.3). Ideally, to avoid distorting the duration of the logic zeros and
`ones, VrRIP should be positioned at a known level relative to the maximum
`and minimum input signal amplitudes. In other words, the reference level
`should change with changes in temperature, process conditions, input maxi(cid:173)
`mum amplitude (VIH ), and input minimum amplitude (V1L). Having said
`this, we note that the input buffers used in first-generation DRAMs were
`simply inverters.
`Continuing our discussion of the block diagram shown in Figure 1.1,
`we see that five address inputs are connected through a decoder to the
`1,024-bit memory array in both the row and column directions. The total
`number of addresses in each direction, resulting from decoding the 5-bit
`word, is 32. The single memory array is made up of 1,024 memory elements
`laid out in a square of 32 rows and 32 columns. Figure 1.4 illustrates the
`conceptual layout of this memory array. A memory element is located at the
`intersection of a row and a column.
`
`Vss
`
`Voo
`
`Column refresh
`amplifiers
`
`Butter
`
`,__,_< 1 DoUT
`
`Cell matrix
`1,024 bits
`
`Figure 1.1 1,024-bit DRAM functional diagram.
`
`Micron Ex. 1018, p. 16
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`

`

`Sec. 1.1 DRAM Types and Operation
`
`3
`
`•
`
`C2 1
`
`C1
`
`2
`
`RIW3
`
`R2 4
`
`Rs 5
`
`R4 6
`
`Rs 7
`
`R1
`
`8
`
`16 Cs
`
`14 Cs
`
`13 CE
`
`12 Dour
`
`10 Vss
`
`9 Voo
`
`Figure 1.2 1,024-bit DRAM pin connections.
`
`Pad
`
`Input signal
`
`VrRIP
`
`Output to
`>------decoders
`
`Input
`signal
`
`ViH v- -\-vrRIP
`
`1
`
`ViL
`
`.__ __ Output signal
`
`Figure 1.3 Ideal address input buffer.
`
`By applying an address of all zeros to the 10 address input pins, the
`memory data located at the intersection of rowO, RA 0, and column 0, CA 0, is
`accessed. (It is either written to or read out, depending on the state of the RIW
`input and assuming that the CE pin is LOW so that the chip is enabled.)
`It is important to realize that a single bit of memory is accessed by using
`
`both a row and a cblumn address. Modem DRAM chips reduce the number
`
`of external pins required for the memory address by using the same pins for
`
`Micron Ex. 1018, p. 17
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`4
`
`Chap. 1 An Introduction to DRAM
`
`Column address decoder outputs
`CA30 CA31
`CAO CA1 CA2
`
`RAO
`
`RA1
`
`RA2
`
`-
`-
`
`RA30
`
`RA31
`
`-
`
`~
`
`The intersection
`of a row and
`.. ,/
`column is the
`___.... _,__
`location of a
`' ..
`memory bit.
`- -
`-
`
`-
`- ,_
`
`Figure 1.4 Layout of a 1,024-bit memory array.
`
`both the row and column address inputs (address multiplexing). A clock sig(cid:173)
`nal row address strobe (RAS) strobes in a row address and then, on the same
`set of address pins, a clock signal column address strobe (CAS) strobes in a
`column address at a different time.
`Also note how a first-generation memory array is organized as a logical
`square of memory elements. (At this point, we don't know what or how the
`memory elements are made. We just know that there is a circuit at the inter-
`. section of a row and column that stores a single bit of data.) In a modem
`DRAM chip, many smaller memory arrays are organized to achieve a larger
`memory size. For example, 1,024 smaller memory arrays, each composed
`of 256 kbits, may constitute a 256-Meg (256 million bits) DRAM.
`
`1.1.1.1 Reading Data Out of the lk DRAM. Data can be read out of
`the DRAM by first putting the chip in the Read mode by pulling the RIW
`pin HIGH and then placing the chip enable pin CE in the LOW state. Figure
`1.5 illustrates the timing relationships between changes in the address
`inputs and data appearing on the Dour pin. Important timing specifications
`present in this figure are Read cycle time (tRc) and Access time (tAc). The
`term tRc specifies how fast the memory can be read. If tRc is 500 ns, then
`the DRAM can supply 1-bit words at a rate of 2 MHz. The term tAc speci-
`
`Micron Ex. 1018, p. 18
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 1.1 DRAM Types and Operation
`
`5
`
`fRC
`1
`1
`,4
`~.
`, Address changing ,
`~
`I
`
`Address
`R1-R5 and
`C1-C5
`
`Data out,
`Dour
`
`-------~x·:----------
`
`RIW= 1 CE=O
`
`Figure 1.5 lk DRAM Read cycle.
`
`fies the maximum length of time after the input address is changed beforethe
`output data (DouT) is valid.
`
`1.1.1.2 Writing to the lk DRAM. Writing data to the DRAM is accom(cid:173)
`plished by bringing the RIW input LOW with valid data present onthe DIN
`pin. Figure 1.6 shows the timing diagram for a Write cycle. The term Write
`cycle time (twc) is related to the maximum frequency at which we can write
`data into the DRAM. The term Address to Write delay time (tAw) specifies the
`time between the address changing and the RIW input going LOW. Finally,
`Write pulse width (twp) specifies how long the input data must be present
`before the RIW input can go back HIGH in preparation for another Read or
`Write to the DRAM. When writing to the DRAM, we can think of the RIW
`input as a clock signal.
`
`1.1.1.3 Refreshing the lk DRAM. The dynamic nature of DRAM
`requires that the memory be refreshed periodically so 'as not to lose the con(cid:173)
`tents of the memory cells. Later we will discuss the mechanisms that lead to
`the dynamic operation of the memory cell. At this point, we discuss how
`memory Refresh is accomplished for the lk DRAM.
`Refreshing a DRAM is accomplished internally: external data to the
`DRAM need not be applied. To refresh the DRAM, we periodically access
`the memory with every possible row address combination. A timing diagram
`for a Refresh cycle is shown in Figure 1. 7. With the CE input pulled HIGH,
`the address is changed, while the RIW input is used as a strobe or clock sig(cid:173)
`nal. Internally, the data is read out and then written back into the same loca(cid:173)
`tion at full voltage; thus, logic levels are restored (or refreshed).
`
`Micron Ex. 1018, p. 19
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`6
`
`Chap. I An Introduction to DRAM
`
`I
`~·
`
`---...J---· I
`•..-:;;sons
`\
`
`I
`
`CE
`
`I
`~tow.....,.,
`I
`11
`
`----------* 1:-~ 0 ~
`
`Data
`input
`
`Figure 1.6 lk DRAM Write cycle.
`
`twc
`
`tAw
`
`:
`Ill I II
`
`twp
`
`Row
`address
`inputs
`
`RIW
`CE=1
`
`Figure 1.7 lk DRAM Refresh cycle.
`
`1.1.1.4 A Note on the Power Supplies. The voltage levels used in the
`lk DRAM are unusual by modem-day standards. In reviewing Figure 1.2,
`we see that the lk DRAM chip uses two power supplies: l'.JDD and Vss· To
`begin, Vss is a greater voltage than V DD: Vss is nominally 5 V, while V DD is
`-12 V. The value of Vss was set by the need to interface to logic circuits that
`were implemented using transistor-transistor logic (TTL) logic. The 17-V
`difference between VDD and Vss was necessary to maintain a large signal-to(cid:173)
`noise ratio in the DRAM array. We discuss these topics in greater detail later
`in the book. The Vss power supply used in modem DRAM designs, at the
`time of this writing, is generally zero; the VDD is in the neighborhood of
`2.5 v.
`
`Micron Ex. 1018, p. 20
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 1.1 DRAM Types and Operation
`
`7
`
`1.1.1.5 The 3-Transistor DRAM Cell. One of the interesting circuits
`used in the lk DRAM (and a few of the 4k and 16k DRAMs) is the 3-transis(cid:173)
`tor DRAM memory cell shown in Figure 1.8. The column- and rowlines
`shown in the block diagram of Figure 1.1 are split into Write and Read line
`pairs. When the Write rowline is HIGH, Ml turns ON. At this point, the data
`present on the Write columnline is passed to the gate of M2, and the informa(cid:173)
`tion voltage charges or discharges the input capacitance of M2. The next, and
`final, step in writing to the·mbit cell is to tum OFF the Write rowline by driv(cid:173)
`ing it LOW. At this point, we should be able to see why the memory is called
`dynamic. The charge stored on the input capacitance of M2 will leak off over
`time.
`
`Write columnline
`
`Read columnline
`
`Read rowline--- - - - - - - - - - - - -
`
`Write rowline - - --1-----------1---
`
`Input /:l:
`
`capacitance
`ofM2
`
`v Storage node
`
`Figure 1.8 3-transistor DRAM cell.
`
`If we want to read out the contents of the cell, we begin by first precharg(cid:173)
`ing the R~ad columnline to a known voltage and then driving the Read row(cid:173)
`line HIGH. Driving the Read rowline HIGH turns M3 ON and, allows M2
`either to pull the Read columnline LOW or to not change the precharged
`voltage of the Read columnline. (If M2's gate is a logic LOW, then M2 will
`be OFF, having no effect on the state of the Read columnline.) The main
`drawback of using the 3-transistor DRAM cell, and the reason it is no longer
`used, is that it requires two pairs of column and rowlines and a large layout
`area. Modem I-transistor, I-capacitor DRAM cells use a single rowline, a
`single columnline, and considerably less area.
`
`1.1.2 The 4k-64 Meg DRAM (Second Generation)
`
`first-generation
`from
`We distinguish second-generation DRAMs
`DRAMs by the introduction of multiplexed address inputs, multiple memory
`
`Micron Ex. 1018, p. 21
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`\
`
`8
`
`Chap. 1 An Introduction to DRAM
`
`arrays, and the I-transistor/I-capacitor memory cell. Furthermore, second(cid:173)
`generation DRAMs offer more modes of operation for greater flexibility or
`higher speed operation. Examples are page mode, nibble mode, static col(cid:173)
`umn mode, fast page mode (FPM), and extended data out (EDO). Second(cid:173)
`generation DRAMs range in size from 4k (4,096 x I bit, i.e., 4,096 address
`locations with I-bit input/output word size) up to 64 Meg (67,I08,864 bits)
`in memory sizes of I6 Meg x 4 organized as I6,777,216 address locations
`with 4-bit input/output word size, 8 Meg x 8, or 4 Meg x 16.
`Two other major changes occurred in second-generation DRAMs:
`(1) the power supply transitioned to a single 5 V and (2) the technology
`advanced from NMOS to CMOS. The cha~e to a single 5 V supply
`occurred at the 64kbit density. It si~lified system design to a single power
`supply for the memory, processor, and any TTL logic used in the system. As
`a result, rowlines had to be driven to a voltage greater than 5 V to tum the
`NMOS access devices fully ON (more on this later), and the substrate held
`at a potential less than zero. For voltages outside the supply range, charge
`pumps are used (see Chapter 6). The move from NMOS to CMOS, at the
`lMb density level, occurred because of concern