United States Patent (19)
`Matsubara et al.
`
`USOO6037625A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,037,625
`Mar. 14, 2000
`
`54 SEMICONDUCTOR DEVICE WITH
`
`SIESERE AND FABRICATION
`75 Inventors:
`is M.tly Maste
`awala, both of Iokyo, Japan
`73 Assignee: NEC Corporation, Tokyo, Japan
`
`FOREIGN PATENT DOCUMENTS
`
`is is in
`OTHER PUBLICATIONS
`Y. Tang et al., “Different Dependence of Band-to-Band and
`Fowler-Nordheim Tunnelling on Source Doping Concen
`tration of an n-MOSFET, pp. 525-527, IEEE Electron
`Device Letters, vol. 17, No. 11, Nov. 1996.
`H.K. Park et al., “Effects of Ion Implantation Doping on the
`Formation of TiSi", Journal of vacuum Science and Tech
`21 Appl. No.: 09/206,377
`nology, vol. 2, No. 2, 1984, pp. 264-268.
`22 Filed:
`Dec. 7, 1998
`Primary Examiner Mary Wilczewski
`O
`O
`Attorney, Agent, or Firm Young & Thompson
`Foreign Application Priority Data
`30
`57
`ABSTRACT
`Dec. 8, 1997
`JP
`Japan .................................... 9-336774
`51) Int. Cl." ...................... H01L 21/8239; H01L 27/105 A Semiconductor device is provided, which makes it pos
`52 U.S. ision assi: 535. i.e. i.
`Sible to decrease the electric sheet resistance of Source/drain
`s
`s
`s
`s 438/2s
`regions of MOSFETs in a peripheral circuitry without deg
`radation of the data writing Speed in nonvolatile memory
`cells. This device is comprised of nonvolatile memory cells
`and a peripheral circuitry provided on a Same Semiconductor
`substrate. The nonvolatile memory cells are formed by a first
`plurality of MOSFETs of a first conductivity type. The
`peripheral circuitry includes a second plurality of MOSFETs
`of the first conductivity type. Each of the first plurality of
`MOSFETs is equipped with a gate electrode having a
`floating gate for data Storing and Source/drain regions having
`substantially no silicide films. Each of the second plurality
`of MOSFETs is equipped with source/drain regions having
`silicide films and a doping concentration lower than that of
`the Source/drain regions of each of the first plurality of
`MOSFETs. It is preferred that the doping concentration of
`the source/drain regions of the first plurality of MOSFETs is
`equal to 1x10' atoms/cm or higher and the doping con
`centration of the Source/drain regions of the Second plurality
`of MOSFETs is lower than 1x10' atoms/cm.
`
`58 Field of Search ........................... - - - - - - - - - 257/315, 382,
`257/383,384, 390; 438/200, 201, 211,
`230, 231, 233, 257, 258, 265, 275, 598,
`649, 655, 682, 683, 660, FOR 360, FOR 359,
`FOR 189, FOR 196, FOR 211, FOR 212,
`FOR 216, FOR 217, FOR 218, FOR 219
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,471,373 9/1984 Shimizu et al. ........................ 257/315
`E. 1. R ea
`4,918,501
`4/1990 Komoriet al... 2573s
`5,262,344 11/1993 Mistry.
`5,585,299 12/1996 Hsu.
`5,672,527 9/1997 Lee.
`5,904,518 5/1999 Komori et al. ......................... 438/201
`5,907,171 5/1999 Santin et al. ............................ 257/315
`5,946,573 8/1999 Hsu ......................................... 438/275
`
`
`
`SS
`
`L. 33
`% % 3. 2
`S. SE MY WyYaw
`3. % 3. ad N. Y. YaYY-axYa is
`Z. ZZ
`Y. All
`
`6 Claims, 16 Drawing Sheets
`
`Se22N
`Se222222N NS Nissa
`N5.
`NelseN
`
`Micron Ex. 1015, p. 1
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 1 of 16
`
`6,037,625
`
`F. G. 1A
`PRIOR ART
`
`F. G. 1B
`
`
`
`
`
`7 N.
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`F. G. 1C
`PRIOR ART
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`
`Micron Ex. 1015, p. 2
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 2 of 16
`
`6,037,625
`
`F. G. 1D
`PRIOR ART
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`Micron Ex. 1015, p. 3
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 3 of 16
`
`6,037,625
`
`F. G. 1 G
`PRIOR ART
`
`111 111110
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`Micron Ex. 1015, p. 4
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 4 of 16
`
`6,037,625
`
`F. G. 1 J
`PRIOR ART
`117b 117
`117a .273'-
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`
`Micron Ex. 1015, p. 5
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`US. Patent
`
`Mar. 14, 2000
`
`Sheet 5 0f 16
`
`6,037,625
`
`FIG.2A
`
`51
`
`52
`
`53
`
`FIG.ZB
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`
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`FIG. 20
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`51
`
`52
`
`Micron Ex. 1015, p. 6
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`US. Patent
`
`Mar. 14,2000
`
`Sheet 6 0f 16
`
`6,037,625
`
`FIG.2D
`
`3b
`
`3b
`
`
`
`53
`
`FIG.2E
`
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`
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`
`Micron Ex. 1015, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`|PR2020-01008
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`Micron Ex. 1015, p. 7
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`

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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 7 of 16
`
`6,037,625
`
`F. G. 2G
`
`
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`
`Micron Ex. 1015, p. 8
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 8 of 16
`
`6,037,625
`
`F. G. 2J
`127b 17a
`
`12
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`
`Micron Ex. 1015, p. 9
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`US. Patent
`
`Mar. 14, 2000
`
`Sheet 9 0f 16
`
`6,037,625
`
`FIG. 3A
`
`51
`
`52
`
`FIG. 3B
`
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`51
`
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`
`51
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`
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`
`Micron Ex. 1015, p. 10
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`US. Patent
`
`Mar. 14, 2000
`
`Sheet 10 0f 16
`
`6,037,625
`
`FIG. 3D
`
`3b
`
`3b
`
`FIG.3E
`
`
`
`
`FIG.3F
`
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`Micron Ex. 1015, p. 11
`Micron v. Godo Kaisha IP Bridge 1
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`Micron Ex. 1015, p. 11
`Micron v. Godo Kaisha IP Bridge 1
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 11 of 16
`
`6,037,625
`
`F. G. 3G
`
`
`
`
`
`
`
`
`
`
`
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`Micron Ex. 1015, p. 12
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 12 of 16
`
`6,037,625
`
`
`
`
`
`4
`
`
`
`-- 377 (7. 27
`IN
`
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`
`Micron Ex. 1015, p. 13
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 13 of 16
`
`6,037,625
`
`F. G. 4
`
`SILIC DE FILM WDTH
`O : 0.2um
`O : 10um
`
`
`
`100
`
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`
`2 5
`
`O
`
`8
`6
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`2
`As-ION DOSE ( x 1015cm2)
`
`10
`
`Micron Ex. 1015, p. 14
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 14 of 16
`
`6,037,625
`
`F. G. 5
`
`T-FILM THICKNESS - 50mm
`
`AS- ON DOSE
`A1:2 x 1015cm2
`A2.5 x 1015cm2
`
`A2
`
`
`
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`
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`
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`
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`
`O. 5
`
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`WDTH (pum)
`
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`
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`
`Micron Ex. 1015, p. 15
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`U.S. Patent
`
`Mar. 14, 2000
`
`Sheet 15 of 16
`
`6,037,625
`
`F.G. 6
`
`T-FILM THICKNESS - 20mm
`
`B2
`
`AS- ON DOSE
`B1.2 x 1015cm2
`B2.5 x 1015cm2
`
`
`
`100
`
`7 5
`
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`
`2 5
`
`O
`
`0. 5
`
`1... O
`WDTH (um)
`
`1.5
`
`2.. O
`
`Micron Ex. 1015, p. 16
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`U.S. Patent
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`Mar. 14, 2000
`
`Sheet 16 of 16
`
`6,037,625
`
`F. G. 7
`
`SLCIDE FILM WDTH
`C1:0. 2pum
`C2: 0.5 pum
`
`
`
`100
`
`G 75
`N
`C
`
`&
`
`25
`
`O
`
`50
`40
`30
`20
`10
`TITANIUM FILM THICKNESS (nm)
`
`60
`
`Micron Ex. 1015, p. 17
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`

`1
`SEMCONDUCTOR DEVICE WITH
`SALCIDE STRUCTURE AND FABRICATION
`METHOD THEREOF
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a Semiconductor device
`with a self-aligned silicide (SALICIDE) structure and a
`fabrication method thereof and more particularly, to a Semi
`conductor device equipped with nonvolatile memory cells
`formed by Metal-Oxide-Semiconductor Field-Effect Tran
`sistors (MOSFETs) and a peripheral circuitry including
`MOSFETs on a semiconductor Substrate, in which the
`MOSFETs of the peripheral circuitry have silicide layers at
`their source/drain regions while the MOSFETs of the
`memory cells have no Silicide layers at their Source/drain
`regions, and a fabrication method of the Semiconductor
`device.
`2. Description of the Prior Art
`Conventionally, the miniaturization and integration of
`Semiconductor elements and components have been pro
`gressing perpetually in Semiconductor integrated circuit
`devices.
`In recent years, highly-integrated Semiconductor inte
`grated circuit devices (i.e., LSIs) designed according to the
`design rule as Small as 0.15 to 0.25 um, Such as memory
`devices and logic devices, have been fabricated and actually
`used. These LSIs are often constituted by the use of
`MOSFETs, because MOSFETs are miniaturized more
`readily than bipolar transistors.
`According to the progressing integration of the Semicon
`ductor elements and components in the LSIs, there has been
`the need to decrease the length of the gate electrodes and the
`width of the source/drain regions in the MOSFETs.
`However, the decrease in the length of the gate electrodes
`and the width of the Source/drain regions increases their
`electric resistance and as a result, there arises a problem that
`the operation speed of the inner circuits of the LSIs tends to
`be badly affected.
`To solve this problem, refractory silicide layers, which are
`low in electric resistance, have been widely used for the
`Source/drain regions formed in a single-crystal Silicon (Si)
`Substrate and the gate electrodes made of polycrystalline Si
`(i.e., polysilicon) in the miniaturized MOSFETs. The refrac
`tory Silicide layers are typically located on the Surface areas
`of the Source/drain regions and the gate electrodes.
`The silicide layers are typically formed by the use of the
`well-known SALICIDE technique. Specifically, first, a
`refractory metal Such as a titanium (T) film is formed in
`contact with the Single-crystal Si Source/drain regions and
`the polysilicon gate electrodes. Then, the refractory metal
`film, the Source/drain regions, and the gate electrodes are
`heat-treated to cause a Silicidation reaction between the
`refractory metal and Si. Thus, refractory silicide films are
`formed at the Surface areas of the Source/drain regions, and
`the gate electrodes, respectively. Finally, the unreacted
`refractory metal film is removed. Since the refractory sili
`cide films are formed in Self-alignment to the gate electrodes
`and an isolation dielectric without any masking film, this
`formation method is termed the “self-aligned silicide”
`technique, or the “SALICIDE” technique. Also, the source/
`drain regions and the gate electrodes equipped with the
`silicide films thus formed are termed the “SALICIDE”
`Structure.
`FIGS. 1A to 1K show a conventional fabrication method
`of a flush nonvolatile semiconductor memory device which
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6,037,625
`
`2
`is termed a flush Electrically Erasable Programmable Read
`Only Memory (EEPROM), in which the SALICIDE tech
`nique is used.
`This memory device is comprised of a lot of nonvolatile
`memory cells formed by n-channel MOSFETs with floating
`gates and a peripheral circuitry formed by n- and p-channel
`MOSFETs. Therefore, the peripheral circuitry has the
`Complementary MOS (CMOS) structure. The peripheral
`circuitry Serves to provide control operations for the
`memory cells, Such as the reading operation and the writing
`or reprogramming operation. The memory cells are arranged
`in a matrix array in a memory cell area. The n- and p-channel
`MOSFETs of the peripheral circuitry are arranged in periph
`eral NMOS and PMOS areas, respectively.
`In FIGS. 1A to 1K, however, two adjoining ones of the
`n-channel MOSFETs in the memory cells, one of the
`n-channel MOSFETs in the peripheral circuitry, and one of
`the p-channel MOSFETs in the peripheral circuitry are
`explained below for the Sake of simplification of description.
`First, as shown in FIG. 1A, an isolation dielectric 102
`with a specific depth is Selectively formed at the main
`surface of a p- or n-type single-crystal Si Substrate 101 by
`the well-known Local Oxidation of Silicon (LOCOS)
`process, thereby defining a peripheral NMOS area 151 and
`a peripheral PMOS area 152 of the peripheral circuitry and
`a memory cell area 153.
`Next, a patterned photoresist film 103a with a window
`uncovering the peripheral NMOS area 151 is formed using
`a photolithography technique. Then, using the photoresist
`film 103a as a mask, boron (B) is selectively ion-implanted
`into the substrate 101, thereby forming a p-type well 104 in
`the peripheral NMOS area 151, as shown in FIG. 1B.
`Thereafter, the photoresist film 103a is removed.
`In the same way as that of the p-type well 104, an n-type
`well 105 is formed in the peripheral PMOS area 152 and a
`p-type well 106 is formed in the memory cell area 153, as
`shown in FIG. 1C.
`A silicon dioxide (SiO2) film 137 is formed on the whole
`main surface of the substrate 101 by a thermal oxidation
`process, as shown in FIG. 1D. By successive Chemical
`Vapor Deposition (CVD) processes, a polysilicon film 138
`(approximately 150 nm in thickness) is formed on the whole
`SiO film 137, an ONO film 139 is formed on the whole
`polysilicon film 138, and a tungsten polycide film 140 is
`formed on the whole ONO film 139. The ONO film 139 is
`formed by three stacked subfilms, i.e., a SiO subfilm, a
`silicon nitride (SiN.) Sub film, and a SiO subfilm. The
`tungsten polycide film 140 is a composite film of an
`impurity-doped polysilicon Subfilm and a tungsten Silicide
`subfilm, where the impurity is typically phosphorus (P).
`Thereafter, a patterned photoresist film 103b with a pat
`tern covering the areas for gate electrodes is formed using a
`photolithography technique. Then, using the photoresist film
`103b as a mask, the polysilicon film 138, the ONO film 139,
`and the tungsten polycide film 140 are Successively
`patterned, thereby forming gate electrodes 111 for the
`n-channel MOSFETs arranged in the memory cell area 153,
`as shown in FIG. 1E. The gate electrodes 111 are formed by
`the combination of the remaining polysilicon film 138, the
`remaining ONO film 139, and the remaining tungsten poly
`cide film 140. In this patterning process, the SiO film 137
`is not patterned.
`A polysilicon film (not shown) is formed on the whole
`SiO film 137 to cover the whole substrate 101 and then, the
`polysilicon film is patterned to form gate electrodes 112 for
`the n- and p-channel MOSFETs in the peripheral NMOS and
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`PMOS regions 151 and 152. In this patterning process, the
`SiO film 137 is not patterned.
`The SiO film 137 is selectively etched using the gate
`electrodes 111 and 112 as a mask, thereby forming respec
`tive gate oxide films 107 and 108. The state at this stage is
`shown in FIG. 1E.
`Following this step, a SiO film (not shown) is formed on
`the uncovered main Surface of the Substrate 101 to cover the
`gate electrodes 111 and 112 by a CVD process. The SiO,
`film is then etched back by an anisotropic etching process,
`thereby forming Sidewall Spacers 113 at each side of the gate
`electrodes 111 and 112, as shown in FIG. 1F.
`An n-type impurity Such as arsenic (AS) is selectively
`ion-implanted into the p-type wells 104 and 106 while
`covering the peripheral PMOS area 152 by a mask. Thus, the
`n-type impurity is Selectively implanted into the p-type wells
`104 and 106 in self-alignment to the gate electrodes 111 and
`112, the sidewall spacers 113, and the isolation dielectric
`102.
`In the same way as the p-type wells 104 and 106, a p-type
`impurity Such as boron (B) is selectively ion-implanted into
`the n-type well 105 while covering the peripheral NMOS
`area 151 and the memory cell area 153 by a mask. Thus, the
`p-type impurity is Selectively implanted into the n-type well
`105 in self-alignment to the gate electrodes 111 and 112, the
`sidewall spacers 113, and the isolation dielectric 102.
`After an annealing process at a temperature of 800 to
`1000 C., n-type source/drain regions 114 are formed in the
`p-type well 104, p-type source/drain regions 115 are formed
`in the n-type well 105, and n-type source/drain regions 114
`are formed in the p-type well 106. The state at this stage is
`shown in FIG. F.
`Subsequently, as shown in FIG. 1G, a titanium (Ti) film
`116 with a thickness of approximately 50 nm is formed over
`the whole Surface of the Substrate 101. The Substrate 101
`with the Ti film 116 is subjected to a heat treatment in a
`nitrogen (N) atmosphere with a normal pressure at a
`temperature of 600 to 650 C. for 30 to 60 seconds using a
`heat treatment apparatus Such as a lamp annealing apparatus.
`Thus, nitrogen atoms are diffused into the Ti film 116 to
`thereby form a nitrogen-containing Ti film 119, as shown in
`FIG. 1H. At the same time as this, the single-crystal Si
`Source/drain regions 114 and 115 and the gate electrodes 112
`chemically react with the nitrogen-containing Ti film 119,
`resulting in titanium silicide (TiSi) films 117a and 117b due
`to a silicidation reaction. The TiSi films 117a are located at
`the surfaces of the source/drain regions 114 and 115. The
`TiSi films 117b are located at the surfaces of the gate
`electrodes 112.
`The TiSi films 117a and 117b, which has the C49 phase,
`has a comparatively high electric resistance of approxi
`mately 60 uS2 cm.
`After this heat treatment proceSS for Silicidation, the
`unreacted nitrogen-containing Ti film 119 is removed by a
`wet etching proceSS using a mixture of water Solutions of
`ammuonia (NH) and hydrogen peroxide (H2O). Thus, the
`TiS i films 117a and to 117b are selectively left on the
`Substrate 101, as shown in FIG. 1I.
`The substrate 101 with the TiSi films 117a and 11.7b is
`then Subjected to another heat treatment in a nitrogen (N)
`atmosphere with a normal pressure at a temperature of
`approximately 850 C. for approximately 60 seconds using
`a heat treatment apparatuS Such as a lamp annealing appa
`ratus. Thus, the TiSi films 117a and 117b having the C49
`phase are turned to have the C54 phase due to phase
`transition.
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`The TiSi films 117a and 117b having the C54 phase has
`a comparatively low electric resistance of approximately 20
`tuS2 cm.
`A thick SiO film 120 serving as an interlevel dielectric is
`formed to cover the whole surface of the substrate 101 by a
`CVD process. Then, the surface of the SiO film 120 is
`planarized by a Chemical Mechanical Polishing (CMP)
`process, as shown in FIG. 1J.
`Then, as shown in FIG. 1 K, via holes 123 are formed to
`penetrate through the SiO film 120 by using photolithog
`raphy and etching techniques to the Source/drain regions 114
`and 115 and the gate electrodes 111 and 112. Metallic plugs
`121 are filled in the via holes 123 to be contacted with the
`Source/drain regions 114 and 115 and the gate electrodes 111
`and 112 by a Selective growth process of a metal film.
`Finally, an aluminum (Al) film (not shown) is formed on
`the SiO film 120 and then, it is patterned to form wiring
`lines 122 to be contacted with the metallic plugs 121. Thus,
`the Source/drain regions 114 and 115 and the gate electrodes
`111 and 112 are electrically connected to the wiring lines
`122.
`Through the above-described proceSS Steps, the conven
`tional flush nonvolatile Semiconductor memory device is
`completed.
`AS Seen from FIG. 1 K, the n-type Source/drain regions
`114 having the silicide films 117a, the gate oxide film 107,
`the gate electrode 112 having the silicide films 117b, and the
`sidewall spacers 113 located in the peripheral NMOS area
`151 constitute an n-channel MOSFET 161 of the peripheral
`circuitry. The p-type Source/drain regions 115 having the
`silicide films 117a, the gate oxide film 107, the gate elec
`trode 112 having the silicide films 117b, and the sidewall
`spacers 113 located in the peripheral PMOS area 152
`constitute a p-channel MOSFET 162 of the peripheral cir
`cuitry. The n-type Source/drain regions 114 having the
`silicide films 117a, the gate oxide film 107, the gate elec
`trode 111, and the sidewall spacers 113 located in the
`memory cell area 153 constitute n-channel MOSFETs 163 of
`the memory cell array.
`With the conventional fabrication method of the flush
`nonvolatile semiconductor memory device shown in FIGS.
`1A to 1K, to improve the performance of the memory device
`while thinning the refractory silicide films 117a and 117b of
`the MOSFETs in the peripheral NMOS and PMOS areas 151
`and 152, there is the following problem.
`Specifically, when electrons are drawn out from the
`floating gates 108 to the source/drain regions 114 of the
`MOSFETs 163 in the memory cell area 153, the drawing
`Speed of the electrons need to be as high as possible. From
`this point of View, it is preferred that the doping concentra
`tion of the Source/drain regions 114 is Set as high as possible.
`In this case, however, there is a problem that refractory
`silicide tends to be difficult to be produced if arsenic (AS) is
`used as the n-type impurity for the Source/drain regions 114.
`This is because the Silicidation reaction is Suppressed by the
`arsenic impurity doped into the regions 114 and as a
`consequence, the nitriding reaction becomes Superior to the
`Silicidation reaction.
`There are two solutions to solve this problem. A first one
`of the Solutions is to decrease the doping (i.e., AS) concen
`tration of the Source/drain regions 114. A Second one of the
`Solutions is to increase the thickness of the Ti film 116,
`thereby Suppressing the competition or conflict between the
`nitriding and Silicidation reactions.
`With the first one of the Solutions, however, as disclosed
`in an article written by Y. Tang et al., IEEE ELECTRON
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`DEVICE LETTERS, Vol. 17, No. 11, pp 525-527, Novem
`ber 1996, the Fowler-Nordheim tunneling current becomes
`small. This lowers the drawing speed of the electrons from
`the floating gates 108, thereby delaying the operation Speed
`of the memory device.
`With the second one of the solutions, the TiSi films
`117aand 117b become thicker according to the thickness
`increase of the Ti film 116. Therefore, the shallow p-n
`junctions of the Source/drain regions 114 and 115 occurring
`due to the device miniaturization tendency approach the
`TiSi films 117a and 117b, resulting in increase of the
`current leakage. This means that the thickness increase of
`the Ti film 116 is contrary to the requirement to decrease the
`thickness of the TiSi, films 117a and 117b. Accordingly, the
`second one of the solutions is unable to be adopted for this
`purpose.
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`However, the Source/drain regions of the Second plurality of
`MOSFETs in the peripheral circuitry have the silicide films
`while the source/drain regions of the first plurality of MOS
`FETs in the memory cells have substantially no silicide
`films. Therefore, the sheet resistance of the Source/drain
`regions of the second plurality of MOSFETs is readily
`equalized to that of the first plurality of MOSFETs.
`Accordingly, the electric Sheet resistance of Source/drain
`regions of the second plurality of MOSFETs in the periph
`eral circuitry is able to be decreased to the desired low
`electric sheet resistance of Source/drain regions of the first
`plurality of MOSFETs in the memory cells without degra
`dation of the data writing Speed in the memory cells.
`This means that both of miniaturization and performance
`improvement of a Semiconductor device of this Sort is able
`to be realized.
`In a preferred embodiment of the device according to the
`first aspect of the present invention, each of the Second
`plurality of MOSFETs in the peripheral circuitry has a
`SALICIDE Structure.
`In another preferred embodiment of the device according
`to the first aspect of the present invention, the doping
`concentration of the Source/drain regions of the first plurality
`of MOSFETs in the memory cells is equal to 1x10'
`atoms/cm or higher and the doping concentration of the
`Source/drain regions of the second plurality of MOSFETs in
`the peripheral circuitry is lower than 1x10' atoms/cm.
`In still another preferred embodiment of the device
`according to the first aspect of the present invention, the
`peripheral circuitry includes a third plurality of MOSFETs
`of a Second conductivity type opposite to the first conduc
`tivity type, thereby forming a CMOS structure. Each of the
`third plurality of MOSFETs is equipped with source/drain
`regions having Silicide films and a doping concentration
`lower than that of the Source/drain regions of each of the first
`plurality of MOSFETs.
`In this embodiment, it is preferred that each of the third
`plurality of MOSFETs in the peripheral circuitry has a
`SALICIDE structure. Also, it is preferred that the doping
`concentration of the Source/drain regions of the third plu
`rality of MOSFETs is lower than 1x10' atoms/cm.
`According to a Second aspect of the present invention, a
`fabrication method of a Semiconductor device is provided,
`which is comprised of the following steps (a) to (g).
`In the step (a), a memory cell area in which nonvolatile
`memory cells are provided and a peripheral circuitry in
`which a peripheral circuitry is provided are defined on a
`Single-crystal Si Substrate.
`In the step (b), gate electrodes of a first plurality of
`MOSFETs for the nonvolatile memory cells are formed
`through gate insulating films in the memory cell area and
`gate electrodes of a second plurality of MOSFETs for the
`peripheral circuitry are formed through gate insulating films
`in the peripheral circuitry area.
`The gate electrodes of the first plurality of MOSFETs is
`equipped with floating gates for data Storing.
`In the step (c), dielectric Sidewall spacers are formed on
`the Substrate at each side of the gate electrodes of the first
`plurality of MOSFETs in the memory cell area and the gate
`electrodes of the second plurality of MOSFETs in the
`peripheral circuitry area.
`In the Step (d), a first impurity is selectively ionimplanted
`into the Substrate to form Source/drain regions of the first
`plurality of MOSFETs in the memory cell area and source/
`drain regions of the second plurality of MOSFETs in the
`
`SUMMARY OF THE INVENTION
`Accordingly, an object of the present invention to provide
`a Semiconductor device that makes it possible to decrease
`the electric sheet resistance of source/drain regions of MOS
`FETs in a peripheral circuitry without degradation of the
`data writing Speed in nonvolatile memory cells, and a
`fabrication method of the device.
`Another object of the present invention is to provide a
`Semiconductor device that copes with both of miniaturiza
`tion and performance improvement, and a fabrication
`method of the device.
`The above objects together with others not specifically
`mentioned will become clear to those skilled in the art from
`the following description.
`According to a first aspect of the present invention, a
`Semiconductor device is provided, which is comprised of
`nonvolatile memory cells and a peripheral circuitry provided
`on a same Semiconductor Substrate.
`The nonvolatile memory cells are formed by a first
`plurality of MOSFETs of a first conductivity type. The
`peripheral circuitry includes a second plurality of MOSFETs
`of the first conductivity type.
`Each of the first plurality of MOSFETs is equipped with
`a gate electrode having a floating gate for data Storing and
`Source/drain regions having Substantially no Silicide films.
`Each of the second plurality of MOSFETs is equipped
`with Source/drain regions having Silicide films and a doping
`concentration lower than that of the Source/drain regions of
`each of the first plurality of MOSFETs.
`With the semiconductor device according to the first
`aspect of the present invention, each of the Second plurality
`of MOSFETs of the first conductivity type in the peripheral
`circuitry have the Source/drain regions whose doping con
`centration is lower than that of the Source/drain regions of
`the first plurality of MOSFETs in the nonvolatile memory
`cells. Therefore, to raise the drawing Speed of the electrons
`from the floating gates to the Source/drain regions of the first
`plurality of MOSFETs in the nonvolatile memory cells (i.e.,
`the access speed to the memory cells), the doping concen
`tration of the Source/drain regions of the first plurality of
`MOSFETs can be increased as necessary.
`On the other hand, Since the doping concentration of the
`Source/drain regions of the second plurality of MOSFETs in
`the peripheral circuitry is lower than that of the Source/drain
`regions of the first plurality of MOSFETs in the memory
`cells, the electric sheet resistance of the Source/drain regions
`of the second plurality of MOSFETs is higher than that of
`the source/drain regions of the first plurality of MOSFETs.
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`peripheral circuitry area using the Sidewall Spacers and the
`gate electrodes of the first and second pluralities of MOS
`FETs as a mask.
`The source/drain regions of the second plurality of MOS
`FETs are lower in doping concentration than the Source/
`drain regions of the first plurality of MOSFETs.
`In the step (e), a first refractory metal film is formed to
`cover the first and second pluralities of MOSFETs.
`In the step (f), a Silicide film is formed on the Source/drain
`regions of the second plurality of MOSFETs by a silicidation
`reaction of the first refractory metal film with the source/
`drain regions of the second plurality of MOSFETs.
`Substantially no silicide film is formed on the source/
`drain regions of the first plurality of MOSFETs in the step
`(f).
`In the Step (g), the unreacted refractory metal film is
`removed.
`With the fabrication method of a semiconductor device
`according to the Second aspect of the present invention, as
`clearly Seen, the Semicondu