John Y. Chen
`I
`
`E
`
`E
`L
`
`F
`
`PRENTICE HALL, Englewood Cliffs, New Jersey 07632
`
`Micron Ex. 1014, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`CMOS DEVICES
`AND TECHNOLOGY
`FOR VLSI
`
`Micron Ex. 1014, p. 2
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Librmy of Congress Cataloging-in-Publication Data
`
`CHEN, JOHN Y.
`CMOS devices and technology for VLSI I John Y. Chen.
`p.
`em.
`
`Bibliography: p.
`Includes index.
`ISBN 0-13-138082-6
`1. Integrated circuits-Very large scale integration. 2. Metal
`I. Title
`oxide semiconductors, Complimentary.
`88-38557
`TK7874.C523 1990
`621.381'73-dc19
`CIP
`
`EditoriaVproduction supervision
`and interior design: BARBARA MARTIINE
`Cover design: DIANE SAXE
`Manufacturing buyer: MARY ANN GLORIANDE
`
`© 1990 by Prentice-Hall, Inc.
`A Division of Simon & Schuster
`Englewood Cliffs, New Jersey 07632
`
`The publisher offers discounts on this book when ordered
`in bulk quantities. For more information, write:
`Special Sales/College Marketing
`College Technical and Reference Division
`Prentice Hall
`Englewood Cliffs, New Jersey 07632
`
`All1ights reserved. No part of this book may be
`reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
`
`10 9 8 7 6 5 4 3 2 1
`
`ISBN
`
`0-13-138082-6
`
`PRENTICE-HALL INTERNATIONAL (UK) LIMITED, London
`PRENTICE-HALL OF AUSTRALIA PTY. LIMITED, Sydney
`PRENTICE-HALL CANADA INc., Toronto
`PRENTICE-HALL HISPANOAMERICANA, S.A., Mexico
`PRENTICE-HALL OF INDIA PRIVATE LIMITED, New Delhi
`PRENTICE-HALL OF JAPAN, INC., Tokyo
`SIMON & SCHUSTER ASIA PTE. LTD., Singapore
`EDITORA PRENTICE-HALL OF BRASIL, LTDA., Rio de Janeiro
`
`Micron Ex. 1014, p. 3
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`TE T
`
`PREFACE
`
`BIOGRAPHY
`
`1
`
`-·
`INTRODUCTION TO CMOS, THE VLSI
`TECHNOLOGY
`
`2 CMOS DEVICE PHYSICS
`2.1 ELECTRONS AND HOLES
`2.2 MOS CAPACITORS
`10
`2.3 MOS TRANSISTORS
`16
`2.4 BURIED CHANNEL DEVICES
`27
`2.5 SHORT- AND NARROW-CHANNEL EFFECTS
`
`6
`
`33
`
`3 MOS MODELLING
`3.1 MODELLING FOR CMOS TECHNOLOGY
`DEVELOPMENT
`38
`3.2 MODELS FOR INDIVIDUAL PROCESS MODULES
`3.3 MODELS FOR PROCESS INTEGRATION
`56
`3.4 TWO-DIMENSIONAL DEVICE MODELS
`61
`3.5 DEVICE PARAMETER EXTRACTION FOR CIRCUIT
`70
`STIMULATION
`
`41
`
`xi
`
`XV
`
`1
`
`5
`
`38
`
`vii
`
`Micron Ex. 1014, p. 4
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`viii
`
`4 CMOS OPERATION
`4.1
`INVERTERS
`92
`101
`4.2 A CMOS OUTPUT BUFFER
`4.3 TRANSMISSION GATE AS A SWITCH
`4.4 CMOS LOGIC GATES
`105
`4.5 DYNAMIC CMOS LOGIC
`106
`4.6 CMOS RAMS
`110
`
`103
`
`5 CMOS PROCESS TECHNOLOGY
`5.1 PROCESS ARCHITECTURE
`119
`5.2 P-WELL PROCESS
`122
`5.3 N-WELL PROCESS
`125
`5.4 P-WELL VERSUS N-WELL
`5.5 TWIN-TUB PROCESS
`128
`130
`5.6 RETROGRADE-WELL PROCESS
`5. 7 CHOICE OF PROCESS ARCHITECTURES
`5.8 SOS TECHNOLOGY
`136
`5.9 SOl TECHNOLOGY
`142
`5.10 BIPOLAR/CMOS INTEGRATION-BiCMOS
`
`127
`
`136
`
`149
`
`6 CMOS TRANSISTOR DESIGN
`6.1 MOSFET SCALING
`175
`176
`6.2 NON-SCALABLE DEVICE PARAMETERS
`6.3 TRANSISTOR DESIGN FOR SHORT-CIRCUIT
`MOSFETS
`182
`6.4 HOT CARRIER EFFECTS AND nMOS DESIGN FOR
`RELIABILITY
`183
`6.5 BURIED-CHANNEL EFFECTS AND pMOS
`DESIGN
`211
`
`7 CMOS ISOLATION
`7.1 BACKGROUND
`233
`7.2 MOS ISOLATION TECHNIQUES
`7.3
`ISOLATION IN CMOS
`249
`7.4 NEW ISOLATION TECHNIQUES FOR CMOS
`7.5
`ISOLATION DESIGN RULES IN CMOS
`277
`
`238
`
`272
`
`8 LATCHUP IN CMOS
`8.1
`INTRODUCTION
`285
`8.2 PHYSICS AND LUMPED CIRCUIT MODEL
`8.3 PARASITIC TRANSISTORS AND RESISTORS
`291
`8.4 LATCHUP CHARACTERIZATION
`
`286
`288
`
`Contents
`
`92
`
`119
`
`17 4
`
`233
`
`285
`
`Micron Ex. 1014, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Contents
`
`301
`8.5 AVOIDING LATCHUP
`8.6 LAYOUT CONSIDERATIONS
`317
`8.7 SUMMARY
`
`309
`
`9 CMOS DESIGN RULES
`323
`9.1 DESIGN RULES DERIVATION
`328
`9.2 LAMBDA-BASED DESIGN RULES
`9.3 LIMITATION OF LAMBDA RULES AND THEIR
`331
`MODIFICATIONS
`9.4 SUBMICRON DESIGN RULES AND THEIR IMPACTS
`334
`9.5 SUMMARY AND FUTURE PERSPECTIVES
`
`332
`
`LIST OF SYMBOLS
`
`INDEX
`
`ix
`
`323
`
`338
`
`343
`
`Micron Ex. 1014, p. 6
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`CMOS DEVICE
`HYSICS
`
`It should form the basis necessary for
`This chapter reviews MOS physics.
`CMOS device design and technology. This chapter uses a simple description
`and follows the logical development from semiconductor physics to MOS
`capacitors, MOS transistors, and finally some important effectsas transistors
`are shrunk for VLSI. Emphasis is placed on the differences between electrons
`and holes for the understanding of n-channel and p-channel transistors, which
`will be discussed in later chapters.
`This chapter starts with a discussion of mobility and impact ionization
`for electrons and holes because these two basic phenomena determine CMOS
`transistor performance such as current driving ability and ~ubstrate current.
`Ideal and non-ideal MOS capacitors are introduced and the definition of
`threshold voltage is presented. Next, aMOS transistor is described by con(cid:173)
`sidering two p-n junctions added to both sides of a MOS capacitor. The
`simple I-V relation in a, M OS field-effect transistor (M OSFET) is described
`and a discussion of its operations in linear, saturation and subthreshold regions
`In addition, buried-channel behaviors are discussed because one of
`follows.
`the two devices in a typical CMOS IC behaves this way. Short and narrow
`channel effects associated with small devices are also considered.
`
`5
`
`Micron Ex. 1014, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`6
`
`CMOS Device Physics
`
`Chap.2
`
`2.1 ELECTRONS AND HOlES
`
`In semiconductors, current c;onduction is caused by the movement of charged
`carriers.
`In an absolutely pure (intrinsic) semiconductor, say silicon (Si),
`electrons are negatively charged carriers which are created due to Si bond
`breakage caused by thermal vibration of the Si atoms. When an Si bond is
`broken, a free electron results, thus leaving a vacancy in the original bond
`(Fig. 2.1a). The vacancy is positively charged, and is referred to as a "hole".
`An electron can hop from one neighboring bond into the hole and cause
`another hole to occur. This current can be viewed as the movement of
`positively charged holes in the opposite direction. The free carrier (electron
`or hole) density in an intrinsic Si is defined as ni which is 1.45 x 1010 em 3
`at room temperature. 1
`
`Some bonds are broken:
`few conduction electrons
`and holes result
`
`1.!.1
`~
`:!) s i <L:::!) s i <!
`Extra hole:
`•
`~
`~ easy to remove
`
`~Si~B(!
`(i)
`(i)
`
`- - - - - -E c
`
`· - - - - - - - - E,.
`
`Acceptor --------------l!:....
`o o o o Ev--f.--
`
`IOns
`
`Ionization energy
`
`(b)
`
`0
`
`(a)
`
`1.!.1
`~
`:!) s i <!::=:!) s i <!
`
`~
`
`~ Extra electron:
`•
`/
`:!)Si~ P (!
`(i)
`(i)
`
`easy to remove
`
`Ionization energy
`_l_ !119999!!1!il9
`Ec
`~-++++++++- Donor ions
`- - - - - - - - - E,.
`
`------Ev
`(c)
`
`Figure 2.1 Schematic atomic structures and energy bands of: (a) intrinsic; and
`(b) extrinsic Si (Ref. 1).
`
`Micron Ex. 1014, p. 8
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.1
`
`Electrons and Holes
`
`7
`
`In a doped (extrinsic) semiconductor, electrons or holes can be gener(cid:173)
`ated by introducing impurity atoms such as phosphorus or boron into Si. The
`doped Si is then called n- or p-type respectively. Compared to Si, phosphorus
`or arsenic has one extra valence electron; this type of atom is called a donor
`impurity. Boron has one less valence electron, i.e., one hole in the Si lattice;
`this type of atom is called an acceptor impurity. The extra electron or hole
`can easily escape from the Si bond and become a free carrier responsible for
`It leaves the impurity atom ionized (Fig. 2.1b) in this
`current conduction.
`situation.
`Sufficient thermal energy exists at room temperature to ionize all the
`donor or acceptor impurity atoms in Si. As a result, the electron density (n)
`in ann-type Si is the same as the donor impurity concentration (N0 ), and
`the hole density (p) in a p-type Si is equal to the acceptor impurity concen(cid:173)
`tration (N A). Another way to create free electrons or holes is by applying
`a voltag~ to Si to bend the Si band to a degree that electrons or holes can
`It can be shown1 in any case, that np = n'f for semi(cid:173)
`be locally generated.
`conductors at equilibrium.
`For CMOS devices, the two most important properties of electrons and
`holes are carrier mobility and impact ionization.
`In a MOSFET, mobility
`affects the drain current and impact ionization determines the substrate cur(cid:173)
`rent. Moreover, these two properties are quite different for electrons and
`holes.
`
`2.1.1 Mobility
`
`When an electrical field is applied to a semiconductor, carriers (electrons
`or holes) are accelerated and also scattered by lattice vibration and impurity
`collision. Consequently, a constant carrier velocity defined as drift velocity
`results. The drift velocities for electrons and holes in Si are dependent on
`the electrical field as shown in Fig. 2.2. At a low field, the velocities are
`proportional to the electrical field, hence constant mobilities (t-t) can be de(cid:173)
`fined as the average velocities per unit electrical field (vi E). Notice that in
`Fig. 2.2a the electron mobility is about 3-4 times higher than the hole mobility
`at low field, i.e., E < 104 V/cm. This phenomenon has resulted in more
`drain current in ann-channel MOSFET than that in a correspondingp-channel
`device. However, at a large field (about 105 V/cm or above), electron and
`hole velocities approach a common asymptote as shown in Fig. 2.2b. 2 Thus,
`for short-channel MOSFETs in which carriers experience high electric field
`and approach saturated velocities, the difference in current between an n(cid:173)
`and a p-channel device decreases greatly.
`Although carrier mobility in bulk Si is a function of impurity doping
`concentration, 1 mobility of charges in a MOSFET channel is not dependent
`on impurity concentration unless the concentration is very large, NA > 1.0
`x 1017 em - 3 . 3 Experiments have verified this observation and shown only
`
`Micron Ex. 1014, p. 9
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`8
`
`CMOS Device Physics
`
`Chap.2
`
`4
`
`2
`
`Holes
`
`1.8 2x104
`
`If (vjcm)
`
`(a)
`
`-~
`
`E
`~
`>- 107
`1-
`u
`0
`...J w
`>
`1-
`1.1..
`0:: 106
`0
`a::
`w
`0::
`a::
`<l:
`<..:>
`
`/
`
`v
`
`~
`
`,
`
`-~ -
`
`/
`
`k'
`
`"
`
`"' "
`
`Si
`
`/
`
`/
`
`/
`
`/
`
`"
`
`=
`=
`T=300K
`ELECTRONS -
`-
`-----HOLES
`
`·.
`
`103
`
`104
`ELECTRIC FIELD (V/cm)
`
`105
`
`(b)
`
`Figure 2.2 Carrier drift velocities for Si in: (a) low electric fields (Ref. 1); and
`(b) a wide range of electric fields (Ref. 2).
`
`<5% difference in mobility values among a large range of doping levels. For
`commonly used channel doping levels, channel mobility fJ-ch is mainly a func(cid:173)
`It can be
`tion of the effective electric field normal to the Si surface. 3 ..+
`described empirically as5
`
`where fJ- 0 is the mobility at the electric field of Ecrit or lower. UEXP and
`
`IJ-ch = JJ.oC£crit/£eff)UEXP
`
`(2.1)
`
`Micron Ex. 1014, p. 10
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.1
`
`Electrons and Holes
`
`9
`
`Ecrit are constants obtained empirically. Channel mobility decreases as the
`effective electric field (Een) exceeds the critical field (Ecrit). Eerr is described
`in the discussion of MOSFET operation (see Section 2.3.2).
`
`2. 1.2 Impact Ionization
`
`When the electric field in a semiconductor is increased to 105 V/cm or
`above, electrons or holes gain enough energy to excite and generate electron(cid:173)
`hole pairs by impact ionization. The generation rate is given by
`
`where <X11 is the electron ionization rate defined as the number of electron(cid:173)
`hole pairs generated by an electron per unit distance traveled; aP is the hole
`
`(2.2)
`
`104
`
`103
`
`1 0 2
`
`I
`E
`u
`w
`1-
`<(
`a:
`z
`0
`i=
`<(
`N
`z
`0
`
`1.5
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7 8
`
`ELECTRIC FIELD (X 105 V /em)
`
`Figure 2.3 Measured ionization coefficient for avalanche multiplication vs. electric
`field for Si (Ref. 2).
`
`Micron Ex. 1014, p. 11
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`10
`
`CMOS Device Physics
`
`Chap.2
`
`ionization rate defined similarly; n and p are the electron and hole concen(cid:173)
`trations; and V 11 and vP are the thermal velocities for electrons and holes,
`respectively. The ionization rates in Si are strongly dependent on the elec(cid:173)
`trical field and can be defined as:
`
`3.8 X 106 exp ( -1.75 X 106/ £)
`
`2.25 x 107 exp ( -3.26 x 106/E)
`
`(2.3a)
`
`(2.3b)
`
`The ionization rates are shown in Fig. 2.3 for electrons and holes in Si at
`room temperature. 2
`6 They are known to decrease as the temperature in(cid:173)
`·
`creases. 7 The ionization rate for electrons is higher than that for holes by
`one-to-two orders of magnitude. This difference causes the substrate current
`in ann-channel MOSFET to be several orders of magnitudes higher than that
`in a p-channel device.
`
`2.2 MOS CAPACITORS
`
`The simplest device in MOS technology is the MOS capacitor, consisting of
`Metal (or other conductors such as doped polysilicon), Oxide and a Semi(cid:173)
`It is different from the capacitor made by
`conductor as shown in Fig. 2.4.
`two conducting parallel plates because the MOS capacitance is strongly de(cid:173)
`pendent on the voltage applied on the gate. Electron energy band diagrams
`
`Si substrate
`
`MOS Capacitor
`
`Figure 2.4 A MOS (Metal Oxide Silicon) capacitor.
`
`Micron Ex. 1014, p. 12
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.2
`
`MOS Capacitors
`
`11
`
`of MOS capacitors with a p-type and an n-type semiconductor are shown in
`Fig. 2.5 for three gate bias conditions. Ec and Ev are the conduction and
`valence band edges. Eh the intrinsic level, is at the middle of the energy
`band gap, i.e., Ei = (Ec + Ev)/2.
`It corresponds to the Fermi level of an
`intrinsic-type (i.e., undoped) semiconductor. For a doped semiconductor,
`the Fermi level is closer to the conduction band for an n-type semiconductor,
`but closer to the valence band for a p-type semiconductor.
`In equilibrium,
`the Fermi level (EF) is constant in all cases because no current conducts.
`Consider the p-type semiconductor first. If a negative voltage is applied
`on the gate (Fig. 2.5a), the band bends up causing majority carriers (holes
`In this accu(cid:173)
`in this case) to accumulate near the semiconductor surface.
`mulation mode, the MOS capacitor behaves just like a parallel-plate capacitor
`
`p- TYPE
`
`n -TYPE
`
`~--.;;.._Ec
`
`-------E·
`k-----E~
`+ + + • Ev
`
`::.--;;...;;;......;;....;;;...._ E c
`1'-----EF
`,......-----E,
`
`+
`
`+ Ev
`
`Ec
`-
`------Ei
`t - - - - - - - - E F
`+ + + + Ev
`+
`
`(b)
`
`;..-------...;;..-- Ec
`
`-----E1
`~----EF
`+ + + + Ev
`
`+
`
`(c)
`
`~-+~--:-+-E v
`
`~----....;-;... Ec
`~----EF
`- - - - -E,
`
`Figure 2.5 Energy band diagrams for ideal MOS capacitors for: (a) accumulation;
`(b) depletion; and (c) inversion (Ref. 2).
`
`Micron Ex. 1014, p. 13
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`12
`
`CMOS Device Physics
`
`Chap.2
`
`with a constant capacitance per unit area (cox)
`
`(2.4)
`
`If
`where Eox and fox are the dielectric constant and thickness of the oxide.
`a small positive gate voltage is applied (Fig. 2.5b), the band bends downward
`and the holes are pushed away from the surface, leaving a depletion region
`consisting of negatively charged acceptor ions.
`In this depletion mode, the
`MOS capacitor has two capacitances in series, the oxide capacitance (Cox)
`and the depletion capacitance( Cd). While Cox is constant
`
`(2.5)
`
`C>
`
`where d, the depletion width, increases as the gate voltage (Va) is increased.
`The corresponding bands are bent downward more and eventually the intrinsic
`level Ei at the surface crosses over the Fermi level E F (Fig. 2.5c). At this
`point, the semiconductor surface is inverted from p-type ton-type. Further
`increase of Vg will pull the bands down continuously until the Ei at the Si
`surface is one <P13 below Ep, where <P8 , bulk potential, is defined as (Ei - EF)
`in bulk Si. This condition is referred to as strong inversion and the corre(cid:173)
`sponding band diagram is shown in Fig. 2.6.
`Additional gate voltage will attract more electrons to the surface but
`will not widen the depletion region significantly. This instance holds true
`because once the onset of strong inversion has occurred, a marginal increase
`in a band bending due to the expansion of the depletion width results in a
`very large increase in the number of electrons within the inversion layer. 2
`Because the depletion region remains more or less unchanged after strong
`inversion is reached, a maximum depletion width (dmaJ can be defined. As
`shown in Fig. 2.6, the potential <Pis measured as the amount of band bending
`with respect to the intrinsic level (Ei) in bulk Si. At the semiconductor
`surface, <P = <Ps, and <Psis called the surface potential. Notice <Ps = 2<1> 13
`at strong inversion. Electron and hole concentrations can be expressed as
`(2.6a)
`
`n = ni exp(Ep - E)kT)
`
`p = ni exp(Ei - Ep/kT)
`Note that np = n? was previously described. At strong inversion, the elec(cid:173)
`tron concentration at the surface is equal to the hole (majority carrier) con(cid:173)
`centration in the bulk.
`In the strong inversion mode, the positive charges
`on the gate (Om) must be balanced out by the electrons at the inversion layer
`(012 ) and the negative charges in the depletion region (Q 13 )
`
`(2.6b)
`
`(2.7)
`
`where Q8 = - qNAdmax· The total capacitance is the oxide capacitance in
`series with the depletion capacitance at the maximum depletion width in
`equilibrium, i.e. cdmax = Ejdmax· The above discussion is for a p-type
`
`Micron Ex. 1014, p. 14
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.2
`
`MOS Capacitors
`
`13
`
`SEMICONDUCTOR
`SURFACE
`
`------------------------~------Ec
`
`---Ei
`
`INSULATOR
`
`Figure 2.6 Energy band diagram at the surface for a p-type semiconductor (Ref.
`2).
`
`semiconductor. Similar results can be obtained for ann-type semiconductor,
`however the polarity of the voltages and charges must be reversed.
`Fig. 2.7 shows the C-V characteristics of aMOS capacitor with a p-type
`substrate. The capacitance at negative voltages is constant and is equal to Cox
`because the device is in the accumulation mode. As the gate voltage (l/.,)
`approaches zero and becomes positive, three curves represent low-frequency
`(curve a), high-frequency (curve b) and pulse measurements (curve c).
`Consider the high frequency case first, i.e., curve (b). When a positive
`voltage is applied, holes are pushed away leaving a negatively charged de(cid:173)
`pletion region. At high enough frequencies, charge increment only occurs
`at the depletion edge. Thus, the depletion capacitor is in series with the
`oxide capacitor forming the MOS capacitance per unit area as
`
`(2.8)
`
`The higher the Vg, the larger the depletion width. And, from Eq. 2.5, C
`from Cd reduces as Vg is increased. Thus, the total capacitance, C, finally
`levels off because the maximum depletion width is reached. When the meas(cid:173)
`urement frequency is low (curve a), the generation-recombination rate can
`keep pace with the small AC signal variation. Hence, the minority carriers
`(electrons, in this example) can modulate the inversion charges at the sem(cid:173)
`iconductor surface. Consequently, the capacitance measured at inversion
`mode will be the oxide capacitance.
`
`Micron Ex. 1014, p. 15
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`14
`
`CMOS Device Physics
`
`Chap.2
`
`1.0~--------
`
`J
`' u
`
`0~------------------J-----L-----------~
`Vt
`0
`-v-
`-+v
`
`V9(VOLTS)
`
`Figure 2. 7 MOS capacitance-voltage curves. (a) Low frequency; (b) high fre(cid:173)
`quency; and (c) deep depletion (Ref. 2).
`
`For both low- and high-frequency cases, the DC-bias of the MOS system
`is swept at sufficiently low rates so that at least a quasi-equilibrium condition
`is maintained. However, if a voltage pulse is suddenly applied to the gate
`. (curve c), holes are pushed away immediately and all incremental charge
`appears at the edge of the depletion region. Sufficient time does not exist
`for the generation-recombination process to create minority carriers ( elec(cid:173)
`trons) at the surface and supply holes to neutralize ionized acceptors at the
`depletion edge. This condition is non-equilibrium and is often referred to
`as deep depletion, which is the operational condition for charge-coupled
`devices (CCDs).
`In this case, maximum depletion width cannot be defined.
`The gate voltage, however can be given as
`
`where the first term corresponds to the voltage across the oxide and the
`second term represents the voltage drop in the semiconductor. At the onset
`of strong inversion
`
`(2.9)
`
`(2.10a)
`
`(2.10b)
`
`And the gate voltage (Vg) at this condition is defined as the threshold voltage,
`Vt. From the above two equations, V 1 can be expressed as
`
`(2.11)
`
`This equation describes the threshold voltage for an ideal MOS capacitor,
`
`Micron Ex. 1014, p. 16
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.2
`
`MOS Capacitors
`
`15
`
`defined as aMOS capacitor that gives no band bending at zero gate voltage.
`However, it is often unrealistic in a non-ideal MOS capacitor. The difference
`between the work functions of a gate and a semiconductor can lead band
`bending at Vg = 0 V. The work function is defined as the minimum energy
`needed for an electron to escape from its Fermi level into vacuum.
`
`X;
`
`VACUUM LEVEL
`
`1x --------r--
`I
`
`V9 = 0
`
`¢se
`
`Eg/2
`1--...l--+-------l-- Ec
`
`AI
`
`p-type si
`
`(a)
`
`VACUUM LEVEL
`
`4>se
`
`AI
`
`p-Type Si
`
`(b)
`
`Figure 2.8 Energy band diagrams for: (a) an ideal MOS, i.e., no work function
`difference; and (b) a non-ideal MOS, i.e., with work function difference (Ref. 1).
`
`Micron Ex. 1014, p. 17
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`16
`
`CMOS Device Physics
`
`Chap.2
`
`To avoid band bending so that a flat-band condition can be achieved,
`an additional gate voltage must be applied to counterbalance the difference
`in work functions. Fig. 2.8 shows the energy band diagrams for an ideal
`MOS capacitor and an MOS capacitor with a work function difference bal(cid:173)
`anced by a non-zero flat-band voltage. <l>m is the work function of the metal
`gate and the work function for the· semiconductor is <~>se, which is equal to
`x + Eg/2 + <I> s for a p-type semiconductor. X is the electron affinity, defined
`as the energy difference between the conduction bend and the vacuum level.
`The charges in the oxide can induce an image charge in the semiconductor.
`Again, to obtain a flat-band condition, an opposite voltage must be applied
`to the gate. The total gate voltage needed to offset the work function dif(cid:173)
`ference and the oxide charge is called flat-band voltage and is given as
`
`(2.12)
`where <~>ms = <l>m - <l>m <l>m and <~>se are the work functions for the gate and
`the semiconductor, respectively, and Q1c is the fixed charge density of the
`oxide.
`The threshold voltage for a non-ideal MOS capacitor is then written as
`
`In practical device design and fabrication, a thin layer of charges is commonly
`introduced at the silicon surface to ad just threshold voltage in a way similar
`to the effect of Q1c in Eq. 2.13. This introduction is normally accomplished
`with ion implantation of boron or arsenic at a very low energy level. The
`ion implantation process is described in Chapter 3.
`
`(2.13)
`
`2.3 MOS TRANSISTORS
`
`The MOS capacitor discussed previously can be made into a transistor if two
`pin junctions are added at both.sides of the capacitor. Fig. 2.9 shows the
`schematic of an n-channel MOS field-effect transistor consisting of a MOS
`capacitor and two n + regions in a p-type Si substrate. It has four terminals:
`gate for the capacitor, source and drain for the two n +, and substrate (or
`body) for the p-substrate.
`The gate can be made by a layer of metal (aluminum is most common)
`or heavily-doped polysilicon. Today, polysilicon gates are commonly used
`because they allow the alignment of the two n + regions (source and drain)
`to the edges of the gate. This self-aligned feature cannot be achieved with
`an aluminum gate because of process incompatibility during fabrication.
`The two n + regions are isolated by the p-type substrate and no current
`can flow unless the surface of p-substrate is inverted by an adequate voltage
`being applied on the gate. At this point, an n-type inversion layer is formed,
`called an n-channel, connecting source and drain so that a positive voltage
`
`Micron Ex. 1014, p. 18
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.3
`
`MOS Transistors
`
`17
`
`Source ~
`
`+--Drain
`
`P-Sub
`
`0
`
`MOSFET
`
`Figure 2.9 AMOS Field Effect Transistor (FET).
`
`on the drain can attract electrons to flow from source to drain. The current
`starts to increase linearly with the drain voltage, but eventually saturates at
`a large drain voltage.
`
`2.3.1 Band Structure in Non-equilibrium
`
`Consider the band structure near the drain junction under the gate. At
`zero drain voltage (Vc~ = 0), only a built-in potential (VbJ exists between the
`p-n junction to counter-balance the diffusion force; the p-n junction is in
`equilibrium and the Fermi level is constant through the channel direction,
`i.e. y-axis. When a gate voltage (Vg) is applied with Vg > V,, the band
`bends 2<I>B (i.e., <I>s = 2<I>B) making the conduction band (Ec) closer to EF,
`resulting in surface inversion as described earlier. This instance is shown in
`Fig. 2.10a.
`Now, if a positive Vc~ is applied at then+ of the p-n junction, the reverse
`bias will create a larger potential barrier (Vbi + Vc~) across the p-n junction,
`thus lowering the quasi-Fermi level for electrons (EFn) by Vct and placing the
`system in non-equilibrium. Therefore the band bending is not enough to
`bring Ec near EFn to cause inversion (Fig. 2.10b ). Higher Vg must be applied
`to bend the band by (2<I>B + Vc~) and lower the Ec under the gate closer to
`E Fw Fig. 2.10( c) shows this condition. The gate voltage for inversion to
`occur in a MOSFET channel is now a function of Vc~.
`
`Micron Ex. 1014, p. 19
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`18
`
`CMOS Device Physics
`
`Chap.2
`
`(b)
`
`c/Js == vd + 2c~Ja (p-type)
`
`~
`
`(c)
`
`Figure 2.10 Energy band diagrams near the drain of a MOSFET with different
`gate and drain bias conditions; (a) Vg > V, Vd = 0, (b) Vg < V, (Vd), Vd > 0;
`and (c) Vg > V, (Vd), Vd > 0 (Ref. 1).
`
`Micron Ex. 1014, p. 20
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.3
`
`MOS Transistors
`
`19
`
`2.3.2 MOSFET Operation
`
`When a voltage greater than V 1 is applied to a gate, the semiconductor
`surface is inverted ton-type and a MOSFET channel is formed, as shown in
`Fig. 2.11. For small drain voltages, the entire channel is inverted and channel
`conductance is proportional to the inversion charges. This area is the linear
`region in which the drain current Ic~ is proportional to Vc~ and the FET acts
`as a resistor. As Vc~ increases and reaches a point such that (Vc~ + 2<1>8 ) is
`just larger than the band bending produced by the gate voltage, the inversion
`disappears at point X near the drain (Fig. 2.11b ). The channel is then pinched
`off at this point and the corresponding drain voltage is defined as Vdsat because
`for Vc~ > Vc~sau Ic~ remains essentially constant. As shown in Fig. 2.11(c),
`the additional voltage above Vdsat is consumed for widening the depletion
`region and the potential at Point X remains constant. Point X moves toward
`the source as Vd exceeds Vdsau but the movement is very slight; hence, Ic~
`increases very little. The drain current basically remains at a constant level,
`lc~san for Vc~ > Vc~sat· However, for a device with very short channel length,
`a slight movement of the pinchoff point can be a significant portion of the
`entire channel length, thereby causing significant increase of Idsat· Other
`short channel effects will be discussed in Sec. 2.5.
`
`Linear and saturation regions. This section derives the basic MOS~
`FET characteristics. If a MOSFET is biased with sufficient gate voltage to
`cause surface inversion, the free charge in the inversion layer at a distance y
`from the source is
`
`where Qs(Y) is the charge induced in the semiconductor per unit area at Point
`y. Because
`
`(2.14)
`
`(2.15)
`
`p
`
`(a)
`
`p
`
`(b)
`
`=
`
`p
`
`(c)
`
`Illustration of the operation of a MOSFET for V8 > V,: (a) Vd <<
`Figure 2.11
`Vdsat; (b) Vd = Vdsat; and (c) Vd > Vdsat (Ref. 1).
`
`Micron Ex. 1014, p. 21
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`20
`
`CMOS Device Physics
`
`Chap. 2
`
`where Vg' = vg - v FB' and
`OB(Y) = -qNAdmax = -Y2EsqNA[V(y) + 2<PB]
`Eq. 2.14 can also be written as
`2<PB - V(y)] + Y2EsqNA[V(y) + 2<PB]
`Qn(Y) = - Cox[Vg' -
`The voltage drop across an element, dy, along the channel is given by
`
`(2.16)
`
`(2.17)
`
`(2.18)
`Using the boundary condition of V = 0 at y = 0 and V = Vd at y = L, and
`Eqs. (2.17) and (2.18), the following I-V characteristics can be obtained
`w
`ld = L f-1n Cox
`
`{ ( Vg'- 2<l>s- ~d) Vr zv;~o:NA [(Vd + 2<1>s)312 - (2<I>e)312
`
`]}
`
`(2.19)
`
`Eq. (2.19) indicates that Id increases linearly with V{h then gradually levels
`off approaching saturation. The mobility f.A-11 in the above equation is not a
`constant, rather it is a function of the effective electric field as described in
`~ec. 2.1.1. The effective electric field (Eerr) is the electric field averaged
`It can also be expressed as
`over the electron distribution in the channel.
`Eeff = (QB + Q,/2)/Es
`= Cox(Vg - Vr]1(2Es)
`Substituting Eq. (2.20) into Eq. (2.1), the following is obtained
`f-A-n = f.lo{EsUcrit/ [Cox(Vg - Vr)]}UEXP
`
`(2.20)
`
`(2.21)
`
`Vd/2]Vc~
`
`(2.22)
`
`It is obvious that f.ln decreases as Vg is increased. Mo(cid:173)
`where· Ucrit is 2Ecrit·
`bility modelling for device and circuit simulation will be discussed in Chapter
`3, and the effect of scaling on mobility in Chapter 6.
`I-V curves with various Vgs are shown in Fig. 2.12, calculated based on
`Eq. 2.19 for Vd < Vdsat· The dashed line marks the locus of the saturation
`drain voltage (Vdsat), beyond which Id reaches its maximum and remains
`constant. For Vd < Vdsat' Eq. (2.19) can be approximated by
`ld = f.ln(WIL)Cox[(Vg - Vr)
`where V0 the threshold voltage, is given by
`vt = v FB + 2<PB + 'V2EsqNA(2<PB)/Cox
`For small Vc~s, Eq. (2.22) can be further reduced to
`for Vd << (Vg - Vr)
`
`ld =
`
`f.ln(W/L)Cox(Vg - Vr)Vd
`
`(2.23),
`
`(2.24)
`
`Micron Ex. 1014, p. 22
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`Sec. 2.3
`
`MOS Transistors
`
`21
`
`I n
`I
`v I
`LINEAR /
`I v
`'I /
`~ V;
`r ~ ~
`~
`~ v ll
`V;
`v/ ~ /
`~
`
`REGION
`
`...J
`......
`<.}
`::t..
`....... .,.
`
`H
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`I
`I
`I
`I "-( Vg - Vtl =10 VOLTS
`I
`I
`I
`
`9
`
`.
`
`I
`I
`I
`/,
`I
`I
`VI
`I
`I
`I'
`
`I
`
`SATURATION
`REGION
`
`8
`
`7
`
`6
`
`v-LOCUS OF ldsot vs Vdsat
`5
`
`I
`
`'
`
`I
`
`2
`
`4
`
`6
`
`8
`10
`Vd (V)
`
`4
`
`3
`
`2
`i
`
`12
`
`14
`
`16
`
`18
`
`Figure 2.12
`
`Idealized drain current vs. drain voltage of a MOSFET (Ref. 2).
`
`This equation can then be rearranged as
`
`for V,1 << (Vg - VJ
`
`(2.25)
`
`ld =
`
`(V 1 )]
`
`WLCa.JVt:- VJ
`Ll[
`d L
`JJ-n
`where the numerator represents the total charge stored in the MOS capacitor
`and the denominator corresponds to the charge transit time, which is equal
`to the channel length divided by the carrier velocity v,p where V11 =
`fJ- 11£ =
`fJ-11 Vc~l L. The M OSFET is now operated in the linear region and acts like a
`linear resistor. From Eq. 2.24, the threshold voltage can be approximated
`
`Micron Ex. 1014, p. 23
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`22
`
`CMOS Device Physics
`
`Chap. 2
`
`75.00
`
`7.500
`/div
`
`Slope cc
`
`J.l.n
`
`vd = 0.1 v
`
`.oooo~~---L~~--~--L-~---L--~--~~
`2.500
`.0000
`
`V9
`
`.2500/div
`
`( V)
`
`Figure 2.13 A typical experimental result of drain current (/d) vs. gate voltage
`(Vg) at a drain voltage (Vd) of 0.1 V.
`
`as the intercept of the ld vs. Vg plot for a small Vd (e.g., 0.1 V). A typical
`experimental result of an ld- Vg relation is shown in Fig. 2.13. The threshold
`voltage (Vr) is commonly measured by extrapolating the linear portion of the
`curve to the horizontal axis and the channel mobility (J.tn) is obtained from
`the slope of the dashed line. Notice a small but finite amount of current
`exists for Vgs which are slightly less V0 due to weak inversion. At strong
`inversion, i.e., Vg > V0 current is approximately linearly proportional to Vg.
`At a large Vd, the MOSFET is in a saturation region and Eq. 2.22 does not
`apply. Another way of obtaining threshold voltage is to define Vr as a gate
`voltage