(12) United States Patent
`Houston
`
`I 1111111111111111 11111 111111111111111 IIIII IIIII 1111111111 1111111111 11111111
`US006424016Bl
`US 6,424,016 Bl
`Jul. 23, 2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) SOI DRAM HAVING P-DOPED
`POLYSILICON GATE FOR A MEMORY PASS
`TRANSISTOR
`
`(75)
`
`Inventor: Theodore W. Houston, Richardson, TX
`(US)
`
`(73) Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`4,841,346 A * 6/1989 Noguchi ..................... 257/407
`4,888,631 A * 12/1989 Azuma ........................ 257/71
`5,164,805 A * 11/1992 Lee ............................ 257/407
`5,256,894 A * 10/1993 Shino ......................... 257/757
`5,714,771 A * 2/1998 Misawa ....................... 257/72
`5,740,099 A * 4/1998 Tanigawa
`................... 257/350
`
`FOREIGN PATENT DOCUMENTS
`* 5/1994
`
`6-151854
`
`JP
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`* cited by examiner
`
`(21) Appl. No.: 08/862,449
`May 23, 1997
`
`(22) Filed:
`
`Related U.S. Application Data
`( 60) Provisional application No. 60/018,300, filed on May 24,
`1996.
`Int. Cl.7 .............................................. H0lL 29/786
`(51)
`(52) U.S. Cl. ........................ 257/407; 257/296; 257/350
`(58) Field of Search ................................. 257/296, 350,
`257/348, 407, 71, 69, 68
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`3,673,471 A * 6/1972 Klein ......................... 257/407
`
`Primary Examiner-Jerome Jackson, Jr.
`(74) Attorney, Agent, or Firm-Wade James Brady, III;
`Frederick J. Telecky, Jr.
`
`(57)
`
`ABSTRACT
`
`An integrated circuit including a DRAM is disclosed,
`wherein the DRAM includes a memory array including a
`plurality of pass gate transistors and a plurality of memory
`elements. The pass gate transistors include a gate material
`selected to provide a substantially near mid-gap work func(cid:173)
`tion or greater. The DRAM also includes a peripheral area
`including a plurality of logic transistors. In a preferred
`embodiment the pass gate transistors are silicon-on-insulator
`transistors.
`
`23 Claims, 5 Drawing Sheets
`
`47
`
`46
`
`Si
`
`BOX
`
`SUBSTRATE
`
`38
`
`32
`
`30
`
`Micron Ex. 1006, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jul. 23, 2002
`
`Sheet 1 of 5
`
`US 6,424,016 Bl
`
`BL
`
`BL
`
`FIG. 1
`(PRIOR ART)
`
`J22
`I
`
`J22
`I
`-
`
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`
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`
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`
`/22
`I
`
`FIG. 2
`
`Si
`
`BOX
`
`SUBSTRATE
`
`FIG. 3
`
`32
`
`_WL
`
`✓22
`
`I
`
`36
`
`/ / / / / / / / / ; , , ,-
`
`, ' / / / / / / / / /
`
`////////,NITRIDE/////////
`
`/ / / / / / / / / , , , , , , / / / / / / / / /
`
`Si
`
`BOX
`32 1 - - - - - - - - - - - - - - - - - - - - ,
`RATE
`30
`
`Micron Ex. 1006, p. 2
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jul. 23, 2002
`
`Sheet 2 of 5
`
`US 6,424,016 Bl
`
`FIG. 4
`37
`33 , . - - - - - - - - -
`Si
`\--------------------,
`BOX
`
`D
`
`=== 11 OOA
`
`SUBSTRATE
`
`FIG. 5
`
`l 41
`
`BOX
`
`Si
`
`SUBSTRATE
`
`FIG. 6
`
`46
`
`Si
`
`BOX
`
`33
`
`30
`
`32
`
`SUBSTRATE
`30 L-------------------
`
`Micron Ex. 1006, p. 3
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jul. 23, 2002
`
`Sheet 3 of 5
`
`US 6,424,016 Bl
`
`10-3
`10-4
`10-5
`
`FIG. 7
`
`Vds=0 05V 2.5V
`
`:~=~ f
`
`Ids
`(AMPS) 1 o-8
`,o-9
`10-10
`10-11
`
`Lg=0.3um
`Wg=1um
`Tox=80A
`Tsi=614A
`p+gate
`
`10-12 1,v-, ..... - -
`10-13 '---l--"--!..-..___..__~_.......___~~~-~
`0.0 0.'.l 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
`Vgs (V)
`
`FIG. 8
`
`1.4
`
`Tox=80A
`Vds=0.05V
`t
`.
`.
`1 3 I
`1- p-. po1y go e
`
`1.2
`
`Vt(V) 1.1
`1.0
`
`0.9
`
`0.8 0.0
`
`FIG. 9
`
`,o-10
`
`10-15
`
`IOFF
`(A/um) ,o-20
`
`....._. T si= 614A
`G--EJ Tsi= 707A
`<r-----0 T si= 7 42A
`A--A T si=850A
`
`0.8
`0.6
`0.4
`0.2
`CHANNEL LENGTH ( urn)
`
`1.0
`
`oTsi=511A
`(cid:143) Tsi=614A
`
`0
`oo o o
`D
`
`0
`
`0
`
`oD
`
`Do (cid:143)
`
`0
`(cid:143)
`
`0
`
`D
`
`0.8
`0.6
`0.4
`0.2
`CHANNEL LENGTH (um)
`
`1.0
`
`,o-25
`
`Tox=80A
`Vds=2.5V
`p+poly gate
`,o-30 a.a
`
`Micron Ex. 1006, p. 4
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`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jul. 23, 2002
`
`Sheet 4 of 5
`
`US 6,424,016 Bl
`
`FIG. 10
`
`L3
`
`1.2
`
`1.1
`
`Tox=80A
`Vds=2.0V
`
`Vt (V)
`
`1.0
`
`0.9
`
`0.8
`
`0.7 0.0
`
`/>r--1,. Tsi=867A
`~+poly gate
`
`0.2
`
`0.6
`0.4
`CHANNEL LENGTH (um)
`
`0.8
`
`1.0
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`oTsi=600A
`(cid:143) Tsi=702A
`o Tsi=746A
`1::, Tsi=867A
`
`t:,
`
`g
`
`t:, t:,
`
`0 (cid:143)
`o(cid:144)
`
`t:,
`
`t:,
`
`(cid:144)
`(cid:143)
`
`(cid:144)
`
`(cid:143)
`0
`
`t:,
`(cid:144)
`(cid:143)
`
`t:,
`
`(cid:144)
`(cid:143)
`0
`
`n+poly gate
`
`I
`i
`
`t:,
`
`El
`
`Tox=80A
`Vds=0.05V
`
`0.0 0.0
`
`0.8
`0.4
`0.2
`0.6
`CHANNEL LENGTH (um)
`
`1.0
`
`10-6
`
`FIG. 1 1
`
`Vt (V)
`
`FIG. 12
`
`IOFF
`(A/um)
`
`,o-8
`
`,o-10
`
`10-12
`
`,o-14
`
`0
`
`Tox=80A
`Vds=2.5V
`
`ll ll
`
`e
`
`6
`
`(cid:144)
`e
`
`ll
`
`Q
`ll@~tl
`(cid:144)
`I:,.
`6 8
`oTsi=600A
`(cid:143) Tsi=702A
`o Tsi= 746A
`t1 Tsi=867A
`n+poly gate
`10 -16 .___......__ _ __.__ _ __..__~-~
`1.00
`0.80
`0.60
`0.40
`0.20
`0.00
`CHANNEL LENGTH (um)
`
`Micron Ex. 1006, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`U.S. Patent
`
`Jul. 23, 2002
`
`Sheet 5 of 5
`
`US 6,424,016 Bl
`
`FIG. 13
`
`10-2 .-----.--------.----,----,-----,
`10-3
`10-4 ---
`10 -5
`Vg-Vlh=2.5V
`10 - 5 Vd=2.SV - ·- - - - - -· -- -- --- -
`[s
`(A/um) 1 o --7
`Tox=80A
`Lg=OJum
`10 -8
`-9 Wg=l.Oum
`10
`-BULK
`1
`1 ~
`O ~--- PARTIALLY DEPLETED T si = 1100A 1
`10 -
`-11
`--FULLY DEPLETED, Tsi=614A WITH p-:-gu_ie
`10
`,o-12 - - · - -~ -~ -~~ - ' -
`0.0
`1.5
`2.0
`0.5
`1.0
`Vs (V)
`
`I
`
`I
`
`I
`
`I
`
`2.5
`
`FIG. 14
`
`CHARGE (C)
`
`7e-14
`
`6e-14
`
`5e-14
`
`4e-14
`
`3e-14
`
`2e-14
`
`1e-14
`
`/
`1
`I I
`I I
`I I
`l I
`,. /
`,,,
`Oe+OO ----....=-"'--'-------'----'----'---L.-----l
`10-13 10-12 10-1110-10 10-9 10-8 10-7 10-6
`TIME (sec)
`
`-BULK
`---- PARTIALLY DEPLETED,
`---:-----
`/,,,,, -------
`Tsi~1 iOOA
`,, ,,,,
`-- FULLY DEPLETED, ~,,,
`Tsi=614A WITH
`/
`p+gate
`//
`
`'I / /
`
`Vg-Vth=2.5V
`Vd=2.5V
`Tox=BOA
`Lg=0.3um
`Wg=1.0um
`
`FIG. 15
`
`100.0
`
`Tox=80A
`Lg=0.3um
`90.0 Vd=2.5V
`
`CHARGING
`EFFICIENCY (%)
`
`80.0
`
`70.0
`
`G--0 BULK
`G---fJ PARTIALLY DEPLETED,
`Tsi=1100A
`A-A FULLY DEPLETED,
`Tsi=614A
`
`60.02.0
`
`2.2
`
`2.6
`2.4
`Vg-Vth (V)
`
`2.8
`
`3.0
`
`Micron Ex. 1006, p. 6
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`
`

`

`US 6,424,016 Bl
`
`1
`SOI DRAM HAVING P-DOPED
`POLYSILICON GATE FOR A MEMORY PASS
`TRANSISTOR
`
`2
`There are different types of SOI transistors, and the choice
`of the SOI transistor type will affect the SOI DRAM
`performance. SOI transistors can be classified as fully
`depleted or partially depleted. Some SOI transistors may
`5 also be classified as nearly fully depleted. These are filly
`depleted when on and partially depleted when off. For a
`given channel doping, SOI transistors go from partially
`depleted to fully depleted as the silicon film thickness is
`thinned. The partially depleted transistor characteristics,
`10 including determination of threshold voltage, are very much
`like bulk transistors except for the floating body effects.
`Fully depleted transistors have some unique characteristics,
`and have reduced floating body effects. For filly depleted
`transistors, the range of threshold voltage is limited by the
`15 gate work function and silicon film thickness. As the channel
`doping is increased to increase the threshold voltage, the
`transistor transitions from fully depleted to partially
`depleted. There is an upper limit of threshold voltage for
`fully depleted SOI transistors for a given silicon film thick-
`20 ness and gate work function. For logic, it has been proposed
`to use a mid band-gap work function to raise the threshold
`voltage of both n and p-channel transistors. Polysilicon gate
`with "opposite" doping (p type for n-channel and n type for
`p-channel) has also been proposed combined with accumu-
`25 lation transistor mode design to get suitable threshold volt(cid:173)
`ages for logic or SRAM circuits.
`In addition to the difficulty of selecting desirable thresh(cid:173)
`old voltage, fully depleted transistors suffer from higher
`source/drain resistance because of the thinner silicon film.
`30 This is particularly true when silicide is used since there is
`high contact resistance if the silicide consumes the fill
`silicon film thickness. For these reasons most commercial
`work on SOI, including work on SOI DRAM, has empha(cid:173)
`sized partially depleted transistors.(See H. S. Kim et al. 1995
`35 Synmposium on VLSI Technology Digest of Technical
`Papers pp. 143, 1995)
`For SOI DRAM, the thinner silicon film associated with
`fully depleted or near fully depleted transistors has several
`advantages. These include a smaller junction area leading to
`smaller junction leakage and smaller junction capacitance.
`The thinner silicon film also provides a smaller volume for
`charge generation from ion strikes. The fully depleted tran(cid:173)
`sistor also has reduced floating body effects that can increase
`leakage in pass transistors and lead to variation of threshold
`voltages which would be deleterious to sense amplifiers.
`Further, the higher series resistance of filly depleted tran(cid:173)
`sistors is not significant in the DRAM array, especially since
`silicide is generally not used. However, the threshold voltage
`of a fully depleted n-channel SOI transistor with n-poly gate
`is too low for DRAM pass transistor application.
`
`This application claims priority from Provisional appli(cid:173)
`cation Ser. No. 60/018,300, filed May 24, 1996.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a the design of DRAMs using
`Silicon on Insulator (SOI) technology and more particularly
`to the design of fully depleted memory pass transistors in the
`DRAM in combination with a P-doped polysilicon gate.
`2. Description of the Prior Art
`SOI is good for DRAM for several reasons. One reason is
`that SOI has lower collection volume for charge generated
`by an alpha particle or a cosmic ray. Such charge can upset
`the memory cell, so the smaller collection volume of SOI is
`desirable. SOI also reduces the capacitance on the bit line so
`less charge is needed to generate an equivalent signal on the
`bit line relative to bulk DRAM. Also reduced junction area
`in the memory cell should give lower leakage which trans(cid:173)
`lates to longer retention time. All these features, lower
`collection volume, lower leakage and lower capacitance, are
`advantages of SOI.
`There are also potential difficulties in using SOI for
`DRAM. These include cost, yield, and floating body effects.
`SOI wafers cost more than bulk silicon wafers so it is
`important to keep the SOI processing cost low. Yield on SOI
`wafers is expected to improve as the material quality con(cid:173)
`tinues to be improved. Floating body effects can improve
`performance for logic circuits, but can also amplify collected
`charge ( as from alpha particle strikes) or increase leakage
`currents. So there is a need for a low cost SOI process with
`reduced floating body effects.
`The basic memory cell in a DRAM is a pass and a storage
`element (capacitor). The full DRAM includes an array of
`memory cells, and peripheral circuitry to control storage and
`retrieval of data into and from the memory array. The
`DRAM may be included with other circuitry in an integrated 40
`circuit. The process for a DRAM must encompass the
`requirements for the memory array pass gate and the periph(cid:173)
`eral transistors. The requirements for the pass gate transistor
`distinguish the design of transistors for DRAMs from logic
`or SRAMs. The pass gate must have very low leakage. This 45
`requires relatively high threshold voltage. It is also desirable
`for the pass gate transistor to have low source capacitance to
`help keep the bit line capacitance low. For charge transfer,
`it is usual to have a boosted word line voltage, which leads
`to thicker gate oxide for reliability. The pass gate transistor 50
`does not need to have high drive current. The pass gate
`transistor is usually N channel with an N doped polysilicon
`gate. There are some advantages to N polysilicon and the N
`channel has higher drive because of the higher mobility of
`electrons.
`Peripheral transistors have requirements similar to stan(cid:173)
`dard logic transistors. They generally will be designed with
`lower V r than the pass transistor.
`But to reduce cost, it is usual to have the peripheral
`transistor with the same gate oxide and single N polysilicon 60
`that is used for the pass transistor. Also, silicide is not used
`to reduce cost.
`Thus the design requirements for the peripheral transistor
`of a DRAM also may be different from the usual design
`requirements for standard logic. Nevertheless, we will some- 65
`times refer to the DRAM peripheral transistors as logic
`transistors.
`
`55
`
`SUMMARY OF THE INVENTION
`
`It is therefore a general object of the present invention to
`design an SOI pass transistor for a DRAM that has a high
`threshold voltage and reduced floating body effects.
`It is a further object of the present invention to integrate
`the above DRAM pass gate transistor with peripheral tran(cid:173)
`sistors with suitable characteristics.
`These and other objects of the invention will become
`apparent to those of ordinary skill in the art having reference
`to the following specification, in conjunction with the draw(cid:173)
`ings.
`In this invention, the gate material is chosen to have a
`higher work function to increase the threshold voltage of the
`DRAM array pass transistor relative to the use of n-poly for
`n-channel transistors. This reduces the floating body induced
`
`Micron Ex. 1006, p. 7
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`

`15
`
`3
`leakage under dynamic conditions. This also allows the use
`of fully depleted or nearly fully depleted transistors in the
`array. These can be combined with fully depleted transistors
`in the periphery. Alternatively, a different thickness silicon
`film can be used in the array verses in the periphery, such as 5
`by selective thinning, to allow fully depleted transistors in
`the array and partially depleted transistor in the periphery.
`The use of SOI transistors in the array and bulk transistors
`in the periphery is also possible.
`In a preferred embodiment the pass transistors are fully 10
`depleted P channel transistors operating in the inversion
`mode with N type polysilicon gates. The periphery has fully
`depleted P channel accumulation mode transistors with N
`doped polysilicon gates and fully depleted N channel inver(cid:173)
`sion mode transistors also with N type polysilicon gates.
`In another embodiment, the pass transistors are fully
`depleted N channel inversion mode transistors with P type
`polysilicon gates, wherein the periphery transistors are fully
`depleted N channel accumulation mode transistors with P
`type polysilicon gates in addition to filly depleted P channel 20
`inversion mode transistors also with P type polysilicon
`gates.
`In another embodiment, the pass transistors are fully
`depleted P channel inversion mode transistors with N type
`polysilicon gates. The peripheral transistors are partially
`depleted P channel inversion mode transistors with N type
`polysilicon gates in addition to partially depleted N channel
`inversion mode transistors with N type polysilicon gates.
`The pass transistors are made with thinner silicon film than
`the peripheral transistors. Optionally some of the peripheral
`transistors such as in the sense amps may also be fully
`depleted.
`In yet another embodiment the silicon insulator and bulk
`transistors are used on the same integrated circuit. This
`would be done with masked SIM OX or by other techniques,
`such as epitaxial lateral overgrowth. Here the transistors in
`the array would be made fully depleted with SOI and the
`peripheral transistors would be fabricated in bulk silicon.
`Selectively, some of the peripheral transistors could also be
`put on SOI.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an illustration of a prior art DRAM memory
`array;
`FIGS. 2-4 show a process flow for arriving at a SOI
`structure having a thinner silicon area in the array area than
`in the periphery area;
`FIG. 5 shows one preferred embodiment of the current
`invention;
`FIG. 6 shows an alternate preferred embodiment of the
`current invention;
`FIG. 7 shows the I-V characteristics of a fully depleted
`SOI DRAM pass transistor;
`FIG. 8 shows the linear threshold voltage of SOI DRAM
`pass transistors with various starting SOI film thicknesses.
`FIG. 9 shows the subthreshold leakage current, Ioff, of
`SOI DRAM pass transistors on two different starting SOI
`films;
`FIG. 10 shows the saturation Vth of SOI DRAM pass
`transistors with various starting SOI film thicknesses;
`FIG. 11 shows the linear Vth of SOI DRAM pass tran(cid:173)
`sistors with various starting SOI film thicknesses;
`FIG. 12 shows the subthreshold leakage current, Ioff, of
`SOI DRAM pass transistor swith various staring film thick(cid:173)
`nesses;
`
`US 6,424,016 Bl
`
`4
`FIG. 13 shows the channel current as a function of source
`node voltage for bulk and SOI DRAM pass transistors;
`FIG. 14 shows the charging characteristics of a 25 fF
`capacitor for bulk and SOI DRAM pass transistors; and
`FIG. 15 shows the charging efficiency as a function of
`gate voltage for bulk and SOI DRAM pass transistors.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`FIG. 1 is a typical DRAM memory array which shows a
`separate pass transistor 20 associated with each memory cell
`22. Word lines WL and bit lines BL are also attached to each
`pass transistor 20 in a known manner. In addition to the
`memory array as shown in FIG. 1 each DRAM also has
`peripheral area outside the memory array. The peripheral
`area includes various logic circuits including for example
`address decoding circuits, wordline drivers, sense
`amplifiers, and input/output circuits.
`FIGS. 2-4 illustrate a process flow for a silicon on
`insulator (SOI) structure wherein the silicon layer is thinner
`in the memory array area than it is in the peripheral area of
`the DRAM. In FIG. 2, the first step is to provide a silicon(cid:173)
`on-insulator structure comprised of silicon layer 33 on an
`25 oxide layer 32 which is on a substrate 30. This SOI structure
`can be fabricated in any of a variety of known processes
`such as bonding with etch back, SIMOX, or epitaxial lateral
`overgrowth. The thickness of silicon layer 33 is desired to be
`approximately 60 nm or greater to provide for partially
`30 depleted transistors in the periphery area. A nitride layer 35
`on top of a pad oxide layer 34 is used to mask the periphery
`area from the array area. As shown in FIG. 3, the exposed
`array area is oxidized to form SiO2 layer 36. The SiO2 layer
`36, the nitride mask 35 and pad oxide 34 are removed
`35 leaving the structure shown in FIG. 4. The silicon in the
`memory array area has been selectively thinned to provide
`a thickness ts; of approximately 30-80 nm This thickness
`should provide for fully depleted pass transistors in the
`memory array area upon further processing. Alternate means
`40 of obtaining seletively different silicon film thickness for
`pass and periphery transistors include the use of selective
`epi, and bonding with a selectively contoured device wafer.
`For the latter, various means of contouring can be used,
`including selective oxidation and etching. Use of bonding
`45 with a selectively contoured device wafer has the advantage
`of presenting a substantially planar surface for subsequent
`processing. (See U.S. Pat. No. 5,436,173).
`As shown in FIG. 5, after processing of the SOI structure,
`with thinned silicon for fully depleted transistors in the array
`50 area, a plurality of pass transistors 40 and 41 are formed in
`the array area and a plurality of logic transistors 42 and 43
`are formed in the periphery of the DRAM. Selected periph(cid:173)
`eral transistors may also be formed in areas of thinner
`silicon. The plurality of transistors 41 and 42 are formed in
`55 accordance with normal processing except that p-doped
`polysilicon is used in the gate material of then-channel pass
`transistors in the array area instead of n doped polysilicon of
`the prior art. The p-doped polysilicon gate material is chosen
`to have a higher work function than the standard n-doped
`60 polysilicon gate for the n-channel pass transistor. For
`p-channel pass transistors, an n-doped polysilicon doped
`gate material would be used to provide the higher threshold
`voltage.
`Instead of using the p-doped polysilicon gate material, a
`65 metal such as tungsten or titanium nitride (having a near
`mid-gap work function) could be chosen to give a higher
`gate threshold voltage for the pass transistor, than the prior
`
`Micron Ex. 1006, p. 8
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`US 6,424,016 Bl
`
`5
`
`6
`(2) n-channel periphery transistors: fully depleted tran(cid:173)
`sistors with 3E16 n type doping in channel.
`(Accumulation mode, Vt=--0.SV)
`(3) p-channel periphery transistors: partially depleted
`transistors with 6El 7 n type doping in channel. (Vt=
`--0.SV)
`As stated above, it is possible to have fully depleted pass
`transistors in the array and partially depleted logic transis(cid:173)
`tors in the periphery using different silicon film thicknesses.
`10 Another option is to use different gate materials. An example
`of this is as follows:
`
`Fourth example
`
`5
`art. Multilayer gate material may be used to get the desired
`work function combined with other desired characteristics.
`For example, p-doped polysilicon may be layered with
`tungsten to reduce resistance, or TiN may be layered with
`n-doped polysilicon.
`With the SOI structure shown in FIG. 5, the silicon layer
`37 in the array area could be either fully depleted or partially
`depleted depending on the exact doping and Si film thick(cid:173)
`ness ts;• It is preferable to use a thin silicon film (less than
`80 mm) for reduced junction area, leading to a fully depleted
`channel for the pass gate transistors of the array area.
`For optimal performance of the pass transistors in the
`array area and the logic transistors in the periphery, different
`gate material and/or different film thickness could be used in
`the array vs. the periphery, as illustrated in FIG. 5 and 15
`discussed above. This is because the transistors in both areas
`can be optimized independently.
`However, for optimal processing efficiency, the same gate
`material and film thickness ts; would be used for both the
`array area and periphery to reduce cost. An SOI structure
`with a plurality of pass transistors 45 and 46 in the array area
`and a plurality of logic transistors 47 and 48 in the periphery
`of the DRAM is shown in FIG. 6. One less lithography step
`would be required to produce the SOI structure in FIG. 6 as 25
`compared to the SOI structure of FIG. 5 due to uniform layer
`38 providing a uniform silicon film thickness ts; for all
`transistors throughout the DRAM device. Following are
`three examples of a DRAM having a uniform silicon chan(cid:173)
`nel thickness ts; of 60 mm, in accordance with FIG. 6, 30
`wherein the pass and periphery transistors use n-doped
`polysilicon gates for all transistors in the first example and
`p-doped polysilicon gates for all transistors in the second
`and third examples given below.
`
`20
`
`Uniform thickness for Silicon channel: 60 nm
`(1) Pass transistors: fully depleted p-channel transistors
`having n-doped poly gates with lEl 7 n type doping in
`channel. (Vt=--1.2V)
`(2) n-channel periphery transistors: partially depleted
`transistors having n-doped poly gates with 6El 7 p type
`doping in channel. (Vt=-0.SV)
`(3) p-channel periphery transistors: partially depleted
`transistors having p-doped poly gates with 6El 7 n type
`doping in channel. (Vt=--0.SV)
`It should be recognized that the above examples were
`given knowing that the devices can be optimized with
`channel profiling and source/drain engineering. Therefore,
`the invention is not intended to be limited to the above
`examples.
`The p-channel pass transistor has an advantage relative to
`the n channel pass for SOI because of the lower parasitic
`bipolar gain for a p-n-p structure vs a n-p-n structure. Also,
`if opposite gate doping is used (n-poly for p-channel or
`p-poly for n-channel) the n-poly gate of the p-channel pass
`35 transistor has the advantage of lower resistance. Further, as
`gate oxides are thinned, n-poly will have an advantge of not
`needing to be concerned with boron penetration through the
`gate oxide as would be the case for p-poly.
`
`40
`
`Experimental Results
`
`Both partially and fully depleted pass transistors were
`designed and fabricated on SIMOX substrates. Using a p+
`gate design, V,h=l V and I0_u<l fNmm was achieved for ultra
`45 thin film SOI pass transistors. With less than 1 fNmm
`off-state leakage design, the SOI pass transistor should
`provide excellent DRAM cell retention time and low stand(cid:173)
`by power. In addition, the SOI pass transistors were found to
`have a high DRAM charging efficiency (>80% for partially
`50 depleted devices and >95% for fully depleted devices) than
`the bulk pass transistor (80%) because of the elimination of
`the body effect. The higher charging efficiency allows SOI
`pass transistors to reduce the wordline voltage during the
`charging state, increase the gate oxide integrity and decrease
`55 the active power.
`V,h design of the Pass Transistors
`
`FIG. 7 shows the I-V characteristics of a fully depleted
`SOI DRAM pass transistor with p+ gate design. The Vth
`60 implant was BF2, 40 Ke V, 8Ell dose. The LDD implant was
`As, 40 Ke V, 3El 4 dose and the p+ gate was formed by 10
`Ke V, 3E15 dose Boron implant and annealed during the
`junction sequence. FIG. 8 shows the linear V,h of DRAM
`pass transistors for various SOI film thicknesses using
`65 p+gate design. The Vth implant for all the transistors is BF2,
`40 KeV, 1E12 dose and the LDD implant is As, 40 KeV,
`4E13 dose, and the channel width is 1.0 um. The subthresh-
`
`First example
`
`Uniform thickness for Silicon channel: 60 mm Single gate
`material: n+polysilicon
`(1) Pass transistors: fully depleted p-channel transistors
`with lEl 7 n type doping in channel. (Vt=--1.2V)
`(2) n-channel periphery transistors: partially depleted
`transistors with 6El 7 p type doping in channel. (Vt=
`-0.SV)
`(3) p-channel periphery transistors: fully depleted tran(cid:173)
`sistors with 3E16 p type doping in channel.
`(accumulation mode, Vt=--0.SV)
`
`Second example
`
`Uniform thickness for Silicon channel: 60 mm Single gate
`material: P+polysilicon
`(1) Pass transistors: fully depleted n-channel transistors
`with lEl 7 p type doping in channel. (Vt=-1.2V)
`(2) n-channel periphery transistors: fully depleted tran(cid:173)
`sistors with 3E16 n type doping in channel.
`(Accumulation mode, Vt=-0.SV)
`(3) p-channel periphery transistors: partially depleted
`transistors with 6El 7 n type doping in channel. (Vt=
`--0.SV)
`
`Third example
`
`Uniform thickness for Silicon channel: 60 mm Single gate
`material: p+polysilicon
`(1) Pass transistors: fully depleted n-channel transistors
`with 1E16 n type doping in channel. (Accumulation
`mode, Vt=-0.8V)
`
`Micron Ex. 1006, p. 9
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`US 6,424,016 Bl
`
`7
`old leakage current, I 0ff, at V as=2.5V of these transistors is
`shown in FIG. 9. As shown in the FIG. 8, the V,h of the
`transistors is 1.1-1.2V and does not change significantly as
`the SOI film thickness varies. The short channel effect on
`these transistors is also very small, due to the thin SOI film
`thicknesses. The leakage current I at V as=2.5V is below 1
`fNmm, which would improve the retention of the DRAM
`cell and reduce the stand-by power significantly. In the
`saturation condition, the V,h roll-off is larger and is a
`function of the SOI film thicknesses, shown in FIG. 10. For 10
`a comparison, all the n+ gate design n-channel transistors
`have V,h below 0.6 V and I0ffis on the order of nNmm. FIG.
`11 and FIG. 12 show the V,h and I 0 ff of n+ gate transistors
`as a function of SOI film thicknesses. As the SOI film
`thickness is larger than 60 mm, the sub threshold slope of the 15
`devices at V as=2.5V is less than 70 m V/dec which is an
`indication that the devices are partially depleted.
`It is commonly considered a draw back of fully depleted
`SOI that the Vt depends on Si film thickness, adding another
`source of Vt variation. But with the very low channel doping 20
`with opposite gate type, this variation is very small. Further,
`the variation of Vt with temperature is smaller for fully
`depleted SOI than for partially depleted or bulk.
`
`Charging characteristics of the Pass Transistors
`The bulk pass transistors suffer from the increase in Vt
`threshold voltage caused by the body effect during the
`capacitor charging state, so the wordline voltage has to be
`boosted to VwL=V,h+Vas+_V, where _V compensates for
`the V,h increasing during the charging. Reducing the body
`effect becomes a major issue in bulk pass transistor design.
`On the other hand, the body potential of the partially
`depleted SOI transistors will follow the source node poten(cid:173)
`tial during the charging because of the floating body effect,
`so that the body to source potential difference is kept at a 35
`substantially constant value. For fully depleted SOI
`transistors, there is no body potential change since the
`channel is filly depleted through the entire silicon-filmed
`thickness. Therefore, the SOI transistors will have a higher
`charging efficiency compared to the bulk transistors. FIG. 13 40
`shows the channel current as a function of source node
`voltage for the bulk and SOI transistors. If the charging
`current is designed to be 1 mNmm, then the charging
`efficiency, defined as the ratio of source voltage at 1 mm to
`the drain voltage (the bitline voltage), the charging effi- 45
`ciency is 80% for bulk transistors and 88% and 98% for
`partially and fully depleted SOI transistors, respectively. The
`higher charging efficiency of SOI shows charging charac(cid:173)
`teristics of a 25 fF capacitor. The bulk transistor shows a
`faster charging at below 0.1 ns due to its higher initial 50
`current. The SOI transistors show faster charging character(cid:173)
`istics for time greater than 0.1 ns. The fully depleted SOI
`transistor can charge ten times more charge than bulk
`transistor at 1 ns, which is the typical charging time for a
`DRAM cell. For the bulk pass transistors to reach the same 55
`charging efficiency as SOI transistors, one has to increase
`the wordline voltage during the charging. FIG. 15 shows the
`charging efficiency as a function of gate voltage for the bulk
`and SOI DRAM pass transistors. To reach 90% charging
`efficiency, the gate voltage of the bulk transistor has to be 0.6 60
`V higher than that of thin film SOI transistors. The increased
`wordline voltage will worsen the gate oxide integrity and is
`also not favorable for the low power operation.
`In summary, we have demonstrated a p+ gate SOI DRAM
`pass transistor design on ultra thin SOI films which has 65
`below 1 fA/mm subthreshold leakage current. In addition,
`we have shown that the fully depleted SOI pass transistors
`
`8
`have higher charging efficiency compared to bulk pass
`transistors. The higher charging efficiency allows SOI pass
`transistors to reduce the wordline voltage during the charg(cid:173)
`ing state and increase the gate oxide integrity. By using a p+
`5 gate design for the pass transistors of the DRAM, we have
`achieved less than 1 fA/mm of subthreshold leakage current
`on ultra thin SOI film thicknesses ranging from 400A to
`800A.
`While the invention has been shown and described with
`respect to particular embodiments, it will be understood by
`those skilled in the art that the foregoing and other changes
`in form and detail may be made therein without departing
`from the spirit and scope of the invention.
`What is claim is:
`1. An integrated circuit including a DRAM, said DRAM
`comprising:
`a memory array including a plurality of pass gate tran(cid:173)
`sistors and a plurality of memory elements;
`said pass gate transistors each having a gate material
`selected to provide a substantially near mid-gap work
`function or greater; and
`a peripheral area including a plurality of logic transistors.
`2. The integrated circuit of claim 1 wherein said pass gate
`25 transistors are silicon-on-insulator transistors.
`3. The integrated circuit of claim 1 wherein the gate
`material of said logic transistors are of the same type of
`material as said gate material for said pass gate transistors.
`4. The integrated circuit of claim 1 whe