1602
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980
`
`A 1-µm Mo-Poly 64-kbit MOS RAM
`
`FUMIHIKO YANAGAWA, KAZUHIDE KIUCHI, TETSUO HOSOY A, TOSHIAKI TSUCHIYA,
`TAKAO AMAZAWA, AND TSUNEO MANO
`
`Abstract-This paper describes a 1-µm 64-kbit MOS RAM using Mo(cid:173)
`poly technology. New 1-µm double-gate technology using molybde(cid:173)
`num and polysilicon (Mo-poly technology) is proposed. In this tech(cid:173)
`nology, molybdenum and polysilicon are used for ~ord lines and storage
`capacitor electrodes in the memory cell, respectively. Therefore, the
`propagation delay in a word line becomes extremely small and mem?_IY
`cell size is reduced. New two step annealing was developed for stabiliz(cid:173)
`ing an Mo-gate MOS structure. Design is optimized for 1-µm Si-gate
`FET's in peripheral circuitry. A 1-µm Mo-poly 64-kbit MOS RAM was
`experimentally fabricated by using 1-µm process technologies. Th~ cell
`size and die size were 8 µm X 8 µm and 3 mm X 3 mm, respectively.
`Access time was less than 100 ns.
`
`I. INTRODUCTION
`
`T HE HIGHLY INTEGRATED NMOS dynamic RAM is
`
`rapidly progressing towards increased speed and packing
`density. For high-density VLSI's, 64-kbit RAM's in 2- and
`1-µm devices using electron-beam direct writing have been re(cid:173)
`ported (1] - [4]. For high-speed LSI's, a molybdenum-gate
`16-kbit MOS RAM has been developed [5]. However, com(cid:173)
`bined high packing density and speed performance haw not
`been demonstrated in the past.
`In this paper, a new 1-µm double-gate technology using
`molybdenum and polysilicon (Mo -poly technology) is pro(cid:173)
`In this technology, molybdenum is used for word
`posed.
`lines and gate electrodes for MOSFET's in memory cells.
`Polysilicon is used for gate electrodes for MOSFET's in periph(cid:173)
`eral circuitry and storage capacitor electrodes. Therefore,
`a high packing density and high-speed MOS RAM is realized
`due to reduction in memory-cell size and in word-line propa(cid:173)
`gation delay.
`Two-step annealing was developed to realize the Mo-poly
`MOS RAM. The 1-µm Si-gate FET design is optimized to
`improve speed performance. A 1-µm fine pattern is obtained
`by electron-beam direct write and dry etching.
`Based upon the above technologies, a 1-µm Mo-poly 64-
`kbit MOS RAM has been experimentally fabricated. Minimum
`pattern width was 1 µm. The die size was 3 mm X 3 mm.
`Access time was less than 100 ns at single power supply
`(VDD = 5 V).
`
`II. Mo-POLY TECHNOLOGY
`Recently, most LSI's have used polysilicon for gate material.
`Some MOS memories are reported to have a metal gate, such
`as molybdenum or aluminum [5], [6], depending upon the
`
`Manuscript received December 6, 1979; revised January 16, 1980.
`The authors are with Musashino Electrical Communication Labora(cid:173)
`tory, Nippon Telegraph and Telephone Public Corporation, Musashino,
`Tokyo 180, Japan.
`
`,;
`s
`>-
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`~
`5 ;::
`< (!)
`< 10
`g;
`a:
`C.
`w
`/I
`~
`@ 0o
`4
`~ WORD-LINE LENGTH
`(mm)
`Fig. 1. Propagation delay in a word line versus~orfline length .. Prop(cid:173)
`agation delay t pd is calculated ~Y t pd = kRs COL I W, where k 1s con(cid:173)
`stant (1.025). Wis 2 µm and C 0 is 0.33 pF/mm. Rs ofa molybde(cid:173)
`num word line is 0.5 0/CJ and those of a polysilicon and aluminum
`word lines are 25 0/o and 0.1 0/o, respectively.
`
`desired MOS RAM speed performance characteristics. Small
`propagation delay in a word line is necessarily required in
`order to realize a high-speed MOS RAM whose access time is
`less than I 00 ns. Propagation delay mainly depends on word(cid:173)
`line sheet resistivity and its length. Fig. 1 shows the word-line
`length dependence for each material. Propagation delay tpd
`was estimated by step response on a distributed transmission
`line, that is, tpdcxR/)0L 2/W, where Rs is sheet resistance,
`C0
`is an effective value of the capacitance per unit length,
`L is length, and Wis width in a word line [7]. According to
`the calculated results, propagation delay in the metal word
`line is negligible. However, if conventional polysilicon is
`selected as the gate material, the word line in the MOS RAM
`must be divided into several small parts to reduce the delay.
`However, this leads to additional complexity with peripheral
`circuitry and an increase in die size. It is obvious then, that
`the metal-gate structure is better than the Si gate. Moreover,
`self-aligning gate technology becomes important to minimize
`FET size. Thus refractory metal, such as molybdenum, is
`most suitable for the word-line material [8] .
`In addition to the reduction in propagation delay, it is nec(cid:173)
`essary to consider packing density when developing a high(cid:173)
`performance RAM. From this point of view, molybdenum(cid:173)
`polysilicon (Mo-poly) technology is proposed, since the use of
`double-gate structure is effective to reduce the memory-cell
`size. Fig. 2 shows memory-cell structures realized by this
`technology. First-level gate of polysilicon is used as the stor(cid:173)
`age capacitor electrode, which does not significantly affect
`word-line delay or speed performance. The word line is made
`of molybdenum, that is, second-level gate. These structures
`also provides a good intermediate insulating layers between
`two gate electrodes and aluminum-molybdenum multilevel
`
`0018-9383/80/0800-1602$00.75 © 1980 IEEE
`
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`

`YANAGAWA eta/.: 1-µm Mo-POLY 64-KBIT MOS RAM
`
`1603
`
`WORD LINE
`1Moi
`
`COLUMN
`SELECT
`
`: - - - · ---,LINE.Ali
`
`(a)
`
`~
`-
`,A
`.L~
`
`'
`
`A
`
`-
`_ _j
`~Sµm----1 E:~E
`/~:o,
`
`SG
`OLY·Si
`o,
`
`(b)
`
`l
`
`Mo
`
`J
`P SUBSTRATE
`64-kbit memory cell diagram. (a) Layout. (b) Cross section of
`A-A'.
`
`Fig. 2.
`
`tlJ o.sr;;,
`
`0
`
`0.6
`J
`0
`;; 0.4
`
`;:
`g 0.2
`
`0
`
`V, ~ SV
`Vsus = ~2v
`J,l! 0,.----~-~-
`1
`2
`~
`EFFECTIVE CHANNEL
`LENGTH Leff
`:µm',
`Fig. 3. Mobile charge density dependence on annealing atmosphere.
`Annealing temperature was l000°C. At two-step annealing, nitrogen
`annealing time was 10 min. The hydrogen and nitrogen mixture gas
`volume ratio was 1: 10.
`
`interconnection system. Thus in the Mo-poly technology,
`two kinds of MOSFET's are available on a chip: Mo-gate FET's
`for cell transistors and Si-gate FET's for peripheral circuitry.
`Si-gate FET's were used in the latter because they have low
`threshold voltage due to their work-function values [9].
`
`III. A Two-STEP ANNEALING METHOD FOR
`AN Mo GATE
`An Mo-gate MOS structure has been stabilized in the Mo(cid:173)
`gate 16K fabrication process by improved molybdenum
`evaporation, high-temperature annealing in nitrogen for the
`Mo gate, and HCl gate oxidation [10].
`HCl oxidation is desirable because of its passivation effect
`[11] . However, the conventional HCl oxidation process in(cid:173)
`cludes annealing at l 150°C in HCl-OrN2 mixture gas which
`is not desirable to make a fine-pattern device, because the
`channel-stopper profile becomes very wide. An Mo-gate FET
`with dry 0 2 gate oxide, on the other hand, has large mobile
`charges as the Mo gate does not have the passivation effect.
`The mobile charge density, however, can be reduced on subse(cid:173)
`quent annealing. Fig. 3 shows the annealing atmosphere effect
`on mobile charge density in an Mo-gate MOS structure. The
`annealing temperature was 1000°C. By annealing in a mixture
`of hydrogen and nitrogen, mobile charges were reduced to one
`hundredth of that of nitrogen annealing. The stabilization
`effect by the mixture gas annealing has already been reported
`[12]. The NrH2 annealing, however, causes many defects
`such as holes in the Mo film. Fig. 4 shows scanning-electron
`micrographs of molybdenum-film surfaces before and after
`Nz-H2 mixed gas annealing. A two-step annealing process
`of N2 annealing followed by Nz-H2 mixed gas annealing
`results in mobile charge density reduction of one tenth of
`that in N2 annealing but the defect density in the Mo film
`is much smaller. For this reason, two-step annealing was
`employed instead of mixed gas annealing.
`Further reduction in mobile charge density to ~l X 10 10/cm 2
`is obtained by pre-evaporation of Mo before actual deposition
`and washing of the wafers in H3P04 solution and water prior
`to the two-step annealing to reduce photoresist contamination.
`The pre-evaporation step is carried out by evaporating molyb(cid:173)
`denum before the silicon wafers are set in the evaporator, to
`reduce sodium-ion contamination on the surface of the crucible
`and the substrate holders.
`
`1--1
`O.Sµm
`
`AFTER 2 STEP ANNEALING
`(N2 AND H2/N2)
`Fig. 4. A scanning-electron micrographs of molybdenum film surfaces
`deposited onto SiO2 film thermally grown on Si wafer. Deposition
`rate and film thickness were 10 A/sand 0.2 µm, respectively. Sub(cid:173)
`strate temperature was 250°C. Annealing temperature and time were
`1000°C and 20 min, respectively. Annealing time in nitrogen at two(cid:173)
`step annealing was 10 min.
`
`IV. MOSFET DESIGN
`Short-channel Si-gate and Mo-gate FET's have been designed
`to develop the 1-µm Mo-poly 64-kbit MOS RAM. The design
`for the two kinds of MOSFET's was somewhat restricted by
`the fabrication process technologies, because two kinds of
`MOSFET's must be made on the same substrate. Device
`parameters for 1-µm Si-gate FET's are optimized for peripheral
`circuitry where high performance is required.
`For high-speed operation of the 64-kbit RAM, a 5-V power
`supply and 0.5-V threshold voltage for 1-µm Si-gate FET's are
`chosen for high-speed operation of the 64-kbit RAM. Other
`important device parameters in designing Si-gate FET's with
`1-µm effective channel length are source and drain n+ junction
`depth, gate oxide thickness, and substrate doping concentra(cid:173)
`tion. Shallow n+ junction of 0.25-µm depth is sufficient to
`minimize short-channel effects. The gate oxide has to be thin
`to minimize subthreshold leakage and back-gate effect, while
`giving due consideration to defect density. A 30-nm gate
`
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`1604
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980
`
`(cid:143)
`1-z
`~>
`0:: 0
`----(cid:173)
`::::,
`(.) <
`E
`z
`ci:
`0::
`Cl
`
`DRAIN VOLTAGE Vo
`(IV/DIV)
`
`(cid:143)
`
`(a)
`
`(b)
`
`DRAIN VOLTAGE Vo
`(IV/DIV)
`Fig. 6. Si- and Mo-gate FET drain characteristics. (a) Si-gate MOSFET.
`(b) Mo-gate MOSFET Si-gate FET effective channel length was 1 µm.
`That of an Mo-gate FET was 1.5 µm. There were eight gate voltage
`steps. Each step was 1 V.
`
`RAS CAS i~ '~·-~~ -
`
`-- 7
`
`I
`
`;
`
`I
`
`:
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`:~I
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`~ u 81:,! MEMORY 1j1~1j\ MEMORY I~
`Sci ~1~,I ARRAY :~; ~I ARRAY I~
`I!
`1\ililii, 32K
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`~=:'~--Ac -----A,
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`N, ANNEALING
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`2 STEP ANNEALING
`N, AND N, H,,
`
`Hz N, ANNEALING
`
`30
`20
`10
`ANNEALING TIME min
`Fig. 5. Threshold-voltage dependence on effective channel length. Gate
`oxide was 30 nm thick. Substrate concentration and B+ dose were
`3 X 10 15/cm 3 and 5.9 X 10 11/cm2 , respectively.
`
`TABLE I
`MQSFETS PARAMETERS AND CHARACTERISTICS
`
`I
`
`I
`
`Substrate Concentration
`
`B+ Dose
`
`Gate Oxide Thickness
`
`N+ Junction Depth
`
`Si-Gate
`
`Mo-Gate
`
`3 X ~015 /cm3
`5. 9 X 10 11;crn2 - -
`--
`30 nm
`40 nm
`
`0. 25 µm
`
`Effective Channel Length
`
`) 1)
`Thifthold Voltage ( Vth
`Subthreshold Leakage ( JJ) 2)
`
`1.0 µm
`
`0. 5 V
`
`1.5 µm
`
`1. 3 V
`
`75 mV/dec.
`
`85 mV/dec.
`
`Back-gate Coefficient (()\ sub) J) 0. 054
`5 30 cm 2 /v sec
`
`Field Effect Mobility
`
`- -
`- -
`
`1) V = V I
`-7
`g ID = 10
`(Weff/Leff), VD = 5 V, vsub = -2 v.
`th
`2) £ =
`
`l
`
`/
`
`( cJ(log r
`
`)/c1VG).
`
`O
`
`)) Ci sub= (Vth (Vsubl) - vth (Vsub2) )/(Vsub2 - vsubl)'
`
`oxide thickness was chosen. Shallow B+ implantation was
`made for threshold-voltage adjustment. The substrate concen(cid:173)
`tration and the B+ dose were determined to suppress the
`threshold voltage change caused by drain voltage, back-gate
`effect, and subthreshold leakage at the same time. B+ dose
`and substrate concentration were 5.9 X 10 11/cm2 and 3 X
`1015/cm3, respectively. Fig. 5 shows effective channel length
`versus
`threshold voltage for short-channel Si-gate FET's.
`Threshold voltage was defined as a measured gate voltage Ve
`to give drain current In = 0.1 (Werr/Leff) µA. To make
`0 .5 ± 0 .1-V threshold voltage, it is necessary to make I ±
`0.1-µm effective channel length. This value was realized by
`the use of electron-beam direct writing. Device parameters
`and characteristics for 1-µm Si-gate FET's are shown in
`Table I.
`In designing Mo-gate FET's in memory cell, gate oxide
`thickness and effective channel length are important. Maxi(cid:173)
`mum gate voltage, applied to Mo-gate FET's in memory cells,
`is 7 V to obtain higher signal level. Therefore, it was necessary
`to increase Mo-gate FET gate oxide thickness to 40 nm. To
`avoid short-channel effect in Mo-gate FET's, the effective
`channel length was increased to 1.5 µm. Device parameters
`and characteristics for the Mo-gate FET are also shown in
`Table I. Mo-gate FET characteristics are good enough for
`memory operation, because Mo-gate FET's are used only in
`memory cells.
`
`32K
`
`8 ii
`
`I
`
`11
`
`I
`
`I
`
`O ~ 0
`lu,I
`,
`1r5i
`IU::I
`ROW DECODER
`
`I
`
`I
`
`I~
`
`I
`
`I
`
`Fig. 7. 64-kbit RAM block diagram.
`
`Drain characteristics for Si-gate and Mo-gate FET's are
`shown in Fig. 6. Source-drain breakdown voltage for the Si(cid:173)
`gate FET is higher than 8 V under a near 0-V gate voltage.
`
`V. 64-KBIT RAM DESIGN AND ITS FABRICATION
`RESULTS
`
`A. 64-kbit RAM Design
`Fig. 7 shows a block diagram of this RAM. There are two
`memory array blocks. Each block consists of 128 X 256 mem(cid:173)
`ory cells. Typical power supply is a single 5 V. Main clocks,
`addresses, inputs, and outputs are TTL compatible. External
`clocks are used for all the other clocks.
`An array of 256 sense-refresh amplifiers is located between
`the two memory array blocks. A capacitive-coupled amplifier
`is used, which consists of a flip-flop with two coupling capac(cid:173)
`itors [5]. When the clock is applied to drive the sense ampli·
`fier, the amplifier is activated and the bit-line potential is
`pushed up to high level through the coupling capacitors, thus
`providing a high potential level.
`Two multiplexers are placed symmetrically on either side of
`memory cells [ 5] . Only multiplexer (I) is used for the read
`
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`

`YANAGAWA et al.: 1-µm Mo-POLY 64-KBIT MOS RAM
`
`1605
`
`TABLE II
`MAIN PROCESS TECHNOLOGIES USED FOR THE 64-KBIT RAM
`
`+ N-channel 1 frn Mo-poly Technology
`+ Electron-beam Direct Writing,
`
`Ultraviolet Photolithography
`
`+ Dry Etching, Wet Etching
`+ Dry o2 Oxidation for Both Gate Oxides,
`Si-gate and Mo-gate
`
`cycle. For the writing operation, input data signal and its
`complimentary signal are fed to a pair of bit lines, at the same
`time, through multiplexers (I) and (II), respectively. Then, the
`flip-flop state is settled. Thus read-modify-write is possible
`in spite of dynamic mode operation.
`A memory cell diagram is shown in Fig. 2. The cell size is
`8 µm X 8 µm. The word line, composed of molybdenum, is
`2 µm wide. The bit and column select lines, composed of
`aluminum, are 1 µm wide. The contact hole is 1 µm X 1 µm.
`Space between an Mo-gate elect
`and the storage capacitor
`polysilicon electrode ensures precision effective channel length
`for an Mo-gate FET. Storage capacitance Cs to effective bit(cid:173)
`line capacitance CB ratio is about 1 :8. The worst signal size
`is about ±100 mV.
`
`B. Fabrication Process
`Table II shows the main process technologies used. Electron(cid:173)
`beam direct writing was employed for the critical levels to
`ensure highly precise patterns. Dry-etching techniques were
`used to make the precisely shaped patterns at all patterning
`Isolation layers were made by recessed selective oxi(cid:173)
`levels.
`dation in much the same way as in a standard Si-gate MOS
`fabrication process [ 13 ][ . Gate oxide film was made with dry
`0 2 oxidation. Gate oxide thickness for Si-gate was 30 nm
`and that for Mo gate was 40 nm. Polysilicon was deposited
`by the usual chemical vapor deposition process. Molybdenum
`film was deposited by the electron-beam gun evaporation
`method. For stabilizing Mo-gate MOS structure, two-step
`annealing was performed before intermediate layer deposi(cid:173)
`tion. A 0.25-µm-deep diffused layer, for the source and
`drain, was fabricated by arsenic-ions implantation. Flowed
`phosphosilJcate glass was used as the intermediate layer be(cid:173)
`tween two gate electrodes and the second-layer electrode
`[14]. The second-layer electrode, composed of aluminum,
`was deposited by the planer magnetron sputtering technique.
`Fig. 8 shows a scanning-electron micrograph of the 64-kbit
`memory cells. The bit and column select lines are 1 µm in
`width. Alignment accuracy for bit lines and contact holes
`was within ±0.2 µm.
`
`C. Experimental Results
`A microphotograph of the fabricated RAM and the observed
`operating waveforms are shown in Figs. 9 and 10, respectively.
`Measurements were carried out under typical VDD = 5 V con(cid:173)
`dition. The upper waveform is the RAS clock. The lower
`waveforms are data out, "l" and "0." The observed access
`
`COLUMN
`SELECT
`-- LINE (Al)
`( lµm WIDE)
`
`-BIT LINE (Al)
`( lµm WIDE)
`
`~WORD LINE
`(Mo)
`(2µm WIDE)
`Fig. 8. 64-kbit memory cell scanning-electron micrograph.
`
`Fig. 9. 64-kbit RAM die. Die size was 3 mm X 3 mm.
`
`Dour
`
`,, 1 "
`no"
`
`Fig. 10. 64-kbit RAM observed waveforms.
`
`time is 95 ns as compared to the simulated access time of
`75 ns for VDD = 5 V. Table III shows the 64-kbit RAM char(cid:173)
`acteristics. Memory organization is 64 K words X 1 bit. Power
`dissipation is 150 mW at 150-ns cycle time.
`
`VI. SUMMARY
`A new Mo-poly technology is proposed. This technology
`provides reduction in word-line propagation delay and in
`memory-cell size. To realize a stable Mo-gate MOS structure,
`two-step annealing was developed. To improve speed perfor(cid:173)
`mance, design was optimized for 1-µm Si-gate FET's em(cid:173)
`ployed in peripheral circuitry.
`
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`

`1606
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980
`
`TABLE III
`64-KBIT RAM CHARACTERISTICS
`
`Technology
`
`Single Transistor Cell,
`
`N-channel Mo-poly Technology
`
`Organization
`
`64 -Kword x 1 bit
`
`Cell Size
`
`Die Size
`
`8 pm X 8 }lm
`
`3 mm x 3 mm
`
`Access Time
`
`95 ns
`
`Supply Voltage
`
`+ 5 V single
`
`Power Dissipation
`
`150 mW (at 150 ns cycle time)
`
`Refresh
`
`256 cycle
`
`The cell and die sizes are 8 µm X 8 µm and 3 mm X 3 mm,
`respectively. The access time is 95 ns_ The word-line delay in
`this 64-kbit RAM is about 0.25 ns. This value is negligible for
`high-speed memory operation. The Mo-poly technology is
`useful for VLSI fabrication, due to its low-resistance word
`line and high packing density.
`
`ACKNOWLEDGMENT
`The authors wish to thank Dr. S. Ohara and Dr. H. Yoshimura
`for their advice and encouragement. They also wish to thank
`Dr. Katsuraki and his staff members in the Mask and Pattern
`Generation Section at Musashino Electrical Communication
`Laboratory, who are responsible for electron-beam writing
`and dry etching development. The authors are also grateful
`to Dr. M. Kondo, Dr. T. Asaoka, Dr. N. Ieda, Dr. E. Arai, and
`the staff members of the Semiconductor Memory Technology
`Section and the Semiconductor Memory Design Section for
`useful discussions and comments.
`
`REFERENCES
`
`[1] E. Arai and N. Ieda, "A 64-kbit dynamic MOS RAM," IEEE J.
`Solid-State Circuits, vol. SC-13, pp. 333-338, June 1978.
`[2] T. Wada, M. Takada, S. Matsue, M. Kamoshida, and S. I. Suzuki,
`"A 150 ns 150 mW 64K dynamic MOS RAM," IEEE J. Solid(cid:173)
`State Circuits, vol. SC-13, pp. 607-611, Oct. 1978.
`[3] R. P. Cenker, D. G. Clemons, W. R. Huber, J. B. Petrizzi, F. J.
`Procyk, and G. M. Trout, "A fault-tolerance 64K dynamic RAM,"
`in ISSCC Tech. Dig., pp. 150-151, Feb. 1979.
`[4] P. W. Cook, S. E. Schuster, D.R. Freedman, J. T. Pairish, and
`V. DiLonardo, "One micron MOSFET PLA's" in ISSCC Tech.
`Dig., pp. 62-63, Feb. 1979.
`[5] M. Kondo, T. Mano, F. Yanagawa, H. Kikuchi, T. Amazawa, K.
`Kiuchi, N. Ieda, and H. Yoshimura, "A high speed molybdenum
`gate MOS RAM," IEEE J. Solid-State Circuits, vol. SC-13, pp.
`611-616, Oct. 1978.
`[6] R.R. DeSimone, N. M. Donofrio, B. L. Flur, R.H. Kruggel, and
`H. H. Leung, "Dynamic memories," in /SSCC Tech. Dig., pp.
`154-155, Feb. 1979.
`[7] L. P. Huelsman and W. J. Kerwin, "Digital computer analysis of
`distributed-lumped-active networks," IEEE J. Solid-State Cir(cid:173)
`cuits, vol. SC-3, pp. 26-29, Jan. 1968.
`(8] D. M. Brown, W. E. Engeler, M. Gaifinkel, and P. V. Gra}, "Self(cid:173)
`registered molybdenum-gate MOSFET," J. Electrochem. Soc.,
`vol. 115, pp. 874-876, Aug. 1968.
`[9] F. Faggin and T. Klein, "Silicon gate technology," Solid-State
`Electron., vol. 13, pp. 1125-1144, 1970.
`[10] F. Yanagawa, T. Amazawa, and H. Oikawa, "Mo-gate MOS metal(cid:173)
`lization system," Japan. J. Appl. Phys., vol. 18, suppl. 18-1, pp.
`237-245, 1979.
`[11] C. Hashimoto, S. Muramoto, N. Shiono, and 0. Nakajima, "A
`method of forming thin and highly reliable gate oxides-two step
`HCl oxidation," J. Electrochem. Soc., vol. 127, pp. 129-135,
`Jan. 1980.
`[12] H. Ishikawa, H. Tokunaga, N. Toyokura, and M. Shinoda, "Inter(cid:173)
`face properties of Mo-gate MOS structure," in Electrochem. Soc.
`115th Meet., vol. 79-1, pp. 406-408, May 1979.
`[13] E. Bassous, H. N. Yu, and V. Maniscalno, "Topology ofstructures
`with recessed SiO 2 ," J. Electrochem. Soc., vol. 123, pp. 1729-
`1737, Nov. 1976.
`[14] C. T. Naber, "A technique for obtaining tapered oxide steps in
`silicon-gate integrated circuits," J. Electrochem. Soc., vol. 119,
`p. 301C (abstr. 351RNP), 1972.
`
`Micron Ex. 1004, p. 5
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`

`~ IEEE TRANSACTIONS ON
`
`ELECTRON
`DEVICES
`
`AUGUST 1980
`
`VOLUME ED-27
`
`NUMBER 8
`
`(ISSN 0018-9383)
`
`A PUBLICATION OF THE IEEE ELECTRON DEVICES SOCIETY
`
`JOINT SPECIAL ISSUE ON VERY-LARGE-SCALE INTEGRATION
`Also published in IEEE Journal of Solid-State Circuits, August 1980, Volume SC-15, Number 4
`
`FOREWORD ...................................................... H. Friedrich, W. F. Kosonocky, and Y. Takeishi 1319
`
`PAPERS
`
`1346
`
`Overviews
`Basic Technology for VLSI (Part II) .................................................................. Y. Tarui 1321
`VLSI Impact on Microprocessor Evolution, Usage, and System Design .................................... P. M. Russo 1332
`The Challenge of the VLSI Technique to Telecommunications Systems .................................... K. F. Gaser 1341
`VLSI Technologies
`1-µm MOS Process Using Anisotropic Dry Etching ........................................... N. Endo and Y. Kurogi
`Quadruply Self-Aligned MOS (QSA MOS)-A New Short-Channel High-Speed High-Density MOSFET for VLSI ........ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K. Ohta, K. Yamada, M. Saitoh, K. Shimizu, and Y. Tarui 1352
`Design and Characteristics of the Lightly Doped Drain-Source (LOO) Insulated Gate Field-Effect Transistor ............. .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard 1359
`Electrical Measurement of Feature Sizes in MOS Si 2-Gate VLSI Technology ........ D. Takacs, W. Muller, and U. Schwabe 1368
`A 1-µm Bipolar VLSI Technology ............. S. A. Evans, S. A. Morris, L.A. Arledge, Jr., J. 0. Englade, and C.R. Fuller 1373
`Subnanosecond Self-Aligned 12L/MTL Circuits ............................................................... .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D. D. Tang, T. H. Ning, R. D. Isaac, G. C. Feth, S. K. Wiedmann, and H-N. Yu
`1379
`Application of MoSb to the Double-Level Interconnections of 12L Circuits .......... Y. Sasaki, 0. Ozawa, and S. Kameyama
`1385
`An Advanced PSA Technology for High-Speed Bipolar LSI ......... H. Nakashiba, I. Ishida, K. Aomura, and T. Nakamura 1390
`Vertical p-n-p for Complementary Bipolar Technology ................................................. I.E. Magda
`1394
`OXIL, A Versatile Bipolar VLSI Technology ........................ J. Agraz-Guerena, P. T. Panousis, and B. L. Morris
`1397
`Emitter Effects in Shallow Bipolar Devices: Measurements and Consequences ............................. A. W. Wieder
`1402
`Processing and Lithography
`Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects ............................ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. P. Murarka, D. B. Fraser, A. K. Sinha, and H.J. Levinstein 1409
`Composite Silicide Gate Electrodes-Interconnections for VLSI Device Technologies ................................. .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H.J. Geipel, Jr., N. Hsieh, M. H. Ishaq, C. W. Koburger, and F. R. White 1417
`MOS Compatibility of High-Conductivity TaSb/n+ Poly-Si Gates ................................................ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. K. Sinha, W. S. Lindenberger, D. B. Fraser, S. P. Murarka, and E. N. Fuls
`Film Properties of MoSi 2 and their Application to Self-Aligned MoSb Gate MOSFET ................................ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T. Mochizuki, T. Tsujimaru, M. Kashiwagi, and Y. Nishi 1431
`Selective Anodic Oxidation of Silicon in Oxygen Plasma ...................................... V. Q. Ho and T. Sugano 1436
`Double-Layer Resist Films for Submicrometer Electron-Beam Lithography ............................... Y. Todokoro 1443
`Application of Line-Edge Profile Simulation to Thin-Film Deposition Processes ... A. R. Neureuther, C. H. Ting, and C-Y. Liu
`1449
`A General Simulator for VLSI Lithography and Etching Processes: Part II-Application to Deposition and Etching ........ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W. G. Oldham, A. R. Neureuther, C. Sung, J. L. Reynolds, and S. N. Nandgaonkar 1455
`
`1425
`
`( Contents continued on back cover)
`
`Micron Ex. 1004, p. 6
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`(Contents continued from front cover)
`
`1629
`1640
`1649
`
`1655
`
`Quantitative Evaluation of Proximity Effect in Raster-Scan Exposure System for Electron-Beam Lithography ............. .
`1460
`• • • • • • • • • • • • • • ................................................................. M. Nakase and M. Yoshimi
`Advanced Electron-Beam Lithography-Software System AMDES ....... N. Sugiyama, K. Saitoh, K. Shimizu, and Y. Tarui 1466
`Analysis of the Role of High-Brightness Electron Guns in Lithography ..................................... J. C. Wolfe 147 5
`Process, Device, and Circuit Modeling
`1479
`Two-Dimensional Numerical Simulation of Impurity Redistribution in VLSI Processes ......................... R. Tielert
`Simulation of Doping Processes ................. H. Ryssel, K. Haberger, K. Hoffman, G. Prinke, R. Dumcke, and A. Sachs 1484
`1493
`A Model for the Lateral Variation of Autodoping in Epitaxial Films ................................... G. R. Srinivasan
`Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces ....................... .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. C. Sun and J. D. Plummer 1497
`Threshold-Sensitivity Minimization of Short-Channel MOSFET's by Computer Simulation ............................ .
`1509
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K. Yokoyama, A. Yoshii, and S. Horiguchi
`1514
`Computer Analysis of a Short-Channel BC MOSFET ............... H. Oka, K. Nishiuchi, T. Nakamura, and H. Ishikawa
`Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation .............. J. A. Greenfield and R. W. Dutton 1520
`A Two-Dimensional Computer Analysis of Triode-Like Characteristics of Short-Channel MOSFET's .................... .
`1533
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L. M. Dang and M. Konaka
`MINIMOS-A Two-Dimensional MOS Transistor Analyzer ................... S. Selberherr, A. Schutz, and H. W. Patz! 1540
`1550
`Interactive Two-Dimensional Design of Barrier-Controlled MOS Transistors ...... S. Liu, B. Hoe/flinger, and D. 0. Pederson
`Computer-Aided Device Optimization for MOS/VLSI .............. R. F. Motta, P. Chang, J. G. J. Chern, and N. Godinho 1559
`A Model for the Submicrometer n-Channel Deep-Depletion SOS/MOSFET .. . R. T. Jerdonek, W.R. Bandy, and J. Birnbaum 1566
`Transient Analysis of MOS Transistors ...................................... . S-Y. Oh, D. E. Ward, and R. W. Dutton 1571
`1579
`An Evaluation of Submicrometer Potential Barriers Using Charge-Transfer Devices ....... G. W. Taylor and P. K. Chatterjee
`Memories
`An Mo Gate 4K Static MOS RAM ......................................................................... .
`1586
`. . . . . . . . . . . . . . . . . . . . . . H. Ishikawa, M. Yamamoto, H. Tokunaga, N. Toyokura, F. Yanagawa, K. Kiuchi, and M. Kondo
`1591
`. 0. Minato, T. Masuhara, T. Sasaki, H. Nakamura, Y. Sakai, T. Yasui, and K. Uchibori
`2K X 8 Bit Hi-CMOS Static RA M's
`1596
`A 5-V Only 16-kbit Stacked-Capacitor MOS RAM .... M. Koyanagi, Y. Sakai, M. Ishihara, M. Tazunoki, and N. Hashimoto
`1602
`A 1-µm Mo-Poly 64-kbit MOS RAM ........ . F. Yanagawa, K. Kiuchi, T. Hosoya, T. Tsuchiya, T. Amazawa, and T. Mano
`1607
`Single 5-V, 64K RAM with Scaled-Down MOS Structure .................. H. Masuda, R. Hori, Y. Kamigaki, and K. Itoh
`1612
`A 1-Mbit Full-Wafer MOS RAM ........................... Y. Egawa, T. Wada, Y. Ohmori, N. Tsuda, and K. Masuda
`A 4-Mbit Full-Wafer ROM .......................................... Y. Kitano, S. Kohda, H. Kikuchi, and S. Sakai 1621
`Hot-Electron Design Considerations for High-Density RAM Chips ................................................ .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R. R. Troutman, T. V. Harroun, P. E. Cottrell, and S. N. Chakravarti
`A Limitation of Channel Length in Dynamic Memories ........................ . J-I. Nishizawa, T. Ohmi, and H-L. Chen
`Proposed Process Modifications for Dynamic Bipolar Memory to Reduce Emitter-Base Leakage Current .......... I. Antipov
`High-Density Electron-Beam-Fabricated CCD Memory Components .............................................. .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. M. Hamilton, J. G. Nash, R. C. Henderson, J. Y. Chen, D. M. Leong, and N. Cuk
`Logic Arrays and Image Sensors
`1665
`High-Speed MOS Gate Array ................................... M. Nakaya, 0. Tomisawa, I. Ohkura, and T. Nakano
`A Dense Gate Matrix Layout Method for MOS VLSI .................................. . A. D. Lopez and H-F. S. Law 1671
`MOS Area Sensor: Part I-Design Consideration and Performance of an n-p-n Structure 484 X 384 Element Color MOS
`lmager ................................ . N. Koike, I. Takemoto, K. Satoh, S. Hanamura, S. Nagahara, and M. Kubo
`MOS Area Sensor: Part II-Low-Noise MOS Area Sensor with Antiblooming Photodiodes ............................ .
`. . . . . . . . . . . . . . . S. Ohba, M. Nakai, H. Ando, S. Hanamura, S. Shimada, K. Satoh, K. Takahashi, M. Kubo, and T. Fujita
`A Large Area TOI Image Sensor for Low Light Level Imaging ............................ M. G. Farrier and R.H. Dyck
`Materiar Limitations which Cause Striations in CCD lmagers .................................................... .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L. Jastrzebski, P.A. Levine, A. D. Cope, W. N. Henry, and D. F. Battson
`
`1676
`
`1682
`1688
`
`1694
`
`CONTRIBUTORS
`
`1701
`
`ANNOUNCEMENT
`Ad com Elections ......................................................................... • . • • • • • • • • • • • • • •
`
`1725
`
`Micron Ex. 1004, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`,/( ~ ?>
`Y®
`
`IEEE ELECTRON DEVICES SOCIETY
`
`The Electron Devices Society is an organization, within the framework of the IEEE, of members with principal professional interest in