UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Declaration of Dr. John Bravman
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner
`
`Case No.: IPR2020-01008
`U.S. Patent No. 6,445,047
`Original Issue Date: September 3, 2002
`
`Title: SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING
`THE SAME
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`
`- 1 -
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`Micron Ex. 1003, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
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`

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`
`
`Declaration of Dr. John Bravman
`
`I. 
`II. 
`
`Page
`TABLE OF CONTENTS
`INTRODUCTION ............................................................................ - 6 - 
`EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS ................................................. - 6 - 
`III.  ASSIGNMENT AND MATERIALS CONSIDERED .................... - 9 - 
`IV.  UNDERSTANDING OF THE LAW ............................................. - 11 - 
`V. 
`LEVEL OF SKILL IN THE ART .................................................. - 15 - 
`VI.  THE 047 PATENT’S EFFECTIVE FILING DATE ..................... - 16 - 
`VII.  THE 047 PATENT ......................................................................... - 17 - 
`A. 
`Technology Background ...................................................... - 17 - 
`B. 
`Summary of the 047 Patent .................................................. - 19 - 
`C. 
`The 047 Patent’s Claims ...................................................... - 22 - 
`VIII.  CLAIM CONSTRUCTION ........................................................... - 26 - 
`A. 
`“Surface-channel-type MOSFET” (Claims 1-4) .................. - 27 - 
`B. 
`“Logic Circuit Block” and “Memory Cell Block” (Claim 3-4) .. -
`31 - 
`IX.  THE PRIOR ART ........................................................................... - 33 - 
`A.  Yanagawa, A 1-µm Mo-Poly 64-kbit MOS RAM, IEEE
`Transaction on Electron Devices, Vol. ED-27, No. 8, Aug. 1980
`(“Yanagawa”) ....................................................................... - 33 - 
`U.S. Patent No. 6,424,016 (“Houston”) ............................... - 35 - 
`B. 
`U.S. Patent No. 6,165,849 (“An”) ........................................ - 40 - 
`C. 
`X.  YANAGAWA: CLAIMS 1-2 AND 4 ............................................ - 41 - 
`A. 
`Claim 1 ................................................................................. - 41 - 
`1. 
`[1.PRE] “A semiconductor device comprising:” ....... - 41 - 
`2. 
`[1.A] “a first-surface-channel-type MOSFET with a first
`threshold voltage; and” .............................................. - 42 - 
`[1.B] “a second-surface-channel-type MOSFET with a
`second threshold voltage having an absolute value greater
`than an absolute value of said first threshold voltage,” .... -
`44 - 
`
`3. 
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`Declaration of Dr. John Bravman
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`4. 
`
`5. 
`
`6. 
`
`7. 
`
`[1.C] “wherein the first-surface-channel-type MOSFET
`includes: a first gate insulating film formed on a
`semiconductor substrate; and” ................................... - 46 - 
`[1.D] “a first gate electrode, which has been formed out
`of a poly-silicon film formed directly on the first gate
`insulating film; and” .................................................. - 47 - 
`[1.E] “wherein the second-surface-channel-type
`MOSFET includes a second gate insulating film formed
`on the semiconductor substrate; and” ........................ - 50 - 
`[1.F] “a second gate electrode, which has been formed
`out of a refractory metal film formed directly on the
`second gate insulating film, the refractory metal film
`being made of a refractory metal or a compound thereof.”
` .................................................................................... - 52 - 
`Claim 2: “The device of claim 1, wherein a dopant
`concentration in the channel region of the second-surface-
`channel-type MOSFET is lower than a dopant concentration in
`the channel region of the first-surface-channel-type MOSFET” -
`54 - 
`Claim 4 ................................................................................. - 56 - 
`1. 
`[4.A.] “The device of claim 1, wherein the first-surface-
`channel-type MOSFET is formed in a logic circuit block
`of the semiconductor substrate, and” ......................... - 56 - 
`[4.B] “wherein the second-surface-channel-type
`MOSFET is formed in a memory cell block of the
`semiconductor substrate, and” ................................... - 57 - 
`[4.C] “wherein the second gate insulating film is thicker
`than the first gate insulating film.” ............................ - 59 - 
`XI.  YANAGAWA IN VIEW OF AN: CLAIM 3 ................................. - 59 - 
`A. 
`Claim 3 ................................................................................. - 60 - 
`1. 
`[3.A.] “The device of claim 1, wherein the first-surface-
`channel-type MOSFET is formed in a logic circuit block
`of the semiconductor substrate, and” ......................... - 60 - 
`
`B. 
`
`C. 
`
`2. 
`
`3. 
`
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`Micron Ex. 1003, p. 3
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`Declaration of Dr. John Bravman
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`2. 
`
`[3.B] “wherein the second-surface-channel-type
`MOSFET controls power to be supplied to the logic
`circuit block.” ............................................................. - 61 - 
`3.  Motivation to Combine Yanagawa with An .............. - 61 - 
`XII.  HOUSTON: CLAIMS 1-2 AND 4 ................................................. - 67 - 
`A. 
`Claim 1 ................................................................................. - 67 - 
`1. 
`[1.PRE] “A semiconductor device comprising:” ....... - 67 - 
`2. 
`[1.A] “a first-surface-channel-type MOSFET with a first
`threshold voltage; and” .............................................. - 67 - 
`[1.B] “a second-surface-channel-type MOSFET with a
`second threshold voltage having an absolute value greater
`than an absolute value of said first threshold voltage,” .... -
`69 - 
`[1.C] “wherein the first-surface-channel-type MOSFET
`includes: a first gate insulating film formed on a
`semiconductor substrate; and” ................................... - 72 - 
`[1.D] “a first gate electrode, which has been formed out
`of a poly-silicon film formed directly on the first gate
`insulating film; and” .................................................. - 74 - 
`[1.E] “wherein the second-surface-channel-type
`MOSFET includes a second gate insulating film formed
`on the semiconductor substrate; and” ........................ - 74 - 
`[1.F] “a second gate electrode, which has been formed
`out of a refractory metal film formed directly on the
`second gate insulating film, the refractory metal film
`being made of a refractory metal or a compound thereof.”
` .................................................................................... - 75 - 
`Claim 2: “The device of claim 1, wherein a dopant
`concentration in the channel region of the second-surface-
`channel-type MOSFET is lower than a dopant concentration in
`the channel region of the first-surface-channel-type MOSFET” -
`77 - 
`Claim 4 ................................................................................. - 78 - 
`
`3. 
`
`4. 
`
`5. 
`
`6. 
`
`7. 
`
`B. 
`
`C. 
`
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`Micron Ex. 1003, p. 4
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`IPR2020-01008
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`

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`
`Declaration of Dr. John Bravman
`
`1. 
`
`2. 
`
`3. 
`
`2. 
`
`[4.A.] “The device of claim 1, wherein the first-surface-
`channel-type MOSFET is formed in a logic circuit block
`of the semiconductor substrate, and” ......................... - 78 - 
`[4.B] “wherein the second-surface-channel-type
`MOSFET is formed in a memory cell block of the
`semiconductor substrate, and” ................................... - 79 - 
`[4.C] “wherein the second gate insulating film is thicker
`than the first gate insulating film.” ............................ - 80 - 
`XIII.  HOUSTON IN VIEW OF AN: CLAIM 3 ..................................... - 83 - 
`A. 
`Claim 3 ................................................................................. - 83 - 
`1. 
`[3.A.] “The device of claim 1, wherein the first-surface-
`channel-type MOSFET is formed in a logic circuit block
`of the semiconductor substrate, and” ......................... - 83 - 
`[3.B] “wherein the second-surface-channel-type
`MOSFET controls power to be supplied to the logic
`circuit block.” ............................................................. - 83 - 
`3.  Motivation to Combine Houston with An ................. - 84 - 
`XIV.  DECLARATION ............................................................................ - 90 - 
`
`
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`
`I.
`
`Declaration of Dr. John Bravman
`
`I, Dr. John Bravman, hereby declare as follows:
`
`INTRODUCTION
`1.
`I have been retained Micron Technology, Inc. (“Micron”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”). I am not an employee of Micron or any affiliate
`
`or subsidiary of Micron.
`
`2.
`
`I have been asked to consider whether certain references teach or
`
`suggest the features recited in certain claims of U.S. Patent No. 6,445,047, which I
`
`refer to herein as the 047 patent.
`
`3. My opinions and the bases for my opinions are set forth below.
`
`4.
`
`I am being compensated at $695 per hour for my work, plus
`
`reimbursement for any reasonable expenses. My compensation is based solely on
`
`the amount of time that I devote to activity related to this case and is in no way
`
`contingent on the nature of my findings, the presentation of my findings in
`
`testimony, or the outcome of this or any other proceeding. I have no other
`
`financial interest in this proceeding.
`
`II. EDUCATION BACKGROUND, PROFESSIONAL EXPERIENCE,
`AND OTHER QUALIFICATIONS
`5. My curriculum vitae (“CV”) is attached hereto as Attachment A and
`
`provides an accurate identification of my background and experience.
`
`
`
`- 6 -
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`Micron Ex. 1003, p. 6
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`Declaration of Dr. John Bravman
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`6.
`
`I received my Bachelor of Science degree in Materials Science and
`
`Engineering from Stanford University in 1979. I later received a Master of
`
`Science degree in Materials Science and Engineering from Stanford University in
`
`1981, and I was awarded a Ph.D. in Materials Science and Engineering from
`
`Stanford University in 1984, specializing in semiconductor processing and
`
`materials analysis. My thesis was entitled “Morphological Aspects of Silicon –
`
`Silicon Dioxide VLSI Interfaces,” and concerned structural analyses of silicon-
`
`silicon dioxide interfaces, as found in integrated circuit devices – specifically very-
`
`large-scale integrations devices.
`
`7.
`
`I am currently employed as the President and as a Professor of
`
`Electrical Engineering at Bucknell University in Lewisburg, Pennsylvania. As the
`
`President at Bucknell, I am the chief administrator at the university and am
`
`responsible for helping to set university policy and priorities, alumni relations, and
`
`university advancement.
`
`8.
`
`From 1979 to 1984, while a graduate student at Stanford, I was
`
`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
`
`Research Laboratory. I worked in the Materials Characterization group. In 1985,
`
`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
`
`Professor of Materials Science and Engineering. I was promoted to Associate
`
`
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`- 7 -
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`Micron Ex. 1003, p. 7
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`Professor with tenure in 1991, and achieved the rank of Professor in 1995. In
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`Declaration of Dr. John Bravman
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`1997I was named to the Bing Professorship.
`
`9.
`
`I served as Chairman of Stanford University’s Department of
`
`Materials Science and Engineering from 1998 to 1999, and the Director of
`
`Stanford’s Center for Materials Research from 1998 to 1999. I served as Senior
`
`Associate Dean of the School of Engineering from 1992 to 2001 and the Vice
`
`Provost for Undergraduate Education from 1999 to 2010.
`
`10. On July 1, 2010, I retired from Stanford University and began service
`
`as the President of Bucknell University, where I also became a Professor of
`
`Electrical Engineering.
`
`11.
`
`I have worked for more than 25 years in the areas of thin film
`
`materials processing and analysis. Much of my work has involved materials for
`
`use in microelectronic interconnects and packaging, and in superconducting
`
`structures and systems. I have also led multiple development efforts of specialize
`
`equipment and methods for determining the microstructural and mechanical
`
`properties of materials and structures.
`
`12.
`
`I have taught a wide variety of courses at the undergraduate and
`
`graduate level in materials science and engineering, emphasizing both basic
`
`science and applied technology, including coursework in the areas of integrated
`
`circuit materials and processing. More than two thousand students have taken my
`
`
`
`- 8 -
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`classes, and I have trained 24 doctoral students, most of whom now work in the
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`Declaration of Dr. John Bravman
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`microelectronics and semiconductor processing industries.
`
`13.
`
`I am or have been a member of many professional societies, including
`
`the Materials Research Society, the Institute of Electrical and Electronic Engineers,
`
`Electron Microscopy Society of America, the American Society of Metals, the
`
`Metallurgical Society of AIME, the American Chemical Society, and the American
`
`Physical Society. I served as President of the Materials Research Society in 1994.
`
`III. ASSIGNMENT AND MATERIALS CONSIDERED
`14.
`I have been asked to provide analysis and explain the subject matter of
`
`the 047 Patent, including the state of the art when the 047 Patent application was
`
`filed. I have also been asked to consider, analyze, and explain certain prior art to
`
`the 047 Patent including how that art relates to the challenged claims of the 047
`
`Patent and to provide my opinions regarding whether that art invalidates the
`
`claimed subject matter.
`
`15. The opinions expressed in this declaration are not exhaustive of my
`
`opinions regarding the unpatentability of the claims of the 047 Patent. Therefore,
`
`the fact that I do not address a particular point should not be understood to indicate
`
`an agreement on my part that any claim complies with the requirements of any
`
`applicable patent or other rule.
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`
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`Micron Ex. 1003, p. 9
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`Declaration of Dr. John Bravman
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`16.
`
`I reserve the right to amend and supplement this declaration in light of
`
`additional evidence, arguments, or testimony presented during this IPR or related
`
`proceedings on the 047 Patent.
`
`17.
`
`In forming the opinions set forth in this declaration, I have considered
`
`and relied upon my education, knowledge of the relevant field, knowledge of
`
`scientific and engineering principles, and my experience. I have also reviewed and
`
`considered the 047 Patent (Exhibit 1001), its prosecution history (Exhibit 1002),
`
`and the following additional materials:
`
`Exhibit
`
`Description
`
`1004
`
`1006
`
`1007
`
`1014
`
`1015
`
`1016
`
`1018
`
`1019
`
`Yanagawa et al., A 1-µm Mo-Poly 64-kbit MOS RAM, IEEE
`Transaction on Electron Devices, Vol. ED-27, NO. 8, August
`1980 (“Yanagawa”)
`
`U.S. Patent No. 6,424,016 (“Houston”)
`
`U.S. Patent No. 6,165,849 (“An”)
`
`Chen, CMOS Devices & Technology for VLSI, Prentice Hall
`(1990)
`
`U.S. Patent No. 6,037,625 (“Matsubara”)
`
`Van Der Tol et al., Potential and Electron Distribution Model
`for the Buried-Channel MOSFET, IEEE Transactions on
`Electron Devices, Vol. 36, No. 4, April 1989 (“Van Der Tol”)
`
`Baker et al., DRAM Circuit Design – A Tutorial, IEEE Press
`Series on Microelectronic Systems (Tewksbury & Brewer ed.,
`2001) (“Baker”)
`
`Prince, Semiconductor Memories – A Handbook of Design,
`Manufacture, and Application (2nd ed. 1991) (“Prince”)
`
`
`
`- 10 -
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`Micron Ex. 1003, p. 10
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`

`

`Declaration of Dr. John Bravman
`
`Exhibit
`
`Description
`
`1020
`
`1021
`
`1022
`
`1023
`
`1038
`
`U.S. Patent No. 6,030,862 (“Kepler”)
`
`U.S. Patent No. 5,998,251 (“Wu”)
`
`U.S Patent No. 6,642,098 (“Leung”)
`
`U.S. Patent No. 5,858,831 (“Sung”)
`
`U.S. Patent No. 6,249,145 (“Tanaka”)
`
`
`
`
`
`IV. UNDERSTANDING OF THE LAW
`18.
`I am not an attorney, but have been instructed in and applied the law
`
`as described in this section.
`
`19.
`
`I understand that the first step in comparing an asserted claim to the
`
`prior art is for the claim to be properly construed. I address how a person of
`
`ordinary skill in the art would have understood the claims of the alleged invention
`
`in Section VIII below.
`
`20.
`
`I have been further instructed and understand that a patent claim is
`
`unpatentable and invalid as obvious if the subject matter of the claim as a whole
`
`would have been obvious to a person of ordinary skill in the art of the claimed
`
`subject matter as of the time of the invention at issue. I understand that when
`
`assessing the obviousness of claimed subject matter, the following factors are
`
`evaluated: (1) the scope and content of the prior art; (2) the difference or
`
`
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`differences between each claim of the patent and the prior art; and (3) the level of
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`Declaration of Dr. John Bravman
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`ordinary skill in the art at the time the patent was filed.
`
`21.
`
`I understand that claimed subject matter may be obvious in view of
`
`more than one item of prior art. I understand, however, that it is not enough to
`
`show simply that all the limitations of the claimed subject matter are spread
`
`throughout the prior art. Instead, for claimed subject matter to be obvious over
`
`multiple references, there must be some reason or motivation for one of ordinary
`
`skill in the art to combine the prior art references to arrive at the claimed subject
`
`matter.
`
`22.
`
`I have been informed that, in seeking to determine whether an
`
`invention that is a combination of known elements would have been obvious to a
`
`person of ordinary skill in the art at the time of the invention, one must consider
`
`the references in their entirety to ascertain whether the disclosures in those
`
`references render the combination obvious to such a person.
`
`23.
`
`I have been informed and understand that, while not required, the
`
`prior art references themselves may provide a teaching, suggestion, motivation, or
`
`reason to combine, but other times the motivation linking two or more prior art
`
`references is common sense to a person of ordinary skill in the art at the time of the
`
`invention.
`
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`Declaration of Dr. John Bravman
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`24.
`
`I understand that a particular combination may be proven obvious
`
`merely by showing that it was obvious to try the combination. I have been
`
`informed that, if a technique has been used to improve one device, and a person of
`
`ordinary skill in the art would recognize that it would improve similar devices in
`
`the same way, using the technique is obvious unless its actual application is
`
`beyond his or her skill.
`
`25.
`
`I further understand that an obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references also may be supplied by the direction of the
`
`marketplace. For example, when there is a design need or market pressure to solve
`
`a problem and there are a finite number of identified, predictable solutions, a
`
`person of ordinary skill has good reason to pursue the known options within his or
`
`her technical grasp because the result is likely the product not of innovation but of
`
`ordinary skill and common sense.
`
`26.
`
`I have been informed that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than
`
`yield predictable results. Thus, where all of the elements of a claim are used in
`
`substantially the same manner, in devices in the same field of endeavor, the claim
`
`is likely obvious.
`
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`Declaration of Dr. John Bravman
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`27. Additionally, I understand that a patent is likely to be invalid for
`
`obviousness if a person of ordinary skill can implement a predictable variation or if
`
`there existed at the time of the invention a known problem for which there was an
`
`obvious solution encompassed by the patent’s claims. Therefore, when a work is
`
`available in one field of endeavor, design incentives and other market forces can
`
`prompt variations of it, either in the same field or a different one.
`
`28.
`
`I further understand that combining embodiments related to each other
`
`in a single prior art reference would not ordinarily require a leap of inventiveness.
`
`29.
`
`I also understand that one of ordinary skill in the art must have had a
`
`reasonable expectation of success when combining references for claimed subject
`
`matter to be obvious.
`
`30.
`
`I have been informed and I understand that factors referred to as
`
`“objective indicia of non-obviousness” or “secondary considerations” are also to
`
`be considered when assessing obviousness when such evidence is available. I
`
`understand that these factors can include: (1) commercial success; (2) long-felt but
`
`unresolved needs; (3) copying of the invention by others in the field; (4) initial
`
`expressions of disbelief by experts in the field; (5) failure of others to solve the
`
`problem the claimed subject matter solved; and (6) unexpected results.
`
`31.
`
`I also understand that evidence of objective indicia of non-
`
`obviousness must be commensurate in scope with the claimed subject matter. I
`
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`further understand that there must be a relationship, sometimes referred to as a
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`Declaration of Dr. John Bravman
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`“nexus,” between any such secondary indicia and the claimed invention.
`
`32. Finally, I have been informed that one cannot use hindsight to
`
`determine that an invention was obvious.
`
`33.
`
`I provide my opinions in this declaration based on the guidelines set
`
`forth above.
`
`V. LEVEL OF SKILL IN THE ART
`34.
`I have been informed and understand that the level of ordinary skill in
`
`the relevant art at the time of the invention is relevant to inquiries such as the
`
`meaning of claim terms, the meaning of disclosures found in the prior art, and the
`
`reasons one of ordinary skill in the art may have for combining references.
`
`35.
`
`I have been informed and understand that factors that may be
`
`considered in determining the level of ordinary skill include: (1) the education of
`
`the inventor; (2) the type of problems encountered in the art; (3) prior art solutions
`
`to those problems; (4) rapidity with which innovations are made; (5) sophistication
`
`of the technology; and (6) education level of active workers in the relevant field. I
`
`have been further informed and understand that a person of ordinary skill in the art
`
`is also a person of ordinary creativity.
`
`36. A person of ordinary skill in the art (“POSITA”) at the time of the
`
`alleged invention would have had at least a Bachelor of Science degree in electrical
`
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`engineering or material science (or equivalent education in a related field), and at
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`Declaration of Dr. John Bravman
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`least two years of experience in the development, design, or implementation of
`
`semiconductor devices. This POSITA would be aware of and generally
`
`knowledgeable about the structure and operation of DRAM.
`
`37.
`
`In view of my educational background (e.g. a Ph.D. in Materials
`
`Science and Engineering obtained in 1984) and decades of experience working
`
`with semiconductor materials and associated devices, as discussed in Section II, I
`
`was a person of more than the ordinary level of skill in the art as of October 1999.
`
`My opinions herein, however, were formed taking into account the perspective of
`
`an ordinarily skilled artisan.
`
`VI. THE 047 PATENT’S EFFECTIVE FILING DATE
`38.
`I understand that the application leading to the 047 Patent was filed on
`
`October 26, 2000.
`
`39. Based on my review of the 047 Patent, I note that it also makes
`
`reference to an October 26, 1999 filing in Japan.
`
`40. For purposes of this declaration, I have been instructed to use October
`
`26, 1999 as the effective filing date of the 047 Patent. My opinions in this
`
`declaration were formed from the perspective of a person of ordinary skill in the
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`art as of October 26, 1999, including both the knowledge of a person or ordinary
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`skill in the art at that time as well as how a person of ordinary skill in the art would
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`Declaration of Dr. John Bravman
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`have understood the prior art.
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`VII. THE 047 PATENT
`A. Technology Background
`41. The 047 Patent relates to a semiconductor device with two types of
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`transistors that have different characteristics. 047 Patent at 2:20-62.
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`42. The two types of transistors are both “surface-channel-type
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`MOSFET[s].” MOSFET stands for metal-oxide-semiconductor field-effect
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`transistor. A MOSFET is a transistor with a source, drain, gate, and body
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`(substrate). It includes gate insulating film (typically a gate oxide such as SiO2)
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`that sits on top of the substrate and a gate that sits on the gate insulating film (e.g.,
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`a polysilicon or metal gate). Ex. 1014, Chen, CMOS Devices & Technology for
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`VLSI (1988) (“Chen”) at 16-17 (p. 18-19).1 The below figure depicts a MOSFET:
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`1 The cites to pages (“p.” and “pp.”) are to the pages of the exhibits and the cites
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`without “p.” or “pp.” are to the page of the textbook or article. Thus, this cite is to
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`pages 16-17 of Chen’s textbook, which is pages 18-19 of Exhibit 1014.
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`Ex. 1014, Chen at Fig. 2.9.
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`43. The “M” in MOSFET is short for a “Metal” gate. However, the
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`MOSFET encompasses transistors with polysilicon gates (the polysilicon is
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`typically heavily doped). Ex. 1014, Chen at 16-17 (pp. 18-19). The 047 Patent
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`uses MOSFET to refer to transistors with polysilicon gates as well. E.g., 047
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`Patent at 2:20-34. I discuss “surface-channel” devices in Section VIII.A.
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`44. The 047 Patent refers to the threshold voltage of transistors. A
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`voltage greater than the threshold voltage (typically abbreviated at Vt) inverts the
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`region underneath the gate insulating film (e.g., in the above figure, from p-type to
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`n-type) to form a channel region between the source and drain that is conductive to
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`allow current to flow between the source and drain regions. Ex. 1014, Chen at 19
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`(p. 21). In simple terms, the threshold voltage is the voltage at which the transistor
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`will turn “on.”
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`45.
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`In designing MOSFETs, there were several known issues to consider,
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`and a POSITA would select the transistor’s dimensions and other characteristics in
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`view of these issues. Ex. 1014, Chen at 182 (p. 130). For transistors that had
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`specific purposes, designers would tweak the characteristics of the standard device
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`transistor. For example, it was known that it was preferable for transistors in a
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`memory array to have a higher threshold voltage than transistors that serve only to
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`perform logic functions. Ex. 1006, Houston at 1:41-46, 1:55-57, 1:63-67, 2:53-56.
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`By way of another example, it was known to use transistors in the input/output
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`circuitry that have a thicker gate oxide than other transistors on the device. Ex.
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`1007, An at 1:34-60.
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`B.
`Summary of the 047 Patent
`46. The 047 Patent relates to two different types of transistors: one type
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`for the memory cell block (this would be the pass or access transistor2 that “opens”
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`the memory cell for reading or writing) and a different type for the logic circuit
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`block (these transistors are not in the memory array and are the supporting logic
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`for the memory array). 047 Patent at 2:20-3:10. As I discuss in Section VIII.B.,
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`2 The terms pass transistor and access transistor are interchangeable.
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`the memory cell block is an array of memory cells that includes pass transistors,
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`Declaration of Dr. John Bravman
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`and the logic circuit block is the supporting logic for the memory array.
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`47. The 047 Patent recognizes that it was known to use a first type of
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`transistor in logic circuits and a second type of transistor in the memory cell block
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`that has a higher threshold voltage than the first transistor type. 047 Patent at 1:18-
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`28. This was extremely well known and Yanagawa illustrates that it was known
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`for decades before the filing of the 047 Patent. See Section IX.A.
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`48.
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` One common way to increase the threshold voltage of a transistor is
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`to dope its channel region. Ex. 1014, Chen at 125-126 (pp. 73-74). By way of
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`example, take the case of an N-MOSFET. The N-MOSFET has n-type
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`source/drain regions and is in a p-type substrate. By implanting additional p-type
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`dopant into the channel, it requires additional gate voltage to invert the p-type
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`channel region to form a channel, thereby increasing the transistor’s threshold
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`voltage.
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`49. The 047 Patent contends that the prior art increases the threshold
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`voltage of the memory-type transistor using doping and that the additional doping
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`was problematic. 047 Patent at 1:28-2:12. The 047 Patent teaches increasing the
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`threshold voltage of the memory-type transistor using a refractory metal3 as the
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`material for the second transistor’s gate (e.g., instead of the conventional
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`polysilicon gate material). 047 Patent at 2:20-49. However, this dates back
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`decades before the 047 Patent. See Section IX (Yanagawa). Indeed, it was
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`textbook material to select the gate material (its work function) to modify the
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`threshold voltage. Ex. 1014, Chen at 211 (p. 159).
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`50. The 047 Patent also describes that the gate insulating film of the
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`second transistor type (memory-type transistor) is thicker than the gate insulating
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`film of the first transistor type (logic-type transistor). 047 Patent at 7:23-26 (first
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`transistor type: 2.5 nm), 7:66-8-4 (second transistor type: 5 nm). Figure 4 depicts
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`this embodiment:
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`3 The 047 Patent provides the following examples of refractory metals: “TiN …
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`tungsten, molybdenum, or tantalum or a compound thereof.” 047 Patent at 6:46-
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`51.
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`047 Patent at Figure 4(c) (with overlay of region labels).
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`51. However, employing logic transistors with thinner gate oxide was also
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`well known. See Section XII.C.3.
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`C. The 047 Patent’s Claims
`52. Claims 1-4 recite:
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`1. A semiconductor device comprising:
`a first-surface-channel-type MOSFET with a first
`threshold voltage; and
`a second-surface-channel-type MOSFET with a second
`threshold voltage having an absolute value greater than
`an absolute value of said first threshold voltage,
`wherein
`the
`first-surface-channel-type MOSFET
`includes:
`a first gate insulating film formed on a semiconductor
`substrate; and
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`the
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`film
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`formed on
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`a first gate electrode, which has been formed out of a
`poly-silicon film formed directly on the first gate
`insulating film, and
`wherein
`the second-surface-channel-type MOSFET
`includes:
`insulating
`a
`second gate
`semiconductor substrate; and
`a second gate electrode, which has been formed out of a
`refractory metal film formed directly on the second gate
`insulating film, the refractory metal film being made of a
`refractory metal or a compound thereof.
`2. The device of claim 1, wherein a dopant concentration
`in