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`PATENT NUMBER
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`8446047
`
`111111111111111II IIIII IIIII IIIII IIIII IIII IIII
`6445047
`
`,.
`·• ~~:1
`JP~
`
`U.S. UTILITY Patent Application
`~/~·1Ei
`PATENT DATE
`\ '\ 1~l
`sE-r • V
`
`SCANNED~ Q.A.
`
`CLASS
`257
`
`SUBCLASS 3q l
`
`I :J a. a. .
`
`<
`
`ART UNIT
`
`EX~IN~A
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`~i,t,z.,4 Y1(2>:'l:, ,,
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`
`' ' me~nod for fabficating the same
`CERTIFICATE
`MAR 1.Pi cUUl.
`OF COktt.t.t; IJON
`
`•
`
`PTO-2040
`12/99
`
`ORIGINAL
`
`'•,, •. ,,.,,.
`
`I ""'"""•~
`
`CLASS
`SUBCLASS
`Z §7
`'J1\
`INTERNATIONAL CLASSIFICATION
`2-'1 /7t,
`·11 () i L
`
`ISSUING CLASSIFICATION
`'··~
`CROSS REFERENCE(S)
`~~--
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`D Continued on Issue Slip Inside File Jacket
`/o ~.;1~
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`et.
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`CLAIMS ALLOWED
`
`.·,,,""'
`DRAWl~'6S,~.
`Figs. Drwg. Prinh~.
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`Total Claims
`
`Print Claim for O.G.
`
`,.
`,,..
`NOTICE OF ALLOWANCE MAILED
`
`,·,,
`
`I
`) /::2_1 /4'2..__,
`
`TERMINAL
`DISCLAIMER
`
`D The term of this patent
`subsequent to
`has been disclaimed.
`
`(date)
`
`(cid:143)
`
`The term of this patent shall
`not extend beyond the expiration date
`of U.S Patent. No.
`
`D The terminal _months of
`this patent have been disclaimed.
`
`Form PTO•436A
`(Rev, 6/99)
`
`1...,..,,-" __(AssisWlt Exami11erY,«1.,,,,l
`
`(Date)
`
`'
`
`'
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`
`""¥''
`
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`Date Paid
`
`'} •:,
`
`1'-,; .'';,\:j
`
`Amount Due
`
`,,
`I
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`(Primary Examiner)
`
`(Date)
`
`~ ::_,,,,,, &ji}-d~-
`
`(Legal Instruments Examiner)
`
`(Date)-.?~--
`
`-
`
`l~fD-er- ·7 --:x3-n~
`
`ISSUE BATCH NUMBER
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`(cid:143) CD-ROM
`FILED WITH: (cid:143) DISK (CRF) (cid:143) FICHE
`•I ~
`1439F - -? .J !~
`M -AS-01-3-00-0006-3-09-06 0103286854
`SKP:RF051387130-00002
`2~MST:RF0513871'3D
`-a1e"1am11r1•ilTil
`a 111111111111111111111111111 111111111111111111111111111111 111111111111111111111111111111111 B
`
`•lap)
`
`6445047
`
`Micron Ex. 1002, p. 1
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`(cid:143)
`

`

`/
`
`Jc929 U.S. PTO
`
`·1Ml'16lill~
`
`,
`
`10/25/00
`
`;;ONTENTS
`
`Date Received
`{Incl. C. of M.)
`or
`Date Mailed
`
`INITIALS __ _
`
`N0VOson2
`
`Date Received
`(Incl. C. of M.)
`or
`Date Mailed
`
`42. _ _ _ _ _ _ _ _ - - -
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`
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`28. _ _
`
`29. _ _
`30. _ _
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`31. _ _
`' 32._
`33._
`34._
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`35._
`36._
`
`37._
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`70. _ _ _ _ _ _ _ _ - - -
`
`71. _ _ _ _ _ _ _ _ - - -
`
`72. _ _ _ _ _ _ _ _ - - -
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`74. _ _ _ _ _ _ _ _ - - -
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`75. _ _ _ _ _ _ _ _ - - -
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`76. _ _ _ _ _ _ _ _ - - -
`77. _ _ _ _ _ _ _ _ _........ _ _
`
`78. _ _ _ _ _ _ _ _ - - -
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`
`80. _ _ _ _ _ _ _ _ - - -
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`81. _ _ _ _ _ _ _ _ - - -
`
`82. _ _ _ _ _ _ _ _ - - -
`
`(LEFT OUTSIDE)
`
`Micron Ex. 1002, p. 2
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`Page 1 of 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`COMMISSIONER FOR PATENTS
`UNITED STATES PATENT AND TRADEMARK OFFICE
`WASHINC,ON. o.:::. 2C 231
`Wlvw. uspto. gov
`
`111m11111111111111111111111111111111111111111111111111111111 1 1111
`Bib Data Sheet
`
`FILING DATE
`SERIAL NU,MB.ER
`,, ' ,.,,
`10/25/2000
`09/695,381
`,.RULE
`
`<t:•\:t
`
`PPLICANTS
`Takayuki Yamada, Osa
`., ~APAN;
`Masaru Moriwaki, Osaka, J >
`
`* CONTI.Nt:JlNG DAT A *****************
`''1.t:t~¥-'llil .. '~
`* FOREIGN APPL~-qoN.S ***************** ,,
`JAPAN 11-303414~(~6/1999
`
`IF REQUIRED, FOREIGN Fl~ CENSE
`GRANTED:* 12/21/2000
`
`erified and
`,r '<nowledged
`DDRESS
`
`ITLE
`
`CLASS
`257
`
`GROUP ART UNIT
`2811
`
`ATTORNEY
`DOCKET NO.
`0819-446
`
`SHEETS
`DRAWING
`4
`
`TOTAL
`CLAIMS
`6
`
`INDEPENDENT
`CLAIMS
`2
`
`Semiconductor device an'd111.ethod for fabricating th) me
`
`FILING FEE FEES: Authority has beeh giv )@ in Paper
`RECEIVED No. ____ to charge/credit~, POSIT ACCOUNT
`840
`No. ____ for following:
`
`j(cid:143) All Fees
`I(cid:143) 1.16 Fees (Filing)
`(cid:143) 1.17 Fees ( Processing Ext. of
`ID 1.18 Fees ( Issue )
`j(cid:143) Other
`ID Credit
`
`time)
`
`file://C:\APPS\PreExam\correspondence\1 A.xml
`
`2/27/0 I
`
`Micron Ex. 1002, p. 3
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`Please type a plus sign(+) inside this box - CJ
`
`PTO/SB/05 (1/98)
`Approved for use through 09/30/2000. 0MB 0651-0032
`Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no oersons are required to resoond to a collection of information unless it disolavs a valid 0MB control number.
`
`UTILITY
`PATENT APPLICATION
`TRANSMITTAL
`(Only for new nonprovisional applications under 37 CFR 1.53(b))
`
`Attorney Docket No. 0819-446
`
`First Inventor or Application Identifier: Takayuki YAMADA et al.
`
`Title: SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING
`THE SAME
`
`Express Mail Label No.
`
`APPLICATION ELEMENTS
`See MPEP chapter 600 concerning utility patent application contents.
`
`ADDRESS TO:
`
`Assistant Commissioner for Patents
`Box Patent Application
`Washington, DC 20231
`
`1. [ ] Fee Transmittal Form (e.g., PTO/SB/17)
`(Submit an original, and a duplicate for fee processing)
`2. [X] Specification
`Total Pages [26]
`(preferred arrangement set forth below)
`- Descriptive title of the Invention
`- Cross References to Related Applications
`- Statement Regarding Fed sponsored R & D
`- Reference to Microfiche Appendix
`- Background of the Invention
`- Brief Summary of the Invention
`- Brief Description of the Drawings (if filed)
`- Detailed Description
`-Claim(s)
`- Abstract of the Disclosure
`3. [X) Drawing(s) (35 USC 113)
`4. [ ] Oath or Declaration
`a. [ ] Newly executed (original or copy)
`b. [ ] Copy from a prior application (37 CFR 1.63(d))
`(for continuation/divisional with Box 17 completed)
`[Note Box 5 below]
`i. [ ) DELETION OF INVENTOR(S)
`Signed statement attached deleting
`inventor(s) named in the prior application,
`see 37 CFR 1.63(d)(2) and 1.33(b).
`5. [ ] Incorporation By Reference (useab/e if Box 4b is checked)
`The entire disclosure of the prior application, from which a
`copy of the oath or declaration is supplied under Box 4b,
`is considered to be part of the disclosure of the
`accompanying application and is hereby incorporated by
`reference therein.
`
`Total Sheets [4)
`Total Pages I ]
`
`6. [ ] Microfiche Computer Program (Appendix)
`
`7. Nucleotide and/or Amino Acid Sequence Submission
`(if applicable, all necessary)
`a. [ ] Computer Readable Copy
`b. [ ] Paper Copy (identical to computer copy)
`c. [ ] Statement verifying identity of above copies
`
`ACCOMPANYING APPLICATION PARTS
`
`8. [ ] Assignment Papers (cover sheet & document(s))
`[ ] Power of Attorney
`9. [ ] 37 CFR 3.73(b) Statement
`(when there is an assignee)
`10. [ ] English Translation Document (if applicable)
`11 . [ ] Information Disclosure Statement
`(IDS)/PT0-1449
`12. [ ] Preliminary Amendment
`13. [X] Return Receipt Postcard (MPEP 503)
`(Should be specifically itemized)
`[ J Statement filed in prior application,
`14. [ J *Small Entity
`Status still proper and desired
`Statement(s)
`(PTO/SB/09-12)
`15. [X] Certified Copy of Japanese Priority Document
`No. 11-303414 Filed: October 26, 1999
`16. I l Other:
`
`I ] Copies of IDS
`Citations
`
`*A new statement is required to be entitled to pay small entity fees,
`except where one has been filed in a prior application and is being
`relied uoon.
`
`17. If a CONTINUING APPLICATION, check appropriate box, and supply the requisfte information b~low and in a preliminary amendment:
`[ ] Continuation
`[ ] Divisional
`[ ] Continuation-in-part (CIP)
`of prior application No.
`Prior application information: Examiner:
`Group/Art Unit:
`
`18. CORRESPONDENCE ADDRESS
`
`[X] Customer Number or Bar Code Label
`
`Customer No. 22204
`
`or [X] Correspondence address below
`
`(Insert Customer No. or Attach bar code label here)
`
`Name:
`Eric J. Robinson
`NIXON PEABODY LLP
`Firm:
`Address: 8180 Greensboro Drive, Suite 800
`City:
`Mclean
`State: VA
`Teleohone (703) 790-911 o
`Countrv: U.S.A.
`- -~
`Name: Jason H. Vick
`Registration No. 45,285
`Signature ~ ~~ Date: October 25, 2000
`.
`tement: This form is estimated to take 0.2 hours to complete. Time will vary depending upon the needs of the individual case. Any comments on the amount of
`are required to complete this form should be sent to the Chief Information Officer, Patent and Trademark Office, Washington, DC 20231. DO NOT SEND FEES OR
`MPLETED FORMS TO THIS ADDRESS. SEND TO: Assistant Commissioner for Patents, Box Patent Application, Washington, DC 20231.
`
`Burde
`Ii
`
`Zip Code: 22102
`FAX (703) 883-0370
`
`---- ,
`
`Micron Ex. 1002, p. 4
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`INVENTOR INF~~MATION
`
`Inventor One Given Name:: Takayuki
`Family Name:: YAMADA
`Postal Address Line One:: 4-2-6, Yamashiro-cho
`City:: Yao-shi
`State or Province:: Osaka
`Country:: Japan
`Postal or Zip Code:: 581-0801
`Citizenship Country:: Japan
`Inventor Two Given Name:: Masaru
`Family Name:: MORIWAKI
`Postal Address Line One:: 3-14-438, Miyuki-higashimachi
`City:: Neyagawa-shi
`State or Province:: Osaka
`Country:: Japan
`Postal or Zip Code:: 572-0055
`Citizenship Country:: Japan
`
`CORRESPONDENCE INFORMATION
`
`Correspondence Customer Number:: 22204
`Fax One:: 7038830370
`Electronic Mail One:: pluther@nixonpeabody.com
`
`APPLICATION INFORMATION
`
`SEMICONDUCTOR DEVICE AND METHOD FOR FABR
`Title Line One::
`ICATING THE SAME
`Title Line Two::
`Total Drawing Sheets:: 4
`Formal Drawings?:: Yes
`Application Type:: Utility
`Docket Number:: 0819-0446
`Secrecy Order in Parent Appl.?:: No
`
`REPRESENTATIVE INFORMATION
`
`Representative Customer Number:: 22204
`Registration Number One:: 38285
`Registration Number Two:: 35483
`Registration Number Three:: 27997
`Registration Number Four:: 26477
`
`PRIOR FOREIGN APPLICATIONS
`
`Foreign Application One:: 11-303414
`Filing Date:: 10-26-1999
`Country:: Japan
`Priority Claimed:: Yes
`
`Micron Ex. 1002, p. 5
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`Source:, PrintEFS Version 1.0.1
`
`Micron Ex. 1002, p. 6
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`SEMICONDUCTOR DEVICE AND
`
`METHOD FOR FABRICATING THE SAME
`
`BACKGROUND OF THE INVENTION
`
`5
`
`The present invention relates to a semiconductor device,
`
`which includes: a first-surface-channel..:type MOSFET with a
`
`threshold voltage of a relatively small absolute value; and a
`
`second-surface-channel-type MOSFET with a threshold voltage
`
`of a relatively large absolute value, and also relates to a
`
`10 method for fabricating the device.
`
`~i:~
`
`Performance enhancement of an MOS semiconductor device
`
`is needed typically in a system LSI, and to realize such an
`
`E!
`
`object, miniaturization, increasing the number of devices in(cid:173)
`
`tegrated and lowering operating voltages are required. For
`
`15
`
`this purpose, it is very important to form surface-channel(cid:173)
`
`type MOSFETs of multiple types on a semiconductor chip.
`
`As a semiconductor device including multiple types of
`
`surface-channel-type MOSFETs, a device with logic circuits
`
`and DRAMs on a semiconductor chip is known. In such a semi-
`
`20 conductor device, MOSFETs, which will be formed in a logic
`
`circuit block, should enhance their driving power by lowering
`
`the threshold voltage and increasing the saturated current
`
`value. On the other hand, MOSFETs, which will be formed in a
`
`memory cell block of DRAMs, should increase a data retention
`
`25
`
`time by raising the threshold voltage value and minimizing a
`f,
`
`1~
`
`Micron Ex. 1002, p. 7
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`leakage current.
`
`To reduce the power consumption of a
`
`logic circuit, a
`
`technique of forming an MTCMOS (Multi-Threshold CMOS) was re(cid:173)
`
`ported. In the MTCMOS, a power supply terminal of the logic
`
`5 circuit block is connected to a provisional power supply
`
`line. And a voltage-regulating transistor is provided between
`
`the provisional power supply line and an original power sup(cid:173)
`
`ply line. When a logic circuit should be operated, power is
`
`supplied to the logic circuit block through the provisional
`
`10
`
`power supply line by turning the voltage-regulating transis-
`
`lJ'i
`
`tor ON. In this construction, by lowering the threshold volt(cid:173)
`
`age of the MOSFETs in the logic circuit block and raising the
`
`saturated current value, driving power can be increased. When
`
`the logic circuit should not be operated, power consumption
`
`15 of the logic circuit on standby state can be reduced by turn(cid:173)
`
`ing the voltage-regulating transistor OFF. For such a regu(cid:173)
`
`lating transistor, lower leakage current is required. Thus,
`
`its threshold voltage is set relatively high.
`
`As
`
`a means
`
`for
`
`forming multiple
`
`types of surface-
`
`20
`
`channel~type MOSFETs with mutually different threshold volt(cid:173)
`
`ages on a single semiconductor substrate, a technique of mak(cid:173)
`
`ing the dopant concentrations in the channel regions differ(cid:173)
`
`ent by implanting dopant ions at mutually different doses in(cid:173)
`
`to the channel regions is known. Specifically, an implant do-
`
`25
`
`se is set higher for the channel region of a surface-channel-
`
`Micron Ex. 1002, p. 8
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`type MOSFET
`
`that should have a relatively high
`
`threshold
`
`voltage. In that case, since the dopant concentration in the
`
`channel region is relatively high, the threshold voltage in-
`
`creases.
`
`5
`
`Also, in a surface-channel-type MOSFET, a gate insulat(cid:173)
`
`ing film is thinned as a surface-channel-type MOSFET is minia(cid:173)
`
`turized. Thus, to realize a predetermined threshold voltage,
`
`the dopant concentration in the channel region tends to in-
`
`crease.
`
`When a surface-channel-type MOSFET with a
`
`relatively
`
`W
`
`high threshold voltage is formed, performance degrades, as
`
`the dopant concentration in the channel region gets higher.
`
`For example, if the dopant concentration in the channel
`
`region is raised, a
`
`leakage current flowing through the pn
`
`15
`
`junction might increase. Consequently, if a MOSFET A-with a
`
`heavily doped channel region is used for a memory cell of a
`
`DRAM, data retention time might be shortened. Also, a channel
`
`region with an increased dopant concentration can increase
`
`the scattering of the dopant in the channel region, which re-
`
`20
`
`sults in decrease of carrier mobility.
`
`Moreover, if a MOSFET with the heavily doped channel re(cid:173)
`
`gion
`
`is used as
`
`a voltage-regulating
`
`transistor for an
`
`MTCMOS, ON-state current characteristics might degrade
`
`( or
`
`increase an ON-state resistance). Therefore, the voltage of a
`
`25 provisional power supply line decreases, thus deteriorating
`
`L
`
`3
`
`Micron Ex. 1002, p. 9
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`the performance of the logic circuit.
`
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the present invention to
`
`5 enhance the performance of a surface-channel-type MOSFET with
`
`a higher threshold voltage in a semiconductor device includ(cid:173)
`
`ing multiple types of surface-channel-type MOSFETs with mutu(cid:173)
`
`ally different threshold voltages.
`
`To achieve this object, an inventive semiconductor de-
`
`10 vice
`
`includes: a
`
`first-surface-channel-type MOSFET with a
`
`threshold voltage of a ·relatively small absolute value; and a
`
`second-surface-channel-type MOSFET with a
`
`threshold voltage
`
`of a
`
`relatively
`
`large absolute value. The
`
`first-surface(cid:173)
`
`channel-type MOSFET
`
`includes: a first gate insulating film
`
`15
`
`formed on a semiconductor substrate; and a
`
`first gate elec(cid:173)
`
`trode, which has been formed out of a polysilicon film over
`
`the first gate insulating film.
`
`The second-surface-channel-
`
`type MOSFET includes: a second gate insulating film formed on
`
`the semiconductor substrate; and a
`
`second gate electrode,
`
`20 which has been formed out of a refractory metal film over the
`
`second gate insulating film. The refractory metal film is made
`
`of a refractory metal or a compound thereof.
`
`In the inventive device, the second gate electrode of
`
`the second-surf ace-channel-type MOSFET is made of a refrac-
`
`25
`
`tory metal or a compound thereof that has a work function
`.,/
`/
`4 L)
`
`Micron Ex. 1002, p. 10
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`corresponding to the intermediate level of the energy gap of
`
`silicon. Therefore,
`
`the second-surface-channel-type MOSFET
`
`can have the absolute value of its threshold voltage in(cid:173)
`
`creased without raising the dopant concentration in the chan-
`
`5 nel region of the second-surface-channel-type MOSFET. As a
`
`result, the second-surface-channel-type NMOS
`
`transistor can
`
`enhance the OFF-state
`
`leakage current characteristics and
`
`minimize a leakage current flowing through its pn junction.
`
`In addition, the transistor can enhance the ON-state current
`m 10 characteristics to reduce the ON-state resistance.
`
`In one embodiment of the present invention, a dopant con(cid:173)
`
`centration
`
`in
`
`the channel
`
`region of
`
`the second-surface(cid:173)
`
`channel-type MOSFET is preferably lower than a dopant concen(cid:173)
`
`tration in the channel region of the first-surface-channel-
`
`15
`
`type MOSFET.
`
`In this manner, the OFF-state leakage current character(cid:173)
`
`istics and the ON-state current characteristics of the sec-
`
`end-surface-channel-type MOSFET can be further improved.
`
`In another embodiment of
`
`the present
`
`invention,
`
`the
`
`20
`
`first-surface-channel-type MOSFET
`
`is preferably formed in a
`
`logic circuit block of the semiconductor substrate, and the
`
`second-surface-channel-type MOSFET preferably controls power
`
`to be supplied to the logic circuit block.
`
`In such an embodiment,
`
`the first-surface-channel-type
`
`25 MOSFET
`
`formed in the logic circuit block can increase its
`
`Micron Ex. 1002, p. 11
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`driving power, because the MOSFET can have the absolute value
`
`of its threshold voltage decreased and its saturated current
`
`value raised.
`
`In addition,
`
`the second-surface-channel-type
`
`MOSFET that controls the power to be supplied to the logic
`
`5 circuit block can improve its ON-state current characteris(cid:173)
`
`tics.
`
`In still another embodiment of the present invention,
`
`the first-surface-channel-type MOSFET is preferably formed in
`
`a logic circuit block of the semiconductor substrate, and the
`
`ff!
`
`tn
`
`10
`
`second-surface-channel-type MOSFET is preferably formed in a
`
`memory cell block of the semiconductor substrate. And the sec(cid:173)
`
`ond gate insulating film is preferably thicker than the first
`
`gate insulating film.
`
`In this manner, the second-surface-channel-type MOSFET
`
`15
`
`can enhance its OFF-state leakage current characteristics and
`
`therefore extend a pause time (i.e., a period of time for
`
`which charge is stored in a single memory cell), which is
`
`usually shortened by the leakage current. As a result, the
`
`storage characteristics are improved significantly.
`
`20
`
`An inventive method is a method for fabricating a semi-
`
`conductor device including: a first-surface-channel-type MOS(cid:173)
`
`FET with a threshold voltage of a relatively small absolute
`
`value;
`
`and
`
`a
`
`second-surface-channel-type MOSFET with
`
`a
`
`threshold voltage of a relatively large absolute value. The
`
`25 method includes the steps of: a)
`
`introducing a dopant into
`
`61 l
`
`Micron Ex. 1002, p. 12
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
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`

`

`•
`
`regions of a semiconductor substrate where first and second
`
`gate electrodes will be
`
`formed for the first and second(cid:173)
`
`surface-channel-type MOSFETs, respectively; b) depositing a
`
`first insulating film and a polysilicon film in this order
`
`5 over the semiconductor substrate; c) patterning the polysili(cid:173)
`
`con film and the first insulating film,
`
`thereby forming the
`
`first gate electrode and a dummy gate electrode out of the
`
`polysilicon film for the first and second-surface-channel(cid:173)
`
`type MOSFETs, respectively, and a first gate insulating film
`
`10
`
`and a dummy gate insulating film out of the first insulating
`
`film for the first and second-surface-channel-type MOSFETs,
`
`respectively; d)
`
`forming sidewalls covering the first gate
`
`electrode and the dummy gate electrode, respectively; e) de(cid:173)
`
`positing an interlayer dielectric film over the entire sur-
`
`15
`
`face of the-semiconductor substrate and then removing parts
`
`r:n
`
`~3=~
`
`of the interlayer dielectric film, which are located over the
`
`first gate electrode and the dummy gate electrode, respec(cid:173)
`
`tively, thereby exposing the first gate electrode and the dum(cid:173)
`
`my gate electrode; f) defining a mask pattern, which covers
`
`20
`
`the first gate electrode but exposes the dummy gate elec(cid:173)
`
`trode, over the interlayer dielectric film and then etching
`
`the dummy gate electrode and the dummy insulating film away
`
`using the mask pattern, thereby forming a recess inside the
`
`sidewall of the dummy gate electrode; g)
`
`forming a second
`
`25 gate insulating film for the second-surface-channel-type MOS-
`
`Micron Ex. 1002, p. 13
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`FET on part of the surface of the semiconductor substrate
`
`that has been exposed inside the recess; h) depositing a re(cid:173)
`
`fractory metal film, which is made of a refractory metal or a
`
`compound thereof, over the entire surface of the semiconduc-
`
`5
`
`tor substrate; and i) removing the refractory metal film, ex(cid:173)
`
`cept for its part filled in the recess, thereby forming the
`
`second gate electrode out of the refractory metal film for
`
`the second-surface-channel-type MOSFET.
`
`According to the inventive method, a first gate elec-
`
`10
`
`tr ode for a first-surface-channel-type MOSFET is formed out
`
`of a polysilicon film. In addition, a second gate electrode
`
`for a second-surface-channel-type MOSFET is formed in a re(cid:173)
`
`cess after a dummy electrode has been removed. The second
`
`gate electrode is formed out of a refractory metal film made
`
`15 of a refractory metal or a compound thereof. In this manner,
`
`the first-surface-channel-type MOSFET,
`
`including the first
`
`gate electrode made of the polysilicon film, and the second(cid:173)
`
`surface-channel-type MOSFET,
`
`including the second gate elec(cid:173)
`
`trode made of the refractory metal film, are obtained. Thus,
`
`20
`
`the second-surface-channel-type MOSFET can have the absolute
`
`value of its threshold voltage increased without raising the
`
`dopant concentration in the channel region of the second(cid:173)
`
`surface-channel-type MOSFET.
`
`Thus, according to the inventive method, it is possible
`
`25
`
`to enhance the OFF-state leakage current characteristics and
`
`Micron Ex. 1002, p. 14
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`the ON current characteristics of the second-surface-channel-
`
`type NMOS transistor in fabricating the semiconductor device.
`
`In one embodiment of the present invention, the process
`
`of introducing a dopant preferably includes the steps of: in-
`
`s
`
`traducing the dopant at a relatively high concentration into
`
`the region of the semiconductor substrate in which the first
`
`gate electrode will be formed; and introducing the dopant at
`
`a relatively low concentration into the region of the semi(cid:173)
`
`conductor substrate in which the second gate electrode will
`
`10 be formed.
`
`In such an embodiment, the dopant c0ncentration in the
`
`channel region of the second-surface-channel-type MOSFET is
`
`lower than the dopant concentration in the channel region of
`
`the first-surface-channel-type MOSFET. As a result, the OFF-
`
`15
`
`state leakage current characteristics and the ON-state cur(cid:173)
`
`rent characteristics of the second-surface-channel-type MOS(cid:173)
`
`FET are further improved.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`lA
`
`through
`
`lD are cross-sectional views
`
`il(cid:173)
`
`lustrating respective process steps for fabricating a semi(cid:173)
`
`conductor device according to a first embodiment of the pres(cid:173)
`
`ent invention.
`
`FIGS.
`
`2A
`
`through 2C are cross-sectional views
`
`il-
`
`25
`
`lustrating respective process steps for fabricating the semi-
`
`Micron Ex. 1002, p. 15
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`conductor device of the first embodiment.
`
`FIGS.
`
`3A
`
`through
`
`3D are cross-sectional views
`
`il(cid:173)
`
`lustrating respective -process steps for fabricating a semi(cid:173)
`
`conductor device according to a second embodiment of the pre(cid:173)
`
`s sent invention.
`
`FIGS.
`
`4A
`
`through 4C are cross-sectional views
`
`il(cid:173)
`
`lustrating respective process steps for fabricating the semi(cid:173)
`
`conductor device of the second embodiment.
`
`10
`
`DESCRIPTION OF THE PREFERRED EMBODIMENTS
`
`EMBODIMENT l
`
`Hereinafter, a semiconductor device and a fabrication
`
`process thereof according to a first embodiment of the pre(cid:173)
`
`sent invention will be described with reference to FIGS.
`
`lA
`
`through lD and FIGS. 2A through 2C. It should be noted that
`
`in FIGS. lA through 2C, a first NMOS transistor is formed in
`
`a logic circuit region on the left side, while a second NMOS
`
`transistor is formed in a power supply control circuit (i.e.,
`
`a circuit that provides a supply voltage to the logic cir-
`
`20 cuit) region on the right side.
`
`First, as shown in FIG.
`
`lA,
`
`isolation regions 101 are
`
`formed on a p-type semiconductor substrate 100 of silicon.
`
`Then, a first ion implantation process is performed. Specifi(cid:173)
`
`cally, ions of a p-type dopant (e.g., boron) are implanted
`
`25
`
`into the regions where the first and second NMOS transistors
`
`Micron Ex. 1002, p. 16
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
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`•
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`will be formed at an implant energy of 30 keV and an implant
`
`dose of 1X10 12
`
`/ cm- 2
`
`, for example, thereby forming p-type doped
`
`regions 102.
`
`Next, as shown in FIG.
`
`lB, a resist mask 103 is formed
`
`5
`
`to cover the region where the second NMOS transistor will be
`
`formed. Then, a second ion implantation is performed. Spe(cid:173)
`
`cifically,
`
`ions of a p-type dopant (e.g., boron) are
`
`im(cid:173)
`
`planted into the region where the first NMOS transistor will
`
`be formed at an implant energy of 30 keV and an implant dose
`
`10 of 4Xl0 12 /cm- 2
`
`• As a result, a first p-type doped region 104
`
`that will have a relatively high dopant concentration in its
`
`channel region is formed in the region where the first NMOS
`
`transistor will be formed. In addition, a second p-type doped
`
`region 105 that will have a relatively low dopant concentra-
`
`15
`
`tion in its channel region is formed in the region where the
`
`second NMOS
`
`transistor will be formed. It should be noted
`
`that the second p-type doped region 105 is the same as the p(cid:173)
`
`type doped regions 102.
`
`Then, as shown in FIG. lC, a silicon dioxide film with a
`
`20
`
`thickness of 2. 5 nm, for example, and an n-type polysilicon
`
`film are formed over the semiconductor substrate 100 in this
`
`order. And by patterning the silicon dioxide film and then(cid:173)
`
`type polysilicon film, a first gate insulating film 106A and
`
`a first gate electrode 107A are formed in the region_ where
`
`25
`
`the first NMOS transistor will be formed, while a dummy gate
`
`Micron Ex. 1002, p. 17
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
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`

`

`•
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`insulating film 106B and a dummy gate electrode 107B are
`
`formed in the region where the second NMOS transistor will be
`
`formed. The next step -is implanting n-type dopant ions using
`
`the first gate electrode 107A and dummy gate electrode 107B
`
`5 as a mask. As a result, n-type lightly doped regions 108 are
`
`formed. Thereafter, sidewalls 109 are formed on the sides of
`
`the first gate electrode 107A and dummy gate electrode 107B.
`
`Then, by implanting n-type dopant ions using the first gate
`
`electrode 107A, dummy gate electrode 107B and sidewalls 109
`
`10
`
`as a mask, n-type heavily doped regions 110 are formed. Next,
`
`an interlayer dielectric film 111 made of a silicon dioxide
`
`film is deposited, by a CVD process, for example, to a thick(cid:173)
`
`ness of 400 nm, for example.
`
`Then, as shown in FIG. 1D,
`
`the interlayer dielectric
`
`lJ1
`
`15
`
`film 111 is planarized by a CMP process, for example, to ex(cid:173)
`
`pose the upper surfaces of the first gate electrode 107A and
`
`dummy gate electrode 107B. And a silicon nitride film 112 is
`
`deposited to a thickness of SO nm, for example, over the en(cid:173)
`
`tire surface of the semiconductor substrate 100.
`
`20
`
`Next, as shown in FIG. 2A, a second resist mask 113 is
`
`formed on the silicon nitride film 112 to cover the region
`
`where the first NMOS transistor will be formed. And then, the
`
`silicon nitride film 112 is patterned using the second resist
`
`mask 113 to form a hard mask 114 out of the silicon nitride
`
`25
`
`film 112.
`
`Micron Ex. 1002, p. 18
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
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`Thereafter, the dummy gate electrode 107B is removed by
`
`a wet-etching process using an echant (e.g., an alkaline so(cid:173)
`
`lution such as a KOH) to open a recess 115 for forming a gate
`
`electrode. And then, the dummy gate insulating film 106B that
`
`5
`
`remains on the bottom of the recess 115 is removed by a wet(cid:173)
`
`etching process using an etchant (e.g., a HF solution). The
`
`dummy gate electrode 107B and dummy gate insulating film 106B
`
`are removed using the hard mask 114 as a mask. In this manner,
`
`the semiconductor substrate 100 has a part of its surface ex-
`
`10 posed.
`
`Subsequently, as shown in FIG. 2B, a second gate insu(cid:173)
`
`lating film 116 of silicon dioxide film is formed to a thick-
`
`,!
`
`ness of 2. 5 nm, for example, on the bottom of the recess 115.
`
`Then, a refractory metal film 117 made of TiN, for example,
`
`15
`
`is deposited by a CVD process, for example, to fill in the
`
`recess 115.
`
`The next step is planarizing the refractory metal film
`
`117 by a CMP process, for instance, until the first gate
`
`electrode 107A exposes its upper surface. As a result, the
`
`20
`
`second gate electrode 118 is formed as shown in FIG. 2C. It
`
`should be noted that, in the planarizing process,~ slurry of
`
`the type eliminating selectivity between the refractory film
`
`117 and hard mask
`
`( silicon nitride film) 114 is preferably
`
`used.
`
`25
`
`Then, metal interconnects are defined by a known process . .
`
`Micron Ex. 1002, p. 19
`Micron v. Godo Kaisha IP Bridge 1
`IPR2020-01008
`
`

`

`•
`
`As a result, the first NMOS
`
`trans is tor is obtained in the
`
`logic circuit region, while the second NMOS transistor is ob(cid:173)
`
`tained in the power supply control circuit region.
`
`According to the first embodiment,
`
`the first surface-
`
`s channel-type NMOS transistor, including the first gate elec(cid:173)
`trode 107A made of a polysilicon film, can be formed in the
`the second surface-channel-type
`
`logic circuit region. And
`NMOS transistor, including the second gate electrode 118 made
`of the refractory metal film 117, can be formed in the power
`supply control circuit region. The refractory metal film may
`
`10
`
`be made of TiN, for example.
`A r