`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`________________________
`
`IPR2020-00990
`Patent No. 6,534,805
`_______________________
`
`
`
`PETITIONER’S UPDATED TABLE OF EXHIBITS
`
`
`
`
`
`
`
`U.S. Patent No. 6,534,805
`Petitioner Reply - IPR2020-00990
`
`LIST OF EXHIBITS
`
`
`
`1002
`1003
`1004
`1005
`
`1006
`1007
`1008
`
`Exhibit No. Description
`1001
`U.S. Patent No. 6,534,805 (with Ex Parte Reexamination
`Certificate Appended)
`Declaration of Dr. Miltiadis Hatalis
`Curriculum Vitae of Dr. Miltiadis Hatalis
`U.S. Patent No. 6,417,549 (“Oh”)
`R. JACOB BAKER ET AL., CMOS CIRCUIT DESIGN,
`LAYOUT AND SIMULATION, IEEE Press (1998) (“CMOS
`Circuit Design”)
`Prosecution History for U.S. Patent Application No. 09/829,510
`Ex Parte Reexamination History for U.S. Patent No. 6,534,805
`Ishida, et al., A Novel 6T-SRAM Cell Technology Designed with
`Rectangular Patterns Scalable beyond 0.18 μm Generation and
`Desirable for Ultra High Speed Operation, IEDM 98, IEEE 1998,
`pp. 201-204 (“Ishida IEDM”)
`U.S. Patent No. 6,677,649 (“Osada”)
`Certain Static Random Access Memories and Products Containing
`the Same, USITC Inv. No. 337-TA-792, Order 29 (Feb. 9, 2012)
`Declaration of Dr. Jacob Baker
`IEEE Press Royalty Statement for CMOS Circuit Design
`Declaration of Dr. Gretchen Hoffman
`Curriculum Vitae of Dr. Gretchen Hoffman
`Machine Readable Cataloging (“MARC”) Bibliographic Record
`for CMOS Circuit Design (OCLC)
`
`1009
`1010
`
`1011
`1012
`1013
`1014
`1015
`
`1
`
`
`
`
`
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`1027
`
`U.S. Patent No. 6,534,805
`Petitioner Reply - IPR2020-00990
`
`Machine Readable Cataloging (“MARC”) Bibliographic Record
`for CMOS Circuit Design (University of Texas Library)
`Machine Readable Cataloging (“MARC”) Bibliographic Record
`for CMOS Circuit Design (North Carolina State University
`Library)
`Machine Readable Cataloging (“MARC”) Bibliographic Record
`for CMOS Circuit Design (University of North Texas Library)
`Pi, Jen-I, MOSIS Scaleable CMOS Design Rules (revision 7), pp.
`1-28, Aug. 1, 1995
`Sing, et al., MorphoSys: A Reconfigurable Architecture for
`Multimedia Applications, IEEE Xplore, pp. 134-139 (1998)
`Lee et al., Design and Implementation of the MorphoSys
`Reconfigurable Computing Processor, J. of VLSI Signal
`Processing Systems, 2:147-164 (2000)
`Stephen A. Campbell, The Science And Engineering of
`Microelectronic Fabrication, 427-439 (Oxford University Press,
`1996)
`Declaration of Debra L. Tasker (dated Mar. 12, 2021) with Exs. A
`and B. (cover, title and copyright pages, pp. 876-877, and inside
`back cover of CMOS Circuit Design, Layout, and Simulation by
`R. Jacob Baker)
`Declaration of Rebecca MacKay Johnson (dated Mar. 15, 2021)
`regarding CMOS Circuit Design, Layout, and Simulation by R.
`Jacob Baker
`Robert F. Pierret, Semiconductor Device Fundamentals, 611-620
`(Addison-Wesley Publishing Company, 1996)
`Purdue MARC source record
`Declaration of Nathan Rupp (dated Mar. 16, 2021) regarding
`CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker
`
`2
`
`
`
`
`
`1028
`
`1029
`
`1030
`
`1031
`1032
`1033
`1034
`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`U.S. Patent No. 6,534,805
`Petitioner Reply - IPR2020-00990
`
`Scheffler et al., On the Impact of Design Rules To High-Density
`Substrate Yield, Proceedings IMAPS Europe 2000 (June 18-20,
`2000)
`Naveed Sherwani, Algorithms for VLSI Physical Design
`Automation, 47-50 (Kluwer Academic Publishers 1993)
`The University of Texas at Tyler Libraries catalog › MARC details
`for CMOS circuit design, layout, and simulation (Record no.
`119771)
`U.S. Patent No. 5,824,579
`U.S. Patent No. 6,169,313
`U.S. Patent No. 6,418,551
`U.S. Patent No. 6,681,376
`Peter Van Zant, Microchip Fabrication, 502-510, (3rd Ed.
`McGraw Hill, 1997)
`Declaration of Rachel Watters (dated Mar. 16, 2021) with Ex. A.
`(cover, title and copyright pages, pg. 877, and inside back cover of
`CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker)
`Reply Declaration of Dr. Gretchen Hoffman In Support of
`Advanced Micro Devices, Inc.’s Petition for Inter Partes Review
`of U.S. Patent No. 6,534,805, dated May 28, 2021
`Expert Declaration of Dr. R. Jacob Baker In Support of Advanced
`Micro Devices, Inc.’s Petition of Inter Partes Review of U.S.
`Patent No. 6,534,805
`Reply Declaration of Dr. Miltiadis Hatalis In Support of Advanced
`Micro Devices, Inc.’s Petition for Inter Partes Review of U.S.
`Patent No. 6,534,805, dated June 3, 2021
`Deposition Transcript of Nader Bagherzadeh, Ph.D, dated April
`30, 2021
`
`3
`
`
`
`U.S. Patent No. 6,534,805
`Petitioner Reply - IPR2020-00990
`
`David J. Elliot, Integrated Circuit Fabrication Technology, Ch. 1
`(pp. 1-9) and Ch. 2 (pp. 43-49) (McGraw-Hill Book Company,
`1982)
`M. Michael Vai, Ph.D, VLSI Design, Ch. 1 (pp. 1-4) (CRC Press,
`2001)
`S.M. Sze, VLSI Technology, Ch. 4 (pp. 141-143) (2nd Ed.,
`McGraw-Hill Book Company, 1988)
`Stephen A. Campbell, The Science and Engineering of
`Microelectronic Fabrication, Ch. 7 (pp. 151-153) (2nd Ed.,
`Oxford University Press, 2001)
`Carver Mead and Lynn Conway, Introduction to VLSI Systems,
`47-51 (Addison-Wesley Publishing Company, 1980)
`Inohara et al., Highly Scalable and Fully Logic Compatible SRAM
`Cell Technology with Metal Damascene Process and W Local
`Interconnect, IEEE, pp. 64-65 (1998)
`Petitioner’s Demonstratives
`
`
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`
`
`4
`
`
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`The undersigned certifies pursuant to 37 C.F.R. § 42.6(e) and § 42.105 that on
`
`August 27, 2021, a true and correct copy of this PETITIONER’S UPDATED TABLE
`
`OF EXHIBITS was served via electronic mail on the Patent Owner at the following
`
`correspondence address of record:
`
`Theodoros Konstantakopoulos, Ph.D.
`(Reg. No. 74,155)
`tkonstantakopoulos@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`212-351-3400 (telephone)
`212-351-3401 (facsimile)
`
`Jonas R. McDavit (to be admitted pro hac
`vice)
`Jordan N. Malz (Reg. No. 48,302)
`Michael A. Wueste (to be admitted pro
`hac vice)
`Ryan G. Thorne (Reg. No. 76,462)
`Eliyahu Balsam (admitted pro hac vice)
`jmcdavit@desmaraisllp.com
`jmalz@desmaraisllp.com
`mwueste@desmaraisllp.com
`rthorne@desmaraisllp.com
`ebalsam@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`212-351-3400 (telephone)
`212-351-3401 (facsimile)
`
`Respectfully submitted,
`
` /s/ Ryan Yagura .
`Ryan Yagura (Reg. No. 47,191)
`O’Melveny & Myers LLP
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Phone: 213-430-6000
`
`Attorney for Petitioners
`
`
`
`
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