`
`
`
`
`
`
`
`
`PETITIONER’S
`PETITIONER’S
`DEMONSTRATIVE EXHIBIT
`DEMONSTRATIVE EXHIBIT
`1047
`1047
`
`
`
`
`
`Advanced Micro Devices, Inc. et al.
`v.
`Monterey Research LLC
`
`Petitioners’ Presentation For IPR2020-00990
`U.S. Patent No. 6,534,805
`September 1, 2021
`
`1
`
`Demonstrative Exhibit 1047, 0001
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`2
`
`Demonstrative Exhibit 1047, 0002
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`3
`
`Demonstrative Exhibit 1047, 0003
`
`
`
`’805 Patent Discloses SRAM Cell Design
`
`Ex-1001 at Cover, Col. 1
`
`4
`
`Demonstrative Exhibit 1047, 0004
`
`
`
`’805 Patent’s SRAM Cell Layout
`
`’805 Patent, Fig 2:
`
`Active Region
`
`Polysilicon gates and
`local interconnect
`
`Transistor
`
`AMD Petition (Paper 1) at 6; Ex-1001 at Fig. 2 (annotated)
`
`5
`
`Demonstrative Exhibit 1047, 0005
`
`
`
`’805 Patent Discloses Common 6-Transistor SRAM Layout
`
`’805 Patent, Fig. 2:
`
`Oh (Prior Art), Fig. 3:
`
`AMD Petition (Paper 1) at 6; Ex-1001 at Fig. 2 (annotated)
`
`AMD Petition (Paper 1) at 20; Ex-1004 (Oh) at Fig. 3 (annotated)
`
`6
`
`Demonstrative Exhibit 1047, 0006
`
`
`
`Grounds Instituted For Review
`
`Institution Decision:
`
`Inst. Dec. (Paper 12) at 7
`
`7
`
`Demonstrative Exhibit 1047, 0007
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`8
`
`Demonstrative Exhibit 1047, 0008
`
`
`
`“Single Local Interconnect Layer” Term
`
`Petitioner’s Construction
`Plain and ordinary meaning
`
`PO’s Construction
`“one local interconnect layer that includes short
`connections that route bitline signals and a global
`wordline signal along that same layer”
`PO argues construction requires interconnection of
`“laterally-displaced components”
`
`AMD Reply (Paper 27) at 6-7
`9
`
`Demonstrative Exhibit 1047, 0009
`
`
`
`Claim Term Has Plain And Ordinary Meaning
`
`Claim limitation:
`
`Petitioner’s claim
`construction position:
`
`AMD Reply (Paper 27) at 6-7
`10
`
`Demonstrative Exhibit 1047, 0010
`
`
`
`Board Found That Plain And Ordinary Meaning Controls
`
`Institution Decision:
`
`Inst. Dec. (Paper 12) at 27
`11
`
`Demonstrative Exhibit 1047, 0011
`
`
`
`PO’s Expert Agrees Plain And Ordinary Meaning Controls
`
`PO’s expert Dr. Bagherzadeh:
`. . .
`
`AMD Reply (Paper 27) at 6, n.4; Ex-2005 (Bagherzadeh Decl.) at ¶¶ 82-83; Ex-1040 (Bagherzadeh Dep. Tr.) at 189:10-22
`12
`
`Demonstrative Exhibit 1047, 0012
`
`
`
`PO Adds Limitation Not Corresponding To Any Claim Language
`
`PO’s Sur-Reply (coloring by PO):
`
`Improperly adding a new limitation that does
`not correspond to any claim language
`
`PO Sur-Reply (Paper 35) at 3; AMDs argument presented in Reply, at 7-9
`13
`
`Demonstrative Exhibit 1047, 0013
`
`
`
`PO’s Construction Re-writes Claim Term
`
`PO’s Sur-Reply (coloring by PO):
`
`Improper rewriting of claim language to change claim scope
`
`PO Sur-Reply (Paper 35) at 3; AMDs argument presented in Reply, at 7-9
`14
`
`Demonstrative Exhibit 1047, 0014
`
`
`
`PO’s Construction Adds Words Not In Claim
`
`PO’s Sur-Reply (coloring by PO):
`
`Adding words not in the claim
`
`PO Sur-Reply (Paper 35) at 3; AMDs argument presented in Reply, at 7-9
`15
`
`Demonstrative Exhibit 1047, 0015
`
`
`
`Patent Owner Continues to Advance
`Rejected “Lateral Displacement” Requirement
`
`PO’s argument:
`
`POR (Paper 25) at 15; Argument presented in Reply, at 9-10
`16
`
`Demonstrative Exhibit 1047, 0016
`
`
`
`PO Modifies Figure 3 To Support “Laterally Displaced” Requirement
`
`PO’s Response:
`
`PO adds contacts to Figure 3 as alleged
`support for “laterally displaced”
`construction
`
`POR (Paper 25) at 34; Argument presented in Reply, at 5-6, 9-10
`17
`
`Demonstrative Exhibit 1047, 0017
`
`
`
`PO’s Modified Figure 3 Excludes Embodiment Claimed By Claim 18
`
`PO’s Response:
`
`Local interconnects 37
`and 40 (common ground)
`are not wide enough to
`support complete lateral
`displacement of contacts
`
`AMD’s Reply:
`
`POR (Paper 25) at 34; Argument presented in Reply, at 5-6, 9-10
`
`Reply (Paper 27) at 10
`
`18
`
`Demonstrative Exhibit 1047, 0018
`
`
`
`PO Re-draws Figure 3 To Justify Construction
`
`PO’s Sur-Reply:
`
`PO enlarges local
`interconnects 37 and 40 to
`support its construction
`
`Argument presented in Reply, at 5-6, 9-10
`
`PO Sur-Reply (Paper 35) at 7
`19
`
`Demonstrative Exhibit 1047, 0019
`
`
`
`“Lateral Displacement” Requirement
`Already Rejected By The Board
`
`Institution Decision:
`
`Paper 12 (Inst. Dec.) at 27
`20
`
`Demonstrative Exhibit 1047, 0020
`
`
`
`“A Single Local Interconnect Layer Comprising Local Interconnects
`Corresponding To Bitlines And A Global Wordline”
`
`Petitioner’s Construction
`Plain and ordinary meaning
`
`PO’s Construction
`“one local interconnect layer that includes short
`connections that route bitline signals and a global
`wordline signal along that same layer”
`PO argues construction requires interconnection of
`“laterally-displaced components”
`
`Petitioner: no construction necessary; term readily understandable
`PO: imports new limitations not supported by any intrinsic evidence
`
`AMD Reply (Paper 27) at 6-10
`21
`
`Demonstrative Exhibit 1047, 0021
`
`
`
`Oh Discloses “Single Local Interconnect Layer” Limitation
`
`’805 Patent, Fig. 3:
`
`Oh, Fig. 5:
`
`LOCAL INTERCONNECT
`CORRESPONDING TO
`BIT LINE
`
`LOCAL
`INTERCONNECT
`CORRESPONDING TO
`GLOBAL WORD LINE
`
`LOCAL INTERCONNECT
`CORRESPONDING TO
`BIT LINE
`
`LOCAL INTERCONNECT
`CORRESPONDING TO
`GLOBAL WORD LINE
`
`Ex-1001 at Fig. 3 (annotated); Ex-1004 (Oh) at Fig. 5 (annotated); AMD Petition (Paper 1) at 51
`22
`
`Demonstrative Exhibit 1047, 0022
`
`
`
`Oh’s Bitline And Wordline Contacts Are Laterally Displaced
`
`PO Reply (coloring of Oh’s Figure 6 by PO):
`
`Oh discloses
`laterally displaced
`contacts C7/P70
`and C8/P78
`
`POR (Paper 25) at 12; Argument presented in Reply, at 19-20
`23
`
`Demonstrative Exhibit 1047, 0023
`
`
`
`Oh Discloses “Single Local Interconnect Layer” Under PO’s Construction
`
`Institution Decision:
`
`Inst. Dec. (Paper 12) at 27; POR (Paper 25) at 12 (annotated)
`
`24
`
`Demonstrative Exhibit 1047, 0024
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`25
`
`Demonstrative Exhibit 1047, 0025
`
`
`
`“Substantially Oblong” Terms
`
`Claim Term
`
`“substantially oblong local
`interconnects”
`(claims 8, 10, 12)
`“substantially oblong
`polysilicon structure”
`(claim 22)
`“substantially oblong
`active region”
`(all challenged claims)
`
`Parties’ Position
`In This IPR
`no construction
`required
`
`no construction
`required
`
`no construction
`required
`
`Board’s Preliminary Construction
`from IPR2020-1491, Paper 10
`local interconnects having a substantially rectangular shape
`
`a polysilicon structure having a length that is greater than about three
`times its width or having a substantially wider region that solely
`accommodates a contact region
`an active region that is not markedly L-shaped and that has (1) a
`substantially constant length and a width that varies by approximately
`one-third or less along its length; (2) a substantially constant length and
`a width that varies only with respect to the widths of access and latch
`transistors; or (3) a length that is greater than or equal to
`approximately three times its maximum width
`
`Petitioner: not necessary to construe; prior art discloses specification’s disclosed embodiments
`PO: argument depends on narrow constructions not proposed and not developed in this IPR
`
`26
`
`Demonstrative Exhibit 1047, 0026
`
`
`
`“Substantially Oblong Local Interconnects” And “Polysilicon Structure”
`
`’805 Patent:
`
`AMD Petition (Paper 1) at 50-51; Ex-1001 at 11:4-10; 11:25-29
`
`27
`
`Demonstrative Exhibit 1047, 0027
`
`
`
`Oh’s Polysilicon Local Interconnects Cross Three Active Regions
`
`Oh, Fig. 3:
`
`AMD Reply (Paper 27) at 15; Ex-1004 (Oh) at Fig. 3 (annotated)
`
`28
`
`Demonstrative Exhibit 1047, 0028
`
`
`
`Each Active-Poly Overlap Is Rectangular
`
`Dr. Bagherzadeh (PO’s expert):
`
`Dr. Hatalis (Petitioner’s expert):
`
`. . .
`
`Ex-1002 (Hatalis Decl.) at ¶ 83
`
`AMD Reply (Paper 27) at 14; Ex-1040 (Bagherzadeh Dep.) at 180:2-181:4
`
`29
`
`Demonstrative Exhibit 1047, 0029
`
`
`
`Oh’s Polysilicon Local Interconnects Must Be Greater Than 3:1
`
`Oh, Fig. 3:
`
`local interconnect including 3 square or
`rectangular shapes spaced apart must be > 3:1
`
`channel width
`
`channel width
`
`channel
`length
`
`channel
`length
`
`channel width
`
`channel width
`
`channel
`length
`
`channel
`length
`
`AMD Reply at 15 (annotating Ex-1004 (Oh) at Fig. 3)
`
`30
`
`Demonstrative Exhibit 1047, 0030
`
`
`
`“Substantially Oblong” “Outer Active Regions”
`
`’805 Patent:
`
`AMD Petition (Paper 1) at 38; Ex-1001 at 7:24-28
`
`31
`
`Demonstrative Exhibit 1047, 0031
`
`
`
`Oh’s Outer NMOS Active Regions Are “Substantially Oblong”
`
`Oh:
`
`Oh, Fig. 3:
`
`Ex-1004 (Oh) at 12:66-13:6, Fig. 3 (annotated); AMD Reply (Paper 27) at 15-16
`
`32
`
`Demonstrative Exhibit 1047, 0032
`
`
`
`“Substantially Oblong” “Inner Active Regions”
`
`’805 Patent:
`
`AMD Petition (Paper 1) at 38; Ex-1001 at 7:24-31
`
`33
`
`Demonstrative Exhibit 1047, 0033
`
`
`
`Petitioner’s Expert Applied Design Rules To Inner Active Regions
`
`Baker (Ex-1005):
`
`Dr. Hatalis (Petitioner expert):
`
`AMD Petition (Paper 1) at 38-39; Ex-1002 (Hatalis Decl.) at ¶¶ 74-75
`
`34
`
`Demonstrative Exhibit 1047, 0034
`
`
`
`PO Expert’s “Redrawn Figure 4” Shows 13:4 Ratio
`
`PO expert Dr. Bagherzadeh’s redrawn Fig. 4:
`
`Inner active regions have 13:4 ratio (3.25:1)
`
`AMD Reply (Paper 27) at 17; Ex-2005 (Bagherzadeh Decl.) at ¶¶ 113-14
`
`35
`
`Demonstrative Exhibit 1047, 0035
`
`
`
`PO’s Surreply: Uncited 11:4 Calculation Requires Removal Of Feature
`PO Sur-Reply:
`
`PO’s calculation requires
`removal of a segment from
`PO Expert’s “redrawn Figure
`4”
`
`PO Sur-reply (Paper 35) at 34
`
`36
`
`Demonstrative Exhibit 1047, 0036
`
`
`
`Oh Discloses “Substantially Oblong” “Inner Active Regions”
`
`’805 Patent:
`
`AMD Petition (Paper 1) at 38; Ex-1001 at 7:24-31
`
`37
`
`Demonstrative Exhibit 1047, 0037
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`38
`
`Demonstrative Exhibit 1047, 0038
`
`
`
`Oh And Baker Both Relate To CMOS Design
`
`AMD Petition (Paper 1) at
`32-35
`Ex-1004 at Cover
`Ex-1005 at Cover, 0005
`
`39
`
`Demonstrative Exhibit 1047, 0039
`
`
`
`Baker Uses MOSIS Design Rules To Teach CMOS Design
`
`AMD Petition (Paper 1) at 34; Ex-1005 (Baker) at 0001, 0018
`
`40
`
`Demonstrative Exhibit 1047, 0040
`
`
`
`Patent Owner’s Expert Admitted MOSIS Was Commonly Known
`
`Dr. Bagherzadeh
`(PO expert):
`
`AMD Reply (Paper 27) at 22; Ex-1040 (Bagherzadeh Dep. Tr.) at 41:1-16
`
`41
`
`Demonstrative Exhibit 1047, 0041
`
`
`
`Patent Owner’s Expert Identified Motivations To Use MOSIS
`
`Dr. Bagherzadeh (PO expert):
`
`AMD Reply (Paper 27) at 22; Ex-1040 (Bagherzadeh Dep.) at 43:23-44:4, 59:4-7, 97:25-98:6
`42
`
`Demonstrative Exhibit 1047, 0042
`
`
`
`PO’s Expert: No Unexpected Results From MOSIS-Made SRAM
`
`Dr. Bagherzadeh
`(PO expert):
`
`. . .
`
`AMD Reply (Paper 27) at 22; Ex-1040 (Bagherzadeh Dep.) at 55:13-56:15
`43
`
`Demonstrative Exhibit 1047, 0043
`
`
`
`PO’s “Design Rule Violation” Arguments Violate Two Basic Principles
`
`PO incorrectly assumes that the entirety of Baker (including every
`MOSIS design rule) must be bodily incorporated into Oh
`“The test for obviousness is not whether the features of a secondary reference
`may be bodily incorporated into the structure of the primary reference.”
`Allied Erecting & Dismantling Co., Inc. v. Genesis Attachments, LLC, 825 F.3d 1373, 1381 (Fed. Cir. 2016)
`
`PO incorrectly treats Oh’s drawings as if they were to scale
`“[P]atent drawings do not define the precise proportions of the elements and
`may not be relied on to show particular sizes if the specification is completely
`silent on the issue.”
`Hockerson-Halberstadt, Inc. v. Avia Grp. Int’l, Inc., 222 F.3d 951, 956 (Fed. Cir. 2000)
`
`AMD Reply (Paper 27) at 26, 13
`
`44
`
`Demonstrative Exhibit 1047, 0044
`
`
`
`POSITA Is Not An Automaton
`Dr. Hatalis (Petitioner expert):
`
`AMD Reply (Paper 27) at 25; Ex-1039 (Hatalis Decl.) at ¶ 80
`
`45
`
`Demonstrative Exhibit 1047, 0045
`
`
`
`No Inconsistency Between Baker’s Design Rules And Oh
`
`Dr. Hatalis (Petitioner expert):
`
`Ex-2016 (Hatalis Reply Dep.) at 149:2-19, 210:16-22; Responding to PO Sur-
`reply at 22-29, providing full deposition context for PO cited passage
`
`46
`
`Demonstrative Exhibit 1047, 0046
`
`
`
`POSITA Would Know How To Implement Oh Using MOSIS Rules
`
`Oh’s
`Elements
`P10/P16
`
`P12/P14
`
`Baker/MOSIS
`Design Rules
`DR 6.2
`
`DR 6.2
`DR 3.4
`
`P18/P24
`
`DR 5.2
`
`P20/P22
`All contacts
`(C1-C12)
`
`DR 3.4
`DRs 5.1, 5.2,
`6.1, 6.2
`
`No Conflict Between Oh and Baker
`
`Dr. Hatalis applied DR 6.2 in his analysis of P10/P16. See Ex-1002, ¶74 (last bullet).
`
`Dr. Hatalis applied DR 6.2 in his analysis of P12/P14. See Ex-1002, ¶74 (last bullet).
`POSITA would not have applied DR 3.4 to non-gate overlap locations. Ex-1039, ¶74.
`If applied, PO’s expert admitted that DR 3.4 would lengthen P12/P14 to make them
`more “substantially oblong.” Ex-1040, 268:6-269:14.
`Oh discloses making polysilicon wider to accommodate contact landing (Ex-1039,
`¶77; Ex-1004, Figs. 3-4) and this is a well-known design technique (Ex-1039, ¶78).
`See P12/P14 above.
`DRs 5.1 & 6.1: POSITA would not have applied sizing rules for individual contacts
`(2λx2λ) to shared contacts. Ex-1039, ¶76; Exs-1031-1032.
`DR 5.2: See P18/P24 above. DR 6.2: See P10/P16 and P12/P14 above.
`
`AMD Reply (Paper 27) at 27-31
`
`47
`
`Demonstrative Exhibit 1047, 0047
`
`
`
`DR 3.4’s Active Extension Over Poly Ensures Capacitance For Transistor
`
`Dr. Hatalis (Petitioner expert reply declaration):
`
`AMD Reply (Paper 27) at 27-28; Ex-1004 (Oh) at Fig. 3 (annotated); Ex-1039 (Hatalis Decl.) at ¶ 72
`
`48
`
`Demonstrative Exhibit 1047, 0048
`
`
`
`DR 3.4 Inapplicable To Overlaps Without Transistor Channel
`
`Dr. Hatalis (Petitioner expert):
`
`AMD Reply (Paper 27) at 28-29; Ex-1004 (Oh) at Figs. 3-4 (annotated); Ex-1039 (Hatalis Decl.) at ¶ 74
`
`49
`
`Demonstrative Exhibit 1047, 0049
`
`
`
`PO Expert: Application of DR 3.4 Makes Active Regions More Oblong
`
`Oh:
`
`PO expert’s admission:
`
`AMD Reply (Paper 27) at 32-33; Ex-1004 (Oh) at Fig. 3 (annotated); Ex-1040 (Bagherzadeh Dep.) at 269:5-14
`
`50
`
`Demonstrative Exhibit 1047, 0050
`
`
`
`DR 5.1 And 6.1 Inapplicable Because C5/C6 Contact Poly And Active
`
`Dr. Hatalis (Petitioner expert):
`
`AMD Reply (Paper 27) at 29-30; AMD Petition (Paper 1) at 20-21; Ex-1004 (Oh) at Fig. 4 (annotated); Ex-1039 (Hatalis Decl.) at ¶ 76
`
`51
`
`Demonstrative Exhibit 1047, 0051
`
`
`
`DR 5.1 And 6.1 Dictate Size of Single Contact To Single Structure
`
`DR 5.1 governs size of
`contact to only Poly:
`
`DR 6.1 governs size of
`contact to only Active:
`
`AMD Reply (Paper 27) at 29-30; Ex-1005 (Baker) at 0144
`
`52
`
`Demonstrative Exhibit 1047, 0052
`
`
`
`PO’s “Design Rule Violation” Arguments Violate Two Basic Principles
`
`PO incorrectly assumes that the entirety of Baker (including every
`MOSIS design rule) must be bodily incorporated into Oh
`“The test for obviousness is not whether the features of a secondary reference
`may be bodily incorporated into the structure of the primary reference.”
`Allied Erecting & Dismantling Co., Inc. v. Genesis Attachments, LLC, 825 F.3d 1373, 1381 (Fed. Cir. 2016)
`
`PO incorrectly treats Oh’s drawings as if they were to scale
`“[P]atent drawings do not define the precise proportions of the elements and
`may not be relied on to show particular sizes if the specification is completely
`silent on the issue.”
`Hockerson-Halberstadt, Inc. v. Avia Grp. Int’l, Inc., 222 F.3d 951, 956 (Fed. Cir. 2000)
`
`AMD Reply (Paper 27) at 26, 13
`
`53
`
`Demonstrative Exhibit 1047, 0053
`
`
`
`PO’s Arguments Improperly Rely On Scaling Of Oh’s Drawings
`
`PO makes apple-to-orange comparison between unscaled figure and scaled figure
`
`Dr. Bagherzadeh (PO expert):
`
`POR (Paper 25) at 23-24; Argument presented in Reply, at 11-12, 18, 26, 29-31
`
`54
`
`Demonstrative Exhibit 1047, 0054
`
`
`
`PO’s Arguments Improperly Rely On Scaling Of Oh’s Drawings
`
`PO makes assumptions about spacing constraints from unscaled figure, but its own
`scaled figure shows no space constraint between P50/C7 and C6
`
`Unscaled
`
`Scaled
`
`POR (Paper 25) at 13, 22; Argument presented in Reply, at 11-12, 18, 26, 29-31
`55
`
`Demonstrative Exhibit 1047, 0055
`
`
`
`PO’s Arguments Improperly Rely On Scaling Of Oh’s Drawings
`
`PO assumes alignment between different layers are shown to scale
`
`PO Sur-Reply (Paper 35) at 27; Argument presented in Reply, at 11-12, 18, 26, 29-31
`
`56
`
`Ex-1004 (Oh) at 8:2-4
`
`Ex-1004 (Oh) at 8:38-40
`
`Demonstrative Exhibit 1047, 0056
`
`
`
`Baker Does Not Teach Away From 6-T CMOS SRAM
`
`Baker compares alternative designs without teaching away
`6-transistor CMOS SRAM larger but consumes less power; 4-transistor non-CMOS SRAM
`smaller but consumes more power
`
`6T CMOS Cell:
`
`4T Resistor/NMOS Cell:
`
`AMD Reply (Paper 27) at 22-23; Ex-1005 (Baker) at 0119, 0124-25
`
`57
`
`Demonstrative Exhibit 1047, 0057
`
`
`
`Overview
`
`Alleged Invention
`The “single local interconnect layer” limitation
`Claim Construction
`The art discloses the “single local interconnect layer”
`The “substantially oblong” limitations
`Claim Construction
`The art discloses the and teaches the “substantially oblong” limitations
`Motivation to Combine Oh + Baker
`Other Issues
`
`58
`
`Demonstrative Exhibit 1047, 0058
`
`
`
`Baker’s Publication Date
`
`Patent owner’s evidence
`Attorney declaration citing Wikipedia
`
`Petitioner’s evidence
`Declarations from author
`IEEE royalty records
`Declarations from librarian expert
`Copies of book from two university
`libraries, one with date stamp and one
`with serial number
`Declarations from two university
`library directors
`
`59
`
`Demonstrative Exhibit 1047, 0059
`
`
`
`Baker Ex-1005 Is Prior Art
`
`Ex-1005
`
`Ex-1036
`
`60
`
`Demonstrative Exhibit 1047, 0060
`
`
`
`Baker Ex-1005 Is Prior Art
`
`Ex-1005
`
`Ex-1036
`
`61
`
`Demonstrative Exhibit 1047, 0061
`
`
`
`Board Already Resolved Evidentiary Issue
`
`Paper 36 (Order Denying Motion to Strike):
`
`Order Denying Motion to Strike (Paper 36) at 6
`
`62
`
`Demonstrative Exhibit 1047, 0062
`
`
`
`File History: No Disclaimer of Overlapping Contacts
`
`Applicant distinguished Osada based on number of layers, not
`placement of contacts:
`
`AMD Reply (Paper 27) at 9; AMD Petition (Paper 1) at 23-29; Ex-1007 (FH) at 0502
`63
`
`Demonstrative Exhibit 1047, 0063
`
`
`
`File History: Did Not Distinguish Osada Over Overlapping Contacts
`
`Partially laterally
`displaced contacts
`
`Fully laterally
`displaced contacts
`
`AMD Petition (Paper 1) at 25; Ex-1009 (Osada, annotated) Fig. 2
`64
`
`Demonstrative Exhibit 1047, 0064
`
`
`
`Dr. Hatalis Confirmed >13:4 Calculation During Reply Deposition
`
`PO Sur-reply (Paper 35) at 34; Ex-2016 (Hatalis Dep.) at 244:2-12, responding
`to PO Sur-reply, at 34 providing full deposition context for PO cited passage
`
`65
`
`Demonstrative Exhibit 1047, 0065
`
`
`
`MOSIS Design Rules Are Scalable To Any Process Node Geometry
`
`AMD Petition (Paper 1) at 32-35; Ex-1005 (Baker) at 0140
`
`66
`
`Demonstrative Exhibit 1047, 0066
`
`
`
`Design Rules Are Not “All-Or-Nothing”
`
`Ex-1033 (contemporaneous
`patent on design rule checking):
`
`Dr. Hatalis
`(Petitioner
`expert):
`
`. . .
`
`AMD Reply (Paper 27) at 25;
`Ex-1039 (Hatalis Reply
`Declaration.) at ¶¶ 79-81; Ex-
`1033 at 3:1-5
`
`67
`
`Demonstrative Exhibit 1047, 0067
`
`
`
`U.S. No. 6,417,549 (“Oh”) Discloses SRAM Design
`
`AMD Petition (Paper 1) at 33; Ex-1004 (Oh) at Cover
`
`68
`
`Demonstrative Exhibit 1047, 0068
`
`
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