Trials@uspto.gov
`571-272-7822
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`Paper No. 13
`Date: December 2, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2020-00985
`Patent 6,651,134 B1
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`
`
`
`
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`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 13
`Date: December 2, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2020-00985
`Patent 6,651,134 B1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`IPR2020-00985
`Patent 6,651,134 B1
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`
`INTRODUCTION
`I.
`Advanced Micro Devices, Inc., (“Petitioner”) filed a Petition (Paper 1,
`“Pet.”) requesting institution of inter partes review of claims 1–21 (“the
`challenged claims”) of U.S. Patent No. 6,651,134 B1 (Ex. 1001,
`“the ’134 patent”). Monterey Research, LLC, (“Patent Owner”) filed a
`Preliminary Response. Paper 9 (“Prelim. Resp.”). After our email
`authorization, Petitioner filed a Preliminary Reply (Paper 10) and Patent
`Owner filed a Preliminary Sur-Reply (Paper 11). Pursuant to 35 U.S.C.
`§ 314 and 37 C.F.R. § 42.4(a), we have authority to determine whether to
`institute review.
`An inter partes review may not be instituted unless “the information
`presented in the petition . . . and any response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a). For the
`reasons set forth below, we conclude that Petitioner has shown a reasonable
`likelihood it will prevail in establishing the unpatentability of at least one
`challenged claim, and we therefore institute inter partes review.
`
`A. REAL PARTIES IN INTEREST
`Petitioner identifies itself and ATI Technologies ULC as real parties
`in interest. Pet. 3. Patent Owner identifies itself and IPValue Management as
`real parties in interest. Paper 5, 1.
`
`B. RELATED MATTERS
`The parties identify the following matters related to the ’134 patent:
`Monterey Research, LLC v. Qualcomm Inc., No. 1:19-cv-02083-NIQA-LAS
`(D. Del.); Monterey Research, LLC v. Nanya Tech. Corp., No. 1:19-cv-
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`02090-NIQA-LAS (D. Del.); Monterey Research, LLC v. Advanced Micro
`Devices Inc., No. 1:19-cv02149-NIQA-LAS (D. Del.); Monterey Research,
`LLC v. STMicroelectronics N.V., No. 1:20-cv-00089-NIQA-LAS (D. Del.);
`Monterey Research, LLC v. Marvell Tech. Grp. Ltd., No. 1:20-cv-00158-
`NIQA-LAS (D. Del.); and Marvell Semiconductor, Inc. v. Monterey
`Research, LLC, No. 3:20-cv-03296 (N.D. Cal.). Pet. 3; Paper 5, 1.
`The parties identify two additional adjudications, now complete,
`which involved the ’134 patent: In the matter of: Certain Static Random
`Access Memories and Products Containing Same, Inv. No. 337-TA-792
`(ITC); and Cypress Semiconductor Corp. v. GSI Tech., Inc., No. 3:13-cv-
`02013-JST and No. 3:13-cv-03757-JST (N.D. Cal). Pet. 3; Paper 5, 1–2.
`
`C. THE ’134 PATENT
` The ’134 patent is titled Memory Device with a Fixed Length Non
`Interruptible Burst. Ex. 1001, code (54). The patent discloses that “the data
`burst transfers of conventional memories can be interrupted and single
`access made,” and proposes a memory device “that has a fixed burst length.”
`Id. at 1:37–45.
`Figure 1 is reproduced below:
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`Ex. 1001, Fig. 1. Figure 1 depicts circuit 100 configured as a fixed burst
`memory, in which circuit 102 accepts external signals including external
`address signal ADDR_EXT, and “generate[s] the signal ADDR_INT as a
`fixed number of addresses in response to the signal CLK.” Id. at 3:21–22.
`The ’134 patent states that “[o]nce the circuit 102 has started generating the
`fixed number of addresses, the circuit 102 will generally not stop until the
`fixed number of addresses has been generated (e.g., a non-interruptible
`burst).” Id. at 3:25–28.
`The ’134 patent depicts two embodiments for circuit 102, in Figures 2
`and 3. Figure 2 is reproduced below:
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`Id. Fig. 2. Figure 2 shows burst counter 128 receiving signal CLK (a clock
`signal), signal ADV, and signal BURST, and providing signal
`BURST_CLK. “When the signal ADV is asserted, the burst counter 128 will
`generally present the signal BURST_CLK in response to the signal CLK.
`The signal BURST_CLK generally contains a number of pulses that has
`been programmed by the signal BURST.” Id. at 4:10–14. Figure 3 and the
`associated description disclose an alternative circuit, in which “counter 138
`may be configured to generate a number of addresses in response to the
`signals CLK, BURST[,] and ADV” and where “[t]he number of addresses
`generated by the counter 138 may be programmed by the signal BURST.”
`Id. at 4:29–31. The ’134 patent describes more generally that, “[w]hen the
`signal ADV is asserted, the circuit 100 will generally generate a number of
`address signals” and that “[t]he address signals will generally continue to be
`generated until the Nth address signal is generated.” Id. at 4:42–48.
`
`D. CHALLENGED CLAIMS
`Challenged claim 1 is reproduced below:
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`1. A circuit comprising:
`a memory comprising a plurality of storage elements each
`configured to read and write data in response to an
`internal address signal; and
`a logic circuit configured to generate a predetermined
`number of said internal address signals in response to
`(i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals, wherein said generation
`of said predetermined number of internal address signals
`is non-interruptible.
`Ex. 1001, 5:22–32. Independent claim 16 recites limitations similar to those
`of claim 1, expressed as means-plus-function elements. Id. at 6:20–30.
`Independent claim 17 recites limitations similar to those of claim 1,
`expressed as a “method of providing a fixed burst length data transfer.” Id.
`at 6:31–39. Claims 2–15 depend, directly or indirectly, from claim 1. Id.
`at 5:33–6:19. Claims 18–21 depend, directly or indirectly, from claim 17. Id.
`at 6:40–48.
`
`E. PRIOR ART AND ASSERTED GROUNDS
`Petitioner asserts the following grounds of unpatentability:
`Claim(s) Challenged 35 U.S.C. § References/Basis
`1–3, 8, 12, 13, 16, 17 102
`Wada1
`1–4, 8, 12–14, 16, 17 103
`Wada
`
`1–4, 8, 12–14, 16, 17 103
`
`4–7, 18–20
`
`103
`
`Wada, Barrett2
`
`Wada, Fujioka3
`
`
`1 U.S. Patent No. 6,115,280 (Ex. 1005).
`2 U.S. Patent No. 5,584,033 (Ex. 1010).
`3 U.S. Patent No. 6,185,149 (Ex. 1006).
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`Claim(s) Challenged 35 U.S.C. § References/Basis
`4–7, 18–20
`103
`Wada, Barrett, Fujioka
`
`9–10, 14, 21
`
`9–10, 14, 21
`11, 15
`
`11, 15
`
`103
`
`103
`103
`
`103
`
`Wada, Reeves4
`
`Wada, Barrett, Reeves
`Wada, Lysinger5
`
`Wada, Barrett, Lysinger
`
`Pet. i–iii, 5. Petitioner also relies on the Declaration of R. Jacob Baker,
`Ph.D., P.E. Ex. 1002.
`
`II. ANALYSIS
`A. LEVEL OF ORDINARY SKILL IN THE ART
`Petitioner proposes that a person of ordinary skill “would have had a
`bachelor’s degree in electrical or computer engineering, applied physics, or a
`related field, and at least two years of experience in design, development,
`and/or testing of memory circuits, related hardware design, or the equivalent,
`with additional education substituting for experience and vice versa.” Pet. 11
`(citing Ex. 1002 ¶ 43). Patent Owner does not dispute this definition of a
`person of ordinary skill. See generally Prelim. Resp. For purposes of this
`Decision, we adopt Petitioner’s proposed level of ordinary skill, as it appears
`to be consistent with the level of skill reflected by the Specification and in
`the asserted prior art references.
`
`
`4 U.S. Patent No. 6,226,755 (Ex. 1008).
`5 U.S. Patent No. 5,748,331 (Ex. 1009).
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`B. CLAIM CONSTRUCTION
`For an inter partes review petition filed after November 13, 2018, we
`construe claim terms “using the same claim construction standard that would
`be used to construe the claim in a civil action under 35 U.S.C. 282(b).”
`37 C.F.R. § 42.100(b) (2019). Petitioner submits that certain claim terms
`were construed by the ITC and a district court in prior proceedings, and
`contends that the following terms may warrant construction in this
`proceeding: “non-interruptible,” “means for reading data” and “means for
`generating a predetermined number of said internal address signals,”
`“external address signal,” “burst,” “internal address signal,” “logic circuit,”
`“predetermined number of [said] internal address signals,” “memory,” and
`“address signal.” Pet. 12–17. Patent Owner agrees that a number of terms
`were construed previously by a tribunal or were construed in a way agreed to
`by the parties involved, but asserts that only three terms require construction
`at this stage: “non-interruptible”; “predetermined number of [said] internal
`address signals”; and “means for generating a predetermined number of said
`internal address signals in response to (i) an external address signal, (ii) a
`clock signal and (iii) one or more control signals.” Prelim. Resp. 14–15.
`Other than as addressed below, we conclude that none of the claim
`terms requires express construction or discussion at this time. See Nidec
`Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017
`(Fed. Cir. 2017).
`
`1. “non-interruptible”
`As to “non-interruptible,” Petitioner submits that the prior art
`discloses the claim elements under Patent Owner’s construction—“cannot be
`stopped or terminated once initiated until the fixed number of internal
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`addresses has been generated.” Pet. 12; Prelim. Resp. 15. We proceed with
`that agreed-upon construction.
`
`2. “predetermined number of internal address signals”
`Petitioner and Patent Owner agree that the ITC expressly construed
`the term as “a fixed number of internal address signals for a burst access.”
`Pet. 16; Prelim. Resp. 15. Petitioner submits that the ITC further applied the
`term in a narrower manner, such that it did not read on prior art “fixing the
`burst length before a data transfer by using a mode register” because that
`burst length “could be programmed.” Pet. 16 (citing Ex. 1013, 24–25). Thus,
`Petitioner submits that a “predetermined number” under the ITC’s
`construction must be a number determined at manufacture time. Id. Thus,
`Petitioner maps the claims to the prior art asserted here using what it views
`as the ITC’s implied construction—“fixed or programmable at manufacture
`time using bond options or voltage levels.” Pet. 16.
`While Patent Owner disputes whether the ITC applied such a
`construction (Prelim. Resp. 15–16),6 it does not assert that Petitioner’s
`construction adversely affects the patentability analysis. We do not
`understand any dispute regarding institution to turn on whether we adopt
`Petitioner’s view that the predetermined number must be fixed at
`manufacture time. Moreover, such a construction would not appear to be
`consistent with dependent claim 5, which recites that the “fixed burst length
`is programmable.” Ex. 1001, 5:40–41. Thus, we do not adopt Petitioner’s
`
`
`6 The ITC decision states that the prior art did not disclose a “predetermined
`number” because it could “vary up to and including the very moment that
`the circuit begins reading or writing.” (Ex. 1013, 25) (emphasis added).
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`proposed construction and proceed with no express construction for
`“predetermined number.”
`
`3. “means for reading data . . . / means for generating a predetermined
`number of said internal address signals in response to (i) an external
`address signal, (ii) a clock signal and (iii) one or more control signals”
`The parties agree that the structure corresponding to the means for
`reading data is “memory array 104.” Pet. 13; Prelim. Resp. 17.
`The parties appear to agree that the structure corresponding to the
`means for generating a predetermined number of internal address signals is
`“burst address counter/register 102,” which may take the form shown in
`either Figure 2 or Figure 3. Pet. 14–15; Prelim. Resp. 17–18.
`We accept both proposed constructions for purposes of this decision.
`
`C. ANTICIPATION BY WADA
`Wada discloses a “semiconductor memory for operating in burst
`mode.” Ex. 1005, code (57). Petitioner relies on two aspects of Wada—its
`description of a first “conventional SRAM” and its “Second Embodiment.”
`See, e.g., Pet. 24–30 (identifying, for each challenged limitation, Wada’s
`disclosures of a “Conventional Embodiment” and “Second Embodiment”).
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`1. Wada’s disclosures
`Wada’s first conventional embodiment is depicted in Figure 12,
`reproduced below:
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`
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`Ex. 1005, Fig. 12. Figure 12 depicts burst counter unit 80 that starts with
`external address signal EXT.ADD and increments the address to create
`internal address signal INT.ADD, which is provided to decoder 2 to select
`word line 11 in memory cell array 1 for reading or writing data. Id. at 1:22–
`2:33, 3:5–32. Wada discloses that “every time the clock signal CLK is at a
`leading edge and the advance signal ADV is High,” the internal address “is
`incremented by the burst counter.” Id. at 3:5–9. Wada notes that speed
`improvement in the conventional embodiment described above is limited by
`the “operative delays resulting from the parts of the memory cell array” such
`as “delay times in the operations of the word lines.” Id. at 5:26–42.
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`Wada discloses a second conventional SRAM embodiment, depicted
`in Figure 15, reproduced below:
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`
`
`Id. Fig. 15. Figure 15 depicts memory cell array 1 where the word line 11
`selected for reading or writing is determined by memory address input signal
`MADD, which is sent to the decoder as internal address signal INT.ADD.
`Id. at 3:33–62. Figure 15 depicts output register 5, which retains data
`received from memory cell array 1 through sense amplifier 41. Id. at 3:42–
`4:13. Rather than using a burst counter to increment the address identifying a
`memory word line as in the first conventional embodiment, the second
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`conventional embodiment uses burst counter 8 to accept external chunk
`address signal EXT.CHA and increment it, producing internal chunk address
`signal INT.CHA, which allows multiplexer 7 to select from one of four
`blocks, 50 through 53, in output register 5, to provide to data input/output
`pin 9. Id. at 4:6–40.
`Wada describes that its second conventional embodiment avoids the
`operative delays involved in its first conventional embodiment. Id.
`at 5:43–45. Wada notes that the second conventional embodiment has the
`disadvantage of one clock-cycle delay between two burst outputs relating to
`two memory addresses. Id. at 5:50–53. That delay arises because data must
`be retained in the output register until output, preventing new data from
`being captured from the memory cell array. Id. at 5:11–24. Thus, Wada
`proposes an improved approach using burst mode that does not suffer from
`the operative delays of the conventional embodiment described above or the
`additional conventional embodiment with “data output interruptions”
`between bursts associated with different addresses. Id. at 5:66–6:7. Wada
`describes six enumerated embodiments that purport to address deficiencies
`of the prior art. Id. at 12:28–14:52 (First Embodiment), 14:53–16:50
`(Second Embodiment), 16:51–18:48 (Third Embodiment), 18:49–19:34
`(Fourth Embodiment), 19:35–20:60 (Fifth Embodiment), 20:61–38 (Sixth
`Embodiment).
`
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`Wada’s Second Embodiment is depicted in Figure 3, reproduced
`below:
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`
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`Id. Fig. 3. Figure 3 depicts a system sharing most components with
`Figure 15 (the second conventional embodiment) described above, but using
`multiple output registers 5A through 5K in place of single output register 5,
`and using additional multiplexers 60a through 63a to select among the
`multiple output registers. See id. at 14:63–15:2 (describing differences
`between the First Embodiment and Second Embodiment), 12:36–13:13
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`(describing differences between the second conventional embodiment and
`the First Embodiment). As with Wada’s second conventional embodiment,
`its Second Embodiment uses burst counter unit 8 to convert external chunk
`address signal EXT.CHA into internal chunk address signal INT.CHA,
`which controls which block of the selected output register is transferred to
`output pin 9. Id. at 15:66–16:3.
`Because the Second Embodiment uses multiple output registers, it can
`“execute data burst output in uninterrupted fashion.” Id. at 16:12–15.
`Wada’s statement in that regard refers to avoiding the one clock-cycle delay
`associated with the single output register used in the second conventional
`embodiment. See id. at 5:50–53 (describing that “a data-free period (an
`interruption in the flow of data output) is bound to occur between two burst
`outputs”), 14:28–33 (describing that using two output registers as in the First
`Embodiment “permit[s] uninterrupted burst output of data), 16:12–15
`(describing that the Second Embodiment “provides one advantage to that of
`the first embodiment, i.e., the ability to execute data burst output in
`uninterrupted fashion”).
`
`2. Unpatentability dispute
`Petitioner contends that both the first conventional embodiment and
`the Second Embodiment anticipate claim 1. Pet. 24–30. As to the claimed
`“logic circuit configured to generate a predetermined number of said internal
`address signals,” Petitioner identifies burst counter unit 80 in Wada’s first
`conventional embodiment (Pet. 26) and burst counter unit 8 in Wada’s
`Second Embodiment (Pet. 28). As described above, Wada teaches that those
`two circuits are “identical in structure” other than being provided with
`different external address signals. See Ex. 1005, 4:18–21 (describing
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`differences between the burst counter unit 80 and burst counter unit 8),
`12:36–39 (describing differences between the second conventional
`embodiment and the First Embodiment, not including any difference in burst
`counter unit 8), 14:63–15:5 (same, as between the First Embodiment and
`Second Embodiment), Figs. 1, 2 (showing the First Embodiment and Second
`Embodiment contain the same burst counter unit 8). Thus, Wada’s two
`embodiments identified by Petitioner for the claimed logic circuit offer no
`functional difference for our analysis of non-interruptibility.
`Patent Owner argues that the identified circuits do not satisfy the
`limitation “wherein said generation of said predetermined number of internal
`address signals is non-interruptible.” Prelim. Resp. 28–33. In particular,
`Patent Owner asserts that Petitioner has not identified a teaching that
`prevents interrupting a burst of address signals. Patent Owner reasons that,
`in Wada, “if the advance signal ADV is not High, then the burst counter will
`not increment an address, interrupting (and terminating) the process.” Id.
`at 30 (citing Ex. 1005, 2:55–60).
`Petitioner contends that “Wada discloses no method of terminating a
`burst before it has completed.” Pet. 28 (citing Ex. 1002 ¶¶ 71–73). In light of
`the ADV signal that Patent Owner identifies, however, we do not agree.
`Wada discloses that the burst counter increments with a leading edge of the
`clock signal only “when the advance signal ADV is brought High.”
`Ex. 1005, 2:56–59; accord id. at 3:5–9 (stating the internal address signal is
`incremented “every time the clock signal CLK is at a leading edge and the
`advance signal ADV is High”). Wada discloses that the advance signal is
`controlled by an external device. Id. at 1:65–66 (“An input pin 93 receives
`an advance signal ADV that is externally furnished.”). Thus, incrementing
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`Wada’s internal address depends on an external device maintaining the
`advance signal. Accordingly, we do not agree with Petitioner that Wada
`discloses no method of terminating a burst before it has completed.
`As to the Second Embodiment, Petitioner points to Wada’s statement
`that the operations “are carried out continuously,” which “allows the data
`corresponding to the address Am to be output uninterrupted in burst mode.”
`Id. at 30 (citing Ex. 1005 at 16:5–10) (emphasis omitted). Patent Owner
`challenges that reliance as misconstruing Wada’s disclosure. Prelim.
`Resp. 30–33. Patent Owner contends that, in Wada, “uninterrupted” means
`without delay between successive bursts, not without interruption within a
`burst. Id. We agree. As described above, Wada’s disclosure of a second
`conventional embodiment specifically points out a one clock-cycle delay,
`which Wada addresses as one of the primary improvements to its disclosed
`embodiments. See supra at 13. When Wada discusses avoiding a “data-free
`period (an interruption in the flow of data output),” it connects that goal with
`the gap “between two burst outputs, one relating to the current memory
`address An, the other associated with the next memory address Am.”
`Ex. 1005, 5:50–53. Thus, Wada’s goal of memory “working in burst mode
`. . . without causing data output interruptions” (id. at 6:3–7) or statements
`that its embodiments “permit uninterrupted burst output of data” (e.g., id. at
`14:32–33, 16:12–15) do not speak to possible interruptions within a
`particular burst, as would be relevant to the claim language.
`Because Wada discloses systems in which the internal address
`increments for burst operation only when an external signal (ADV) is
`maintained in a particular state, it does not disclose the claimed “generation
`of . . . internal address signals is non-interruptible.” To be sure, Wada’s
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`circuit could be used in a manner such that a burst is not interrupted, by
`maintaining the ADV signal high until a desired number of clock cycles
`have passed. But simply using the circuit in that manner does not mean the
`burst was non-interruptible as claimed. 7 The agreed construction requires
`that a non-interruptible burst “cannot be stopped or terminated once initiated
`until the fixed number of internal addresses has been generated.” Pet. 12
`(quoting Ex. 1011, 12–13). Such a limitation is not satisfied by a circuit in
`which burst operation depends on external control. The ’134 patent makes
`precisely that distinction over the prior art. Ex. 1001, 1:32–34 (“Data word
`bursts can be interrupted while in progress since conventional architectures
`support both burst and single access modes.”).
`Accordingly, we conclude Petitioner has not shown a reasonable
`likelihood it would prevail with respect to anticipation of claim 1 by Wada.
`Because independent claims 16 and 17 each require the same non-
`interruptible functionality, we reach the same conclusion for those claims.
`
`D. OBVIOUSNESS OVER WADA
`Petitioner submits that it would have been obvious to skilled artisans
`not to terminate a burst by Wada’s device. Pet. 47. Petitioner reasons that
`Wada itself justifies such a configuration “because Wada teaches against
`interrupting a burst.” Id. (citing Ex. 1005, 6:3–8). As discussed above,
`however, Wada does not address interruptions within a particular burst, only
`
`
`7 As one possible analogy, a claim requiring “a vehicle that may not exceed
`20 mph” would not read on a car that happens to be driven at 15 mph,
`absent some mechanism in the structure of the car that prevents it from
`exceeding 20 mph. Wada’s circuit achieves uninterrupted bursts only when
`external control signals maintain ADV high while internal addresses are
`generated. That is different from a non-interruptible circuit.
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`interruptions between successive bursts. See supra at 13, 15, 17; Prelim.
`Resp. 41–42. Thus, Wada’s disclosure of operating “without causing data
`output interruptions” refers to inter-burst interruptions and does not justify a
`modification that would render bursts non-interruptible.
`Petitioner provides no further reasoning to support that skilled artisans
`would have configured a system as Petitioner asserts. Thus, the Petition
`contains insufficient argument or evidence for us to conclude that Petitioner
`would ultimately prevail on obviousness of the challenged claims over Wada
`alone.
`
`E. OBVIOUSNESS OVER WADA AND BARRETT
`Petitioner submits also that it would have been obvious to a skilled
`artisan “to apply the teachings of Barrett to achieve an uninterruptible data
`transmission stream.” Pet. 52–53.
`Barrett discloses “a burst transfer protocol [that] allows pausing only
`at pre-determined, fixed intervals of n data words.” Ex. 1010, code (57).
`Barrett’s protocol allows sender or receiver devices to “cause transmission
`to pause” only after each burst of data. Id. It notes that “[t]he essential
`feature of burst communication is that the data transfer takes place at high
`speed and without interruption.” Id. at 1:64–66. Barrett also discloses that,
`“[i]n effect, allowing a pause at any point defeats the purpose of burst
`transmission, which is to send data a[s] rapidly as possible in an
`uninterrupted stream.” Id. at 2:39–41.
`Petitioner asserts that Barrett’s teachings are applicable to Wada
`because both are directed to high-speed data exchange. Pet. 51–52.
`Petitioner asserts that “applying Barrett’s teachings to Wada to render bursts
`uninterruptible would result in improved transmission efficiency by
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`minimizing overhead associated with terminating and initiating packets.” Id.
`at 52.
`Patent Owner challenges Petitioner’s reliance on Barrett, arguing that
`Barrett does not remedy what Patent Owner asserts is Wada’s failure to
`disclose “generating a predetermined number” of internal address signals.
`Prelim. Resp. 43. Of course, Petitioner asserts that Wada does disclose that
`limitation in each of the two asserted embodiments.
`For Wada’s conventional embodiment, Petitioner asserts that
`incrementing a k-bit portion of the EXT.ADD provided to burst counter
`unit 80 means that 2^k addresses are generated for INT.ADD, a number
`predefined by the number of bits separated from an n-bit EXT.ADD for
`incrementing. Pet. 26–27.
`For Wada’s Second Embodiment, Petitioner asserts that “the burst
`length is fixed by the choice of a four-input multiplexer and the choice of
`dividing the memory into four blocks (M0-M3).” Pet. 29. Petitioner points
`out that Wada’s Figure 4 shows that the internal chunk address INT.CHA
`takes on four successive values in response to burst incrementing the address
`Ac received as external chunk address signal EXT.CHA. Id. (citing
`Ex. 1005, Fig. 4).
`Patent Owner argues that both of Wada’s disclosures fail to satisfy the
`“predetermined number” limitation because either could be provided with
`signals to generate fewer than the maximum number of addresses. Prelim.
`Resp. 34–38.
`On the present record, considering Wada’s system as modified by
`Barrett leads us to conclude that the combination likely satisfies the
`“predetermined number” limitation. Modifying Wada to render a burst
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`uninterruptible would eliminate Wada’s dependency on external control
`signals to maintain a burst and ability to interrupt a burst prior to generating
`2^k addresses for INT.ADD. Whether in Wada’s first conventional
`embodiment or Second Embodiment, external signals would initiate the
`burst process, which would continue until generating the maximum number
`of internal addresses. Indeed, Patent Owner’s argument discussed above,
`that deasserting the ADV signal would interrupt a burst (see supra at 16),
`could not apply upon modifying Wada’s system such that continued
`generation of address signals in a burst is not interruptible by external
`signals. Accordingly, we do not agree with Patent Owner that, once
`modified, Wada’s system fails to disclose the “predetermined number”
`limitation.
`We conclude that, in light of Barrett’s teaching that “allowing a pause
`at any point defeats the purpose of burst transmission, which is to send data
`a[s] rapidly as possible in an uninterrupted stream” (Ex. 1010, 2:39–41),
`skilled artisans had reason to modify Wada’s conventional embodiment or
`Second Embodiment to remove the ability to interrupt burst-generation via
`external signals. Thus, the modified conventional embodiment and Second
`Embodiment would generate internal address or internal chunk addresses,
`respectively, such that their generation “cannot be stopped or terminated
`once initiated until the fixed number of internal addresses has been
`generated.” See Pet. 12 (claim construction).
`Accordingly, we conclude that Petitioner has shown a reasonable
`likelihood it will prevail with respect to obviousness of claim 1 over Wada
`and Barrett.
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`Patent Owner separately argues that Wada lacks the “means for
`generating a predetermined number of said address signals” of claim 16.
`Prelim. Resp. 38–41. That argument, addressing Petitioner’s assertions of
`both Wada’s conventional embodiment and Second Embodiment, addresses
`functionality regarding a “predetermined number” and asserts Wada
`discloses no structure to provide that functionality. Id. The functionality
`provided by the structures depicted in the ’134 patent’s Figures 2 and 3
`depends on how the blocks in those figures are configured. Compare
`Ex. 1001, Figs. 2–3, with id. at 3:62–4:40. We determine that the present
`record does not counsel for a determination regarding whether claim 16
`reads on a form of Wada as modified by Barrett, and leave such a
`determination for resolution during trial.
`
`F. ADDITIONAL OBVIOUSNESS GROUNDS
`Petitioner raises additional contentions for various dependent claims,
`drawing from further teachings of Fujioka, Reeves, and Lysinger. Pet. 53–
`72. Patent Owner challenges those contentions as suffering from the flaws
`asserted above regarding Wada. Prelim. Resp. 45–49. For the reasons
`discussed above addressing the combination of Wada and Barrett, Patent
`Owner’s arguments do not persuade us against institution.
`
`G. DISCRETIONARY DENIAL UNDER § 325(D)
`Patent Owner asserts that we should deny institution because Wada is
`substantially similar to Cowles, a reference applied during prosecution.
`Prelim. Resp. 24–28, 49–53. The core of Patent Owner’s argument asserts
`that both references relate to “shortening data transfer periods.” Id. at 25. In
`that regard, Patent Owner points to Cowles’s outputting data “in a
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`continuous stream while new rows of the memory are accessed” and Wada’s
`outputting “a plurality of target data items in burst mode without interruption
`therebetween.” Id. at 25–26 (quoting Ex. 2001, 2:7–9; Ex. 1005, 6:56–61).
`Petitioner points out that, during prosecution, Patent Owner relied on
`Cowles’s disclosure that a “continuous burst read operation” could be
`terminated. Prelim. Reply 2 (quoting Ex. 1004, 112). In contrast, Petitioner
`asserts, Wada provides for data “to be output uninterrupted in burst mode.”
`Id. (quoting Ex. 1005, 16:7–15).
`As discussed above, we do not agree with Petitioner’s view of Wada,
`in that Wada’s interruptions relate to periods between bursts. See supra
`at 17. That said, our determination to institute review depends on
`Petitioner’s assertion of obviousness over Wada and Barrett. Patent Owner
`asserts further that “Barrett does not cure Wada’s deficiencies because
`Barrett is directed towards external data transfers, not generation of internal
`address signals.” Prelim. Sur-Reply 3 (citing Ex. 1010, 4:18–32; Prelim.
`Resp. 43). But we agree with Petitioner that Barrett’s disclosures justify
`combination with Wada. See supra at 19. Patent Owner does not assert that
`the Examiner considered the combination of Wada and Barrett, but does
`assert that the combination does not “provide any disclosure meaningfully
`different from that of Cowles.” Prelim. Sur-Reply 3. In light of our
`determination that Barrett would have motivated a change to Wada’s device,
`we do not agree with Patent Owner. In that regard, Barrett’s disclosure of
`avoiding intraburst i
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