Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER PRELIMINARY RESPONSE
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`C. 
`
`I. 
`II. 
`
`Page
`Introduction ...................................................................................................... 1 
`Background ...................................................................................................... 2 
`A.  Overview Of The ’134 Patent. .............................................................. 2 
`III.  Claim Construction ........................................................................................ 13 
`A.  All Challenged Claims: “non-interruptible”. ...................................... 15 
`B. 
`All Challenged Claims: “predetermined number of [said]
`internal address signals”. ..................................................................... 15 
`Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ....................................................... 16 
`IV.  Summary Of Prior Art References ................................................................ 19 
`A.  Wada .................................................................................................... 20 
`1.  Wada Describes Two “Conventional” Ways Of
`Performing A Burst Operation. ................................................. 20 
`2.  Wada Purports To Improve On “Conventional” Burst
`Operations By Eliminating Data-Free Periods Between
`Bursts. ....................................................................................... 21 
`B.  Wada Is Substantially The Same As, And Cumulative To,
`Cowles. ................................................................................................ 24 
`V.  AMD Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 1.................................................................... 28 
`A.  Wada Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 28 
`B.  Wada Does Not Disclose “generating a predetermined number
`of said internal address signals”. ....................................................... 33 
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`B. 
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`Case IPR2020-00985
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`U.S. Patent No. 6,651,134
`1.  Wada’s “Conventional Embodiment” Does Not Disclose
`“generating a predetermined number of said internal
`address signals”. ....................................................................... 34 
`2.  Wada’s “Second Embodiment” Does Not Disclose
`“generating a predetermined number of said internal
`address signals”. ....................................................................... 37 
`C.  Wada Does Not Disclose “means for generating a
`predetermined number of said address signals”. ................................ 38 
`VI.  AMD Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 2.................................................................... 41 
`A.  AMD Did Not Establish That A Person Of Ordinary Skill In
`The Art Would Have Fixed Wada’s Deficiencies. ............................. 41 
`AMD’s Proposed Combination Of Wada And Barrett Does Not
`Meet Every Limitation Of Any Challenged Claim. ............................ 42 
`C.  AMD Did Not Establish That A Person Of Ordinary Skill In
`The Art Would Have Combined Wada And Barrett. .......................... 43 
`VII.  AMD Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 3.................................................................... 45 
`A.  AMD’s Proposed Combination Of Wada And Fujioka Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 45 
`AMD Did Not Establish That A Person Of Ordinary Skill In
`The Art Would Have Combined Wada, Barrett, And Fujioka. .......... 46 
`VIII.  AMD Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 4.................................................................... 47 
`A.  AMD’s Proposed Combination Of Wada And Reeves Does Not
`Meet Every Limitation Of Any Challenged Claim. ............................ 47 
`AMD Did Not Establish That A Person Of Ordinary Skill In
`The Art Would Have Combined Wada, Barrett, And Reeves. ........... 47 
`IX.  AMD Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 5.................................................................... 48 
`
`B. 
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`B. 
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`Page
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`B. 
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`X. 
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`Case IPR2020-00985
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`U.S. Patent No. 6,651,134
`A.  AMD’s Proposed Combination Of Wada And Lysinger Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 48 
`AMD Did Not Establish That A Person Of Ordinary Skill In
`The Art Would Have Combined Wada, Barrett, And Lysinger. ........ 49 
`The Board Should Exercise Its Discretion To Deny Institution. ................... 49 
`A. 
`The Becton Factors Favor Denial Of Institution. ................................ 51 
`1. 
`
`Factor (a): Similarities and material differences in
`asserted art and prior art. ......................................................... 51 
`
`2. 
`
`Factors (b), (c) and (d): Cumulative nature of art, extent
`art evaluated, and overlap in arguments and manner of
`reliance. ..................................................................................... 51 
`3. 
`Factor (e): Establishing Examiner error. ................................. 52 
`4. 
`Factor (f): Additional evidence and facts. ................................ 52 
`XI.  Conclusion ..................................................................................................... 53 
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases 
`Advanced Bionics, LLC v. MED-EL Elektromedizinische Geräte GmbH,
`IPR2019-01469, Paper 6 (PTAB Feb. 13, 2020) (precedential) ............ 49, 50
`Becton, Dickinson & Co. v. B. Braun Melsungen AG,
`Case IPR2017-01586, Paper 8 (PTAB Dec. 15, 2017) (designated
`informative) ............................................................................................ 50, 51
`NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc.,
`IPR2018-00752, slip op. at 11-12 (Paper 8) (PTAB Sept. 12, 2018)
`(precedential) ................................................................................................. 53
`Pers. Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) ....................................................................... 19
`Vivid Techs., Inc. v. Am. Sci. & Eng'g, Inc.,
`200 F.3d 795, 803 (Fed. Cir. 1999) ............................................................... 13
`Statutes 
`35 U.S.C. § 325(d) ..................................................................................................... 2
`Regulations 
`37 C.F.R. § 42.104(b)(4) .......................................................................................... 19
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`
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`All emphases are added unless otherwise indicated.
`
`This paper includes color illustrations and should be viewed in color.
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`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
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`Exhibit No.
`2001
`2002
`
`DESCRIPTION
`U.S. Patent No. 5,729,504 to Cowles (“Cowles”)
`U.S. Patent No. 6,289,138 to Yip (“Yip”)
`
`All citations to specific pages of exhibits follow the pagination added to those
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`I.
`Introduction
`
`The Board should deny Advanced Micro Devices, Inc.’s (“AMD” or
`
`“Petitioner”) petition against Claims 1-21 (collectively, “the Challenged Claims”)
`
`of U.S. Patent No. 6,651,134 (Ex-1001, the “’134 Patent”). The ’134 Patent claims
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`novel and non-obvious designs and procedures for improving the efficiency and
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`speed of memory devices conducting “burst” operations to access multiple memory
`
`locations using a single address. Numerous tribunals have confirmed the validity of
`
`the ’134 Patent—first the United States Patent and Trademark Office (“PTO”) in
`
`issuing the ’134 Patent in 2000, and then the International Trade Commission
`
`(“ITC”) in the course of an Investigation. AMD’s Petition does not establish a
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`reasonable likelihood that the Challenged Claims are anticipated or obvious and that
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`they should be cancelled.
`
`First, though AMD raises a host of grounds, all ultimately depend on AMD’s
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`misreading of a single primary reference: U.S. Patent No. 6,115,280 to Wada (Ex-
`
`1005, “Wada”). But AMD does not meet its burden of establishing a reasonable
`
`likelihood that the Challenged Claims are anticipated or rendered obvious by Wada
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`alone. The Challenged Claims recite operations that generate a predetermined
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`number of internal addresses and ensure that the generation of those internal
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`addresses is non-interruptible. Wada does not teach those limitations, and AMD
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`misrepresents Wada’s disclosure in its attempt to address Wada’s shortcomings. All
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`U.S. Patent No. 6,651,134
`of AMD’s subsequent grounds—including various combinations of Wada with U.S.
`
`Patent Nos. 5,584,033 (“Barrett”); 6,185,149 (“Fujioka”); 6,226,755 (“Reeves”);
`
`and 5,748,331 (“Lysinger”)—depend on Wada’s deficient disclosure, and fail for
`
`the same reasons. Those secondary references do not remedy Wada’s shortcomings.
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`Moreover, AMD fails to show that a person of ordinary skill in the art would have
`
`had reason—absent impermissible hindsight—to combine Wada with Barrett,
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`Fujioka, Reeves, and/or Lysinger.
`
`Second, the Board should exercise its discretion to deny institution under 35
`
`U.S.C. § 325(d). Wada is substantially identical and/or cumulative to prior art the
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`Patent Office previously considered and rejected during the prosecution of the ’134
`
`Patent. The Board need not revisit arguments that the Patent Office has already
`
`rejected.
`
`Accordingly, Patent Owner Monterey Research, LLC (“Monterey”)
`
`respectfully requests that the Board deny institution.
`
`II. Background
`A. Overview Of The ’134 Patent.
`
`The ’134 patent teaches a novel design and operation for memory devices,
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`such as a Static Random Access Memory (SRAM) or a Dynamic Random Access
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`Memory (DRAM), operating in burst mode. In burst mode, a memory device can
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`provide data from multiple locations in the device using a single external address,
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`U.S. Patent No. 6,651,134
`thereby increasing efficiency and reducing activity on address and control buses
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`connected to the device. (Ex-1001, 1:11-13.) Before the invention of the ’134
`
`Patent, burst mode in both conventional SRAMs and DRAMs had drawbacks,
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`particularly a susceptibility to interruptions. For example, in a conventional SRAM,
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`burst mode could be “started and stopped in response to a control signal.” (Ex-1001,
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`1:15-18.) And using burst mode in a conventional DRAM was “difficult because of
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`the need to refresh” data within the memory cell, which might necessitate
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`interrupting the burst application and thus greatly lengthen the amount of time
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`required for accessing data. (Ex-1001, 1:20-36.) Because burst mode data transfers
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`in both conventional SRAMs and DRAMs could be interrupted, the availability of
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`data, address, and control busses within the memory device varied, which
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`“complicate[d] the design of systems with shared data, address, and control busses.”
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`(Ex-1001, 1:38-43.) As such, the ’134 Patent explains that it “would be desirable to
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`have a memory device that has a fixed burst length.” (Ex-1001, 1:44-45.)
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`To that end, the inventor of the ’134 Patent proposed an integrated circuit
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`comprising a memory and a logic circuit which fixes the length of the burst and
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`renders it non-interruptible. (Ex-1001, Abstract, 1:44-45.) The inventions of the
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`’134 Patent present a number of benefits and advantages, including to:
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`(i) give network customers who typically burst large data lengths the
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`ability to set a fixed burst length that suits particular needs; (ii) have
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`U.S. Patent No. 6,651,134
`non-interruptible bursts; (iii) free up the address bus and control bus for
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`a number of cycles; (iv) provide programmability for setting the burst
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`length by using DC levels [Vss or Vcc] on external pins; (v) hide
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`required DRAM refreshes inside a known fixed burst length of data
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`words; and/or (vi) operate at higher frequencies without needed
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`interrupts to perform refreshes of data.
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`(Ex-1001, 1:58-67.) Fixing the burst length permits the ’134 Patent’s novel circuit
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`to “allow shared usage of data, address and control busses,” by “generally free[ing]
`
`up the address bus and control bus for a known number of cycles,” e.g., during the
`
`burst mode, and therefore “may provide a more reliable and/or accurate burst than
`
`is possible with multiple chips.” (Ex-1001, 3:54-61.)
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`Among other things, the ’134 Patent provides a novel circuit integrating a
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`memory device with a logic circuit, thereby providing a fixed burst length and
`
`ensuring non-interruptible generation of a predetermined number of internal
`
`addresses. Independent Claim 1 is illustrative:
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`A circuit comprising:
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`a memory comprising a plurality of storage elements each configured
`
`to read and write data in response to an internal address signal; and
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`a logic circuit configured to generate a predetermined number of said
`
`internal address signals in response to (i) an external address signal,
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`U.S. Patent No. 6,651,134
`(ii) a clock signal and (iii) one or more control signals, wherein said
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`generation of said predetermined number of internal address signals is
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`non-interruptible.
`
`(Ex-1001, Claim 1.)
`
`The ’134 Patent illustrates aspects of the claims using four exemplary figures.
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`For example, Figure 1, reproduced below, presents a circuit 100 comprising “a
`
`[logic] circuit 102 and a memory array” 104:
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`Ex-1001, Figure 1 (annotated1)
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`
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`1 All annotations in drawings are added.
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`U.S. Patent No. 6,651,134
`Circuit 102 includes inputs for receiving signals, including, for example, an
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`external address signal (“ADDR_EXT” 106); an address load control signal
`
`(“LOAD” 108); a clock signal (“CLK” 110); a control signal (“ADV” 112); or a
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`configuration signal (“BURST” 114), as shown in Fig. 1, reproduced below.
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`(Ex-1001, Figure 1.)
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`
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`The external address signal ADDR_EXT may be “n-bits wide,” (Ex-1001,
`
`2:56-58), and presents an “initial address,” which “may determine the initial
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`location where data transfers to and from the memory 104 will generally begin.”
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`(Ex-1001, 3:1-4.) Circuit 100 loads the initial address presented by the external
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`address signal ADDR_EXT in response to the address load control signal LOAD.
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`(Ex-1001, 2:66-3:2.)
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`Circuit 100 “may be configured to transfer a fixed number of words to or
`
`from the memory 104 in response to signals ADV, CLK, and R/Wb.” (Ex-1001,
`
`3:6-8.) For example, the ’134 Patent states:
`
`When the signal ADV is asserted, the circuit 100 will generally begin
`
`transferring a predetermined number of words. The transfer is
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`generally non-interruptible. In one example, the signal ADV may
`
`initiate the generation of a number of addresses for presentation as the
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`signal ADDR_INT. (Ex-1001, 3:6-13.)
`
`
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`Alternatively, the ’134 Patent notes that “signals ADV and LOAD may be, in
`
`one example, a single signal (e.g., ADV/LDb).” (Ex-1001, 3:14-15.) In that
`
`embodiment, when the signal ADV/LDb is in a first state, the “circuit 102 will
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`generally load an address presented by the signal ADDR_EXT as an initial address.”
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`(Ex-1001, 3:17-19.) Conversely, when the signal ADV/LDb is in a second state:
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`“[T]he circuit 102 may be configured to generate the signal
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`ADDR_INT as a fixed number of addresses in response to the signal
`
`CLK. The signal ADDR_INT may be, in one example, an internal
`
`address signal. The signal ADDR_INT may be n-bits wide. Once the
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`circuit 102 has started generating the fixed number of addresses, the
`
`circuit 102 will generally not stop until the fixed number of addresses
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`U.S. Patent No. 6,651,134
`has been generated (e.g., a non-interruptible burst).” (Ex-1001, 3:20-
`
`28.)
`
`
`
`The ’134 Patent states that the fixed number of addresses generated by the
`
`circuit 102 in response to the signals CLK and ADV/LDb may be programmed by,
`
`for example, the configuration signal BURST. (Ex-1001, 3:30-34.) The signal
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`BURST may be generated, for example, by “(i) using bond options, (ii) voltage
`
`levels applied to external pins, or (iii) other appropriate signal generation means.”
`
`(Ex-1001, 3:34-36.) Figure 1, reproduced below, shows the generation of the signal
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`ADDR_INT as a fixed number of addresses as programmed by the signal BURST.
`
`
`
`(Ex-1001, Figure 1.)
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`U.S. Patent No. 6,651,134
`In one embodiment, after receiving the initial starting address from
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`ADDR_EXT, circuit 102 is configured to increment subsequent addresses for a
`
`specific number of times—thereby generating a predetermined number of internal
`
`addresses—as programmed by the signal BURST. For example, Figure 2,
`
`reproduced below, presents a detailed block diagram of the circuit 102 embodied as
`
`an address counter register 126 and a burst counter 128.
`
`(Ex-1001, Figure 2.)
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`
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`In one embodiment of the ’134 Patent, the address counter register 126
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`receives the signals ADDR_EXT, LOAD, and CLK, while the burst counter 128
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`receives the signals ADV and BURST. (Ex-1001, 3:65 – 4:2.) The burst counter
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`128 presents a signal BURST_CLK—which contains “a number of pulses that has
`
`been programmed by the signal BURST”—to the address counter 126 when the
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`signal ADV is asserted. (Ex-1001, 4:10-14.) The address counter register 126 loads
`
`an initial address—identifying the starting point for accessing the memory array—
`
`by receiving the external address signal ADDR_EXT and asserting the signal
`
`LOAD. (Ex-1001, 4:6-8.) The address counter register 126 then “increment[s] an
`
`address in response to the signal BURST_CLK,” for a number of times that equals
`
`the number of pulses in the signal BURST_CLK as programmed by the signal
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`BURST. (Ex-1001, 4:8-10.) As such, the predetermined number of internal
`
`addresses is generated by incrementing the initial address based on the number of
`
`pulses from the signal BURST_CLK.
`
`In this way, this embodiment of the ’134 Patent generates a predetermined
`
`number of internal address signals. For example, when the signal ADV is asserted,
`
`the circuit 100 will “generate a number of address signals, for example, N, where N
`
`is an integer” which address signals “will generally continue to be generated until
`
`the Nth address signal is generated.” (Ex-1001, 4:42-48.)
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`For example, Figure 5a, reproduced below, illustrates an operation for a four-
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`word fixed burst memory. The circuit first loads an initial address (portions 150,
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`154, and 158), and starting with that initial address, transfers a fixed number of
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`words—4 words in Figure 5a—as shown in line DQ. (Ex-1001, 4:54-59.) During
`
`the transfer of the fixed number of words, the address and control buses, including
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`ADDR, CEB, and R/WB, are “generally available to other devices” for a known
`
`number of cycles, shown in in portions 152, 156, and 160 of Figure 5a. (Ex-1001,
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`4:60-64.)
`
`(Ex-1001, Figure 5A.)
`
`
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`The non-interruptible generation of internal address signals presents a
`
`significant advancement over the prior art. Specifically, fixing the burst length in
`
`advance and generating a predetermined number of internal address signals
`
`“generally frees up the address bus and control bus for a known number of cycles.”
`
`(Ex-1001, 3:56-58.) For memory devices that share the address and control buses,
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`the invention of the ’134 Patent provides “a more reliable and/or accurate burst than
`
`is possible with multiple chips.” (Ex-1001, 3:58-61.) The ’134 Patent, therefore,
`
`presents an advantage over prior art solutions that merely read or write a preset
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`number of data words or presented options for continuously reading or writing data
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`from the memory device.
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`For example, the United States Patent and Trademark Office (“PTO”) allowed
`
`the ’134 Patent over prior art such as US Patent No. 6,289,138 to Yip et al, (Ex-
`
`2002, “Yip”), that prevent interrupting read or write bursts until a preset number of
`
`data words has been transferred, which “is not the same as generating a
`
`predetermined number of internal address signals that is non-interruptible.” (Ex-
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`1004, 0065)
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`Similarly, the ’134 Patent was allowed, and provides advantages, over prior
`
`art that merely presented methods for continuously bursting data in and/or out of the
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`memory. For example, the PTO allowed the ’134 Patent over U.S. Patent No.
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`5,729,504 to Cowles (Ex-2001 “Cowles”), which was “directed to a continuous burst
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`EDO memory device,” and specifically directed to “an ability to access a second row
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`of memory while bursting data out of a first row (a so-called “continuous BEDO,”
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`or “CBEDO” architecture . . . ).” (Ex-1004, ¶¶0107-0108). But as the applicant
`
`argued, the “ability to access a second row of memory while bursting data out of a
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`first row has little or nothing to do with whether a ‘burst’ can be interrupted.” (Ex-
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`1004, ¶¶0107-0108). Moreover, the examiner agreed that Cowles’ continuous burst
`
`architecture did not disclose the claim limitation “wherein said generation of said
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`predetermined number of internal address signals is non-interruptible” in the Notice
`
`of Allowance:
`
`“[T]he prior art discloses an integrated circuit memory device which
`
`can operate at high data speeds. The integrated circuit memory can
`
`output data of a “fixed burst length” in a continuous stream while rows
`
`of the memory are accessed. However, to terminate a continuous burst
`
`read operation, the WE signal merely has to transition high prior to a
`
`falling edge of the CAS signal (see, for example, Cowles). [T]hus prior
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`art of record does not teach or fairly suggest the non-interruptible
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`generation of a predetermined number of internal address signals.”
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`(Ex-1004, ¶0172 (emphasis in original).)
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`III. Claim Construction
`
`The Board need only construe terms “that are in controversy, and only to the
`
`extent necessary to resolve the controversy.” Vivid Techs., Inc. v. Am. Sci. & Eng'g,
`
`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Certain terms of the ʼ134 Patent, including
`
`“non-interruptible,” were previously construed or agreed upon by the parties in two
`
`separate actions: (1) Cypress Semiconductor Corp. v. GSI Tech., Inc., No. 3-13-cv-
`
`03757, ECF No. 57 (N.D. Cal. July 29, 2014) (“Cypress District Court litigation”);
`
`and (2) Investigation No. 337-TA-792 (“792 Investigation”), initiated by Cypress
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`Semiconductor Corp., the previous assignee of the ’134 Patent. The prior
`
`constructions include:
`
`Term
`
`“burst”
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`Construction
`
`“a number of words transferred as a
`
`group” (Ex-1011, 0016)
`
`“an address signal that is generated
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`“internal address signal”
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`within the circuit claimed by the
`
`“external address signal”
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`“logic circuit”
`
`“memory”
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`“address signal”
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`preamble” (Ex-1011, 0018)
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`“an address signal that originates
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`outside of the circuit” (Ex-1011, 0015)
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`“a circuit that is designed to perform
`
`one or more logic operations or to
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`represent logic functions” (Ex-1011,
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`0020)
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`“addressable storage” (Ex-1012, 0004-
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`0005)
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`“a signal for determining the address
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`location in the memory array from
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`which data is read to or to which data is
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`written” (Ex-1012, 0005)
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`U.S. Patent No. 6,651,134
`The Board need consider only three terms in independent Claims 1, 16, and
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`17 to deny institution: “non-interruptible;” “predetermined number of [said] internal
`
`address signals;” and “means for generating a predetermined number of said internal
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`address signals in response to (i) an external address signal, (ii) a clock signal and
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`(iii) one or more control signals.”
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`A. All Challenged Claims: “non-interruptible”.
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`In the 792 Investigation, the parties agreed that “non-interruptible” means
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`“cannot be stopped or terminated once initiated until the fixed number of internal
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`addresses has been generated.” (Ex-1011, 0012-0013.) AMD appears to adopt this
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`construction, as it purported to apply its prior art to the claims using this
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`construction. (Petition, 12.) However, AMD’s prior art does not disclose the “non-
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`interruptible” limitation under its proposed construction, as discussed below
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`B. All Challenged Claims: “predetermined number of [said] internal
`address signals”.
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`The Administrative Law Judge in the 792 Investigation construed this term to
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`mean “a fixed number of internal address signals for a burst access.” (Ex-1011, 17.)
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`AMD asserts, incorrectly, that the International Trade Commission further narrowed
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`that construction to imply that it meant “fixed or programmable at manufacture time
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`using bond options or voltage levels.” (Petition, 16.) But the Commission did not
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`narrow the ALJ’s construction. In fact, the words “programmable,” “manufacture
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`time,” “bond options,” and “voltage levels” do not appear anywhere in the
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`Commission’s analysis of the ’134 Patent. (Ex-1013, 0024-0029.) Rather, the
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`Commission simply applied the ALJ’s construction to the proffered prior art and
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`found it failed to disclose the claim limitation as construed. For example, the
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`Commission noted that the “asserted claims require a burst length that is
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`predetermined, by definition a burst length fixed before the burst begins.” (Ex-1013,
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`25.) The prior art proffered by the Respondent, however, undisputedly did not
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`“disclose a burst length that is fixed before burst begins.” (Ex-1013, 25.) As such,
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`there is no basis in the 792 Investigation for AMD’s purported “implied
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`construction,” nor does AMD provide any intrinsic support for such a construction,
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`and it should be rejected. However, AMD’s prior art does not disclose the
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`“predetermined number” limitation under any of its proposed constructions, as
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`discussed below.
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`C. Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in response
`to (i) an external address signal, (ii) a clock signal and (iii) one or
`more control signals”.
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`Claim 16 of the ’134 Patent includes two means-plus-function limitations:
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`“means for reading data from and writing data to a plurality of storage elements in
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`response to a plurality of internal address signals”; and “means for generating a
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`predetermined number of said internal address signals in response to (i) an external
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`address signal, (ii) a clock signal and (iii) one or more control signals.” (Ex-1001,
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`Claim 16.)
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`16
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`The function for the “means for reading data from and writing data to a
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`plurality of storage elements in response to a plurality of internal address signals”
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`limitation is “reading data from and writing data to a plurality of storage elements in
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`response to a plurality of internal address signals.” Monterey agrees with AMD that
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`the corresponding structure is the memory array 104. (Petition, 13-14; Ex-1001, Fig.
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`1, 2:34-38, 2:44-49.) This limitation is not in controversy.
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`The function for the “means for generating a predetermined number of said
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`internal address signals in response to (i) an external address signal, (ii) a clock
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`signal and (iii) one or more control signals” is “generating a predetermined number
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`of said internal address signals in response to (i) an external address signal, (ii) a
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`clock signal and (iii) one or more control signals.” The ’134 Patent discloses a
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`circuit 102 as the corresponding structure that can perform this function. For
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`example, Figure 2 discloses a circuit 102 comprising an address counter register 126
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`and burst counter 128. Similarly, Figure 3 discloses a circuit 102 comprising a
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`counter 138 and latch 134. Both Figures are reproduced below.
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`
`
`
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`(Ex-1001, Figure 2.)
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`(Ex-1001, Figure 3.)
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`According to the ’134 Patent, the circuit 102 depicted in Fig. 2 “may comprise
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`an address counter register 126 and a burst counter 128.” (Ex-1001, 3:63-65.) The
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`address counter register 126 “generally receives the signals ADDR_EXT, LOAD,
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`and CLK” (Ex-1001, 3:65-66); “may be configured to present the signal
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`ADDR_INT” (Ex-1001, 3:67-4:1); and “may be configured to increment an address
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`in response to the signal BURST_CLK.” (Ex-1001, 4:9-10.) The burst counter 128
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`may present a signal BURST_CLK which “generally contains a number of pulses
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`that has been programmed by the signal BURST.” (Ex-1001, 4:13-14.) Similarly,
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`the circuit 102 depicted in Fig. 3 “may comprise a latch 134, a multiplexer 136, and
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`a counter 138.” (Ex-1001, 4:16-18.) The counter 138 receives the “signals ADV,
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`CLK and BURST,” (Ex-1001, 4:28-29), and “may be configured to generate a
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`number of addresses in response to the signals CLK, BURST and ADV.” (Ex-1001,
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`4:30-31.) According to the ’134 Patent, the “number of addresses generated by the
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`counter 138 may be programmed by the signal BURST.” (Ex-1001, 4:31-33.)
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`U.S. Patent No. 6,651,134
`AMD’s prior art does not disclose this limitation or its structural equivalents under
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`AMD’s proposed construction, as discussed below.
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`IV. Summary Of Prior Art References
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`AMD raises a host of grounds, all of which rely primarily upon Wada:
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`Ground
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`Reference(s)
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`Challenged Claims
`
`1
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`2
`
`2a
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`3
`
`3a
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`4
`
`4a
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`5
`
`5a
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`Wada
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`1-3, 8, 12-13, 16, 17
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`Wada + POSITA knowledge
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`1-4, 8, 12-16, 17
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`Wada + Barrett
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`Wada + Fujioka
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`1-4, 8, 12-16, 17
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`4-7, 18-20
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`Wada + Barrett + Fujioka
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`4-7, 18-20
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`Wada + Reeves
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`9-10, 14, 21
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`Wada + Barrett + Reeves
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`9-10, 14, 21
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`Wada + Lysinger
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`11, 15
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`Wada + Barrett + Lysinger
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`11, 15
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`AMD has the burden to show that every limitation of the challenged claims is
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`in the prior art, and that a person of ordinary skill in the art would have combined
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`Wada with the knowledge of a person of ordinary skill in the art, Barrett, Fujioka,
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`Reeves, and Lysinger. Pers. Web Techs., LLC v. Apple, Inc., 848 F.3d 987, 991
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`(Fed. Cir. 2017); 37 C.F.R. § 42.104(b)(4).
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`AMD does not satisfy any of its burdens. Wada neither anticipates nor renders
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`obvious the “generating a predetermined number of said internal address signals” or
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`the “wherein said generation of said predetermined number of internal address
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`signals is non-interruptible” limitations recited in independent Claims 1 and 17, from
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`which all other challenged claims depend. AMD’s assertion that a person of
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`ordinary skill in the art would have combined Wada with Barrett, Fujioka, Reeves,
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`or Lysinger rests on impermissible hindsight. And in any event, none of AMD’s
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`references alone or in combination disclose the “generating a predetermined number
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`of said internal address signals” or the “wherein said generation of said
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`predetermined number of internal address signals is non-interruptible” limitations.
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`For at least these reasons, AMD has not established a reasonable lik