0
`United States Patent
`
`[19]
`
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`USOOS784331A
`
`[11] Patent Number:
`
`5,784,331
`
`
`Lysinger
`[45] Date of Patent:
`Jul. 21, 1998
`
`[54] MULTIPLE ACCESS MEMORY DEVICE
`
`5,526,320
`
`6/1996 Zagar et a1.
`
`......................... 365/2335
`
`[75]
`
`Inventor: Mark A. Lysinger. Carrollton. Tex.
`,
`,
`,
`
`[73] Assrgnee:
`
`(Sglimolmggg Microelectronics, Inc..
`
`[21] APp1‘ No.2 775’664
`[22]
`Filed:
`Dec. 31, 1996
`
`
`6
`
`..................... GllC 8/00
`Int. Cl.
`[51]
`[52] US. Cl. ................................ 365/230.06; 365/ 189.05;
`.
`365/230-08
`[58] Fleld of Search ......................... 365/230.06. 230.08.
`355/13905
`
`[56]
`
`.
`References Cited
`US. PATENT DOCUMENTS
`
`6/19% Slemmer et al.
`5,124,951
`.................. 365030.06
`
`5,261,064 11/1993 Wylarld .................... 395/400
`g’ggég 5:33: I??? 6:211
`ggggggg
`
`6/1994 CE; “e......l.5...
`2'........ 395/400
`5519.759
`
`5.453.957
`9/1995 Norris et a].
`365030.04
`11/1995 Haraguchi .......................... 365/230.06
`5,469,391
`
`Primary Examiner—Son T. Dinh
`Attome , A em, or Firm—David V. Carlson; Theodore E.
`
`Galanthyay; iisa K. Jorgenson
`
`[57]
`
`ABSTRACT
`
`A memory circuit has a plurality of data storage locations
`and an address associated with each data storage location. A
`first decoded address storage circuit stores a first decoded
`memory address and outputs the stored first decoded
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and outputs the
`stored second decoded memory address. An address access
`circuit is coupled to the output of the first decoded address
`storage circuit and accesses the data storage location asso-
`ciated with the first decoded memory address in response to
`the first decoded memory address being output from the first
`decoded address storage circuit. A control circuit is coupled
`to the first decoded address storage circuit for controlling the
`transfer of decoded memory address information from the
`second decoded address storage circuit to the first decoded
`address Storage Circuit
`
`13 Claims, 22 Drawing Sheets
`
`69\\
`
`80
`
`FROM MEMORY BLC<0sy>
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`48 35%
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`(FIG. 22)
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`GLBOUBQL
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`05
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`$5
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`RESET
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`.95
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`
`Petitioner AMD Ex-1009, 0001
`
`—
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`(FIG 3)
`
`88
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`COLUMN
`ADDRESS BURST
`COUNTER
`
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`
`31“
`
`40
`
`Petitioner AMD Ex-1009, 0001
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 1 of 22
`
`5,784,331
`
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`
`Petitioner AMD Ex-1009, 0002
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 2 of 22
`
`5,784,331
`
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`Petitioner AMD EX-1009, 0003
`
`Petitioner AMD Ex-1009, 0003
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 3 of 22
`
`5,784,331
`
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`
`Petitioner AMD Ex-1009, 0004
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 4 of 22
`
`5,784,331
`
`9...
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`
`

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`US. Patent
`
`Jul. 21, 1998
`
`Sheet 5 of 22
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`Petitioner AMD Ex-1009, 0006
`
`Petitioner AMD Ex-1009, 0006
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 6 of 22
`
`5,784,331
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`
`Petitioner AMD Ex-1009, 0007
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 7 of 22
`
`5,784,331
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`Petitioner AMD Ex-1009, 0008
`
`

`

`US. Patent
`
`Jul. 21, 1993
`
`Sheet 8 of 22
`
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`
`5,784,331
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`
`Petitioner AMD EX-1009, 0009
`
`Petitioner AMD Ex-1009, 0009
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 9 of 22
`
`5,784,331
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`
`
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`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 10 of 22
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`5,784,331
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`Petitioner AMD Ex-1009, 0011
`
`
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 11 of 22
`
`5,784,331
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`
`Petitioner AMD Ex-1009, 0012
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 12 of 22
`
`5,784,331
`
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`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 13 of 22
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`5,784,331
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`US. Patent
`
`Jul. 21, 1998
`
`Sheet 14 of 22
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`5,784,331
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`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 15 of 22
`
`5,784,331
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`

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`US. Patent
`
`Jul. 21, 1998
`
`Sheet 16 of 22
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`5,784,331
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`Petitioner AMD Ex-1009, 0017
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 17 of 22
`
`5,784,331
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`Petitioner AMD Ex-1009, 0018
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 18 of 22
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`5,784,331
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`Petitioner AMD Ex-1009, 0019
`
`Petitioner AMD Ex-1009, 0019
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 19 0f 22
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`5,784,331
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`Petitioner AMD Ex-1009, 0020
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 20 of 22
`
`5,784,331
`
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`Petitioner AMD Ex-1009, 0021
`
`Petitioner AMD Ex-1009, 0021
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 21 of 22
`
`5,784,331
`
`MEMORY
`
`COMPUTER
`SYSTEM
`
`
`
`
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`
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`Petitioner AMD Ex-1009, 0022
`
`Petitioner AMD Ex-1009, 0022
`
`

`

`US. Patent
`
`Jul. 21, 1998
`
`Sheet 22 of 22
`
`5,784,331
`
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`Petitioner AMD Ex-1009, 0023
`
`Petitioner AMD Ex-1009, 0023
`
`

`

`1
`MULTIPLE ACCESS MEMORY DEVICE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The following pending US. patent applications by David
`C. McClure entitled: “Architecture Redundancy.” Ser. No.
`08/5 82.424 (Attorney’s Docket No. 95-C-136). and “Redun-
`dancy Control.” Ser. No. 08/580.827 (Attorney’s Docket
`No. 95-C-l43). which were filed on Dec. 29. 1995. and have
`the same ownership as the present application. and to that
`extent are related to the present application. which are
`incorporated herein by reference; and entitled: ‘Test Mode
`Activation And Data Override.” Ser. No. 08/587.709
`(Attorney’s Docket No. 95-C—137). “Pipelined Chip Enable
`Control Circuitry And Methodology.” Ser. No. 08/588.730
`(Attorney’s Docket No. 95—C-138). “Output Driver Cir-
`cuitry Having A Single Slew Rate Resistor.” Ser. No.
`08/588.988 (Attorney’s Docket No. 95-C—139). “Synchro—
`nous Stress Test Control.” Ser. No. 08/589.015 (Attorney’s
`Docket No. 95-C-142). “Write Pass Through Circuit." Ser.
`No. 08/588.662 (Attorney’s Docket No. 95-C- 144). “Data-
`Input Device For Generating Test Signals On Bit And
`Bit-Complement Lines." Ser. No. 08/588.762 (Attorney’s
`Docket No. 95-0145). “Synchronous Output Circuit." Ser.
`No. 08/588.901 (Attorney's Docket No. 95—C-146). “Write
`Driver Having A Test Function.” Ser. No. 08/589.14l
`(Attorney’s Docket No. 95-C-147). “Circuit And Method
`For Tracking The Start Of AWrite To A Memory Cell.” Ser.
`No. 08/589.139 (Attorney’s Docket No. 95-C— 148). “Circuit
`And Method For Terminating A Write To A Memory Cell."
`Ser. No. 08/588.737 (Attorney’s Docket No. 95-C-149).
`“Clocked Sense Amplifier With Word Line Tracking." Ser.
`No. 08/587.782 (Attorney’s Docket No. 95-C-150).
`“Memory-Row Selector Having ATest Function.” Ser. No.
`08/589.l40 (Attorney’s Docket No. 95—C-151). “Synchro-
`nous Test Mode Initialization.” Ser. No. 08/588.729
`(Attorney’s Docket No. 95-C—153). “Device And Method
`For Isolating Bit Lines FromA Data Line.” Ser. No. 08/588.
`740 (Attorney’s Docket No. 95-C-154). “Circuit And
`Method For Setting The Time Duration Of A Write To A
`Memory Cell.” Ser. No. 08/587.7ll (Attorney’s Docket No.
`95-C—156). “Low-Power Read Circuit And Method For
`Controlling A Sense Amplifier." Ser. No. O8I589.024
`(Attorney’s Docket No. 95-C-168). “Device And Method
`For Driving A Conductive Path With A Signal." Ser. No.
`08/587.708 (Attorney’s Docket No. 95-C-169). and the
`following pending US. patent application by Mark A.
`Lysinger entitled: “Burst Counter Circuit And Method of
`Operation Thereof.” Ser. No. 08/589.023 (Attorney’s
`Docket No. 95—C-14lA). all of which have the same eifec-
`tive filing date and ownership as the present application. and
`to that extent are related to the present application. which are
`incorporated herein by reference.
`
`FIELD OF THE INVENTION
`
`This invention is related generally to a burst counter
`circuit and more specifically to a pipelined address scheme
`for storing a second decoded memory address while the
`burst counter circuit is accessing memory locations associ-
`ated with a first decoded memory address.
`
`BACKGROUND OF THE INVENTION
`
`As synchronous burst SRAMs become more popular.
`market pressure to improve performance is increased. Part of
`the increased performance has been obtained by pipelining
`data. While pipelining data increases the speed at which the
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`data is provided to a user. it does not increase the speed of
`the cycle time nor shorten the overall time required to get
`data into or out of specific addresses within a memory array.
`One known technique for increasing the speed at which
`data is read out of a memory is to use a burst counter which
`increments the input and memory address under the control
`of a clock without requiring new address to be input. Prior
`art burst SRAMs used a burst counter which manipulated the
`address signal before it was input to the address decoder
`circuit. In these SRAMs. the output of the burst counter was
`then passed to an address decoder. This type of burst counter
`could also easily be attached to the front of existing syn-
`chronous designs with no significant changes required to the
`memory core or to the synchronous decoder. Using this
`technique. the memory could use well known and reliable
`decoder circuits to select the rows and columns. One down—
`side of this approach is that all address transitions must still
`propagate through the address decoder. The speed at which
`address signals can propagate through the address decoder
`may become a limiting factor at faster cycle times.
`SUMMARY OF THE INVENTION
`
`invention. a
`According to principles of the present
`memory circuit has a plurality of data storage locations and
`an address associated with each data storage location. Afirst
`decoded address storage circuit stores a first decoded
`memory address and holds it for accessing a particular
`memory address. A second decoded address storage circuit
`stores a second decoded memory address and holds it for
`accessing a second decoded memory address. A control
`circuit is coupled to the first decoded address storage circuit
`and operates to transfer decoded memory address inforrna—
`tion from the second decoded address storage circuit to the
`first decoded address storage circuit.
`In one embodiment. a counter circuit is coupled to the
`output of the first decoded address storage circuit for access-
`ing the data storage location associated with the first
`decoded memory address in response to the first decoded
`memory address being output from the first decoded
`memory circuit. The counter circuit includes a burst counter
`circuit which accesses the data storage location associated
`with the first decoded memory address and also accesses
`three additional data storage locations. the decoded memory
`addresses associated with these three additional data storage
`locations being generated by the burst counter circuit using
`the first decoded memory address.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a memory device in accor-
`dance with the present invention.
`FIG. 2 is a block diagram of one embodiment of a
`read/write circuit of the memory device of FIG. 1.
`FIG. 3 is a block diagram of one embodiment of a row
`addressing circuit of the memory device of FIG. 1.
`FIG. 4 is a schematic of the address input buffer of FIG.
`
`3.
`
`FIG. 5 is a schematic of the even/odd row selector of FIG.
`
`3.
`
`FIG. 6 is a detailed schematic of the word line and block
`select circuit of FIG. 3.
`FIG. 7 is a detailed schematic of the word line select
`circuit of FIG. 3.
`FIG. 8 is a detailed schematic of the local word line drive
`circuit of FIG. 3.
`
`FIG. 9A is a block diagram of an SRAM in accordance
`with one embodiment of the present invention.
`
`Petitioner AMD Ex-1009, 0024
`
`Petitioner AMD Ex-1009, 0024
`
`

`

`5.784.331
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`3
`FIG. 9B is a detailed block diagram of one of the blocks
`of the SRAM of FIG. 9A.
`
`FIG. 10 is a block diagram. of the pipelined column
`address burst counter circuit in accordance with one embodi-
`ment of the present invention.
`FIG. 11 is a more detailed block diagram of one embodi-
`ment of the pipelined column address burst counter circuit of
`the present invention.
`FIG. 12 is a schematic of the column address input bufier
`and master latch circuit of FIG. 11.
`FIG. 13 is a schematic of the column address driver circuit
`of FIG. 11.
`
`FIG. 14 is a schematic of the column address predecoder
`circuit of FIG. 11.
`FIG. 15 is a schematic of one embodiment of the column
`address decoder circuit and slave latch circuit of FIG. 11.
`FIG. 16 is a schematic of another embodiment of the
`column address decoder circuit and slave latch circuit of
`FIG. 11.
`FIG. 17 is a schematic of still another embodiment of the
`column address decoder circuit and slave latch circuit of
`FIG. 11.
`
`FIG. 18 is a functional block diagram of one embodiment
`of the burst counter circuit of FIG. 10.
`
`FIG. 19 is a functional block diagram of another embodi-
`ment of the burst counter circuit of FIG. 10 comprising a
`plurality of latches.
`FIG. 20 is a functional block diagram of still another
`embodiment of the burst counter circuit of FIG. 10 com-
`
`prising a plurality of latches.
`FIG. 21 is a schematic of the burst controller of FIG. 10.
`FIG. 22 is a schematic of the column select circuit of FIG.
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`FIG. 23 is a block diagram of a computer system includ—
`ing a memory device according to the present invention.
`FIGS. 24 and 25 are block diagrams of alternative
`embodiments of computer systems using a memory device
`of the present invention.
`
`DETAJLED DESCRIPTION OF THE
`INVENTION
`
`FIG. 1 shows a memory device 50 having a memory array
`52 thereon.
`
`The memory array 52 is subdivided into a plurality of
`memory array blocks 54. The memory array 52 is subdi-
`vided into as many memory array blocks 54 as desired.
`according to the design. For example. eight blocks. nine
`blocks. or 16 blocks are rather common numbers of array
`blocks 54. In one embodiment. 32 memory array blocks 54
`are formed as shown in FIG. 1. The 32 blocks are grouped
`into four quadrants. each quadrant having eight blocks.
`There are four quadrants on the memory device 50.
`Associated with each memory may block 54 is a respec-
`tive block input/output (I/O) circuit 56 and word line drive
`circuit 58. In one embodiment. the word line drive circuit 58
`for two adjacent memory array blocks 54 is positioned in a
`single region between the two adjacent memory array
`blocks. Alternatively. the word line drive circuit 58 can be
`located in the central or peripheral regions of the memory
`device 50. Other circuitry for accessing a memory cell in the
`memory array 52. such as row and address decoders. input!
`output bufiers and sense amplifiers are located in the block
`110 circuitry 56. central regions 60 and 62 and other posi-
`tions on the memory device 50 as needed. A plurality of
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`bonding pads 64 are provided in the peripheral region of the
`memory device 50 for connecting to data input/output pins.
`voltage supply lines. address lines and other electrical con-
`nections as needed.
`FIGS. 2 and 3 illustrate an embodiment of a read/write
`circuit 69 and a row address circuit 105. respectively. of the
`memory device 50. Each memory array block 54 is provided
`with circuitry for providing data to and from for that
`individual block. In one embodiment. the circuitry of FIGS.
`2 and 3 will be provided for each memory array block 54 so
`that there are 32 such circuits on a single memory device 50.
`Alternatively. for that circuitry which can be shared between
`two memory array blocks 54. only 16 such circuits will be
`needed. as will be apparent to those of skill in the art. In one
`embodiment. the memory device 50 is capable of receiving
`32 bits of data simultaneously and outputting 32 bits of data
`simultaneously. Therefore. all circuitry required to input and
`output 32 bits of data simultaneously is provided. such as 32
`input/output buifers. and the like. The 32 bits can be
`provided by simultaneously accessing one memory cell in
`each of the 32 memory array blocks 54 or. alternatively. by
`accessing 8 memory cells in one memory array block within
`one quadrant and accessing four blocks one within each
`quadrant simultaneously. The circuits shown in FIGS. 2 and
`3 are thus provided for each individual block of the memory
`array 52 and can have a 1 bit bus. an 8 bit bus. a 4 bit bus
`or the like.
`
`As shown in FIG. 2. a data signal line 27 receives data and
`provides the data to a conventional data input bulfer 68. The
`data input buffer 68 outputs the data complement DC. on a
`signal line 70 and the data true DT. on a signal line 72. A
`write driver 75 receives the data from the data input buffer
`68 and outputs the data on a pair of signal lines write bit
`complement. WBC 74 and write bit true. WET 76. The data
`input buffer 68 also outputs the data to an output bufier 98
`on line 97. The signal lines WBC 74 and WBT 76 are input
`to a column select circuit 78. The column select circuit 78
`
`outputs the data on bit line complement BBC 80 and bit line
`true BLT 82 for writing to the memory array blocks 54. A
`burst counter 40 outputs column select signals 130 directly
`to the column select circuit 78 for addressing specific bit
`lines within the memory array block 54. The BLC line 80
`and BLT line 82 are connected to the memory array block 54
`as shown in FIG. 3. The WBC and WBT signal lines 74 and
`76 are also connected to a reset control circuit 84 which
`
`outputs signal lines RESET 86 and reset bar (RESET B) 88.
`The column select circuit 78 also receives additional input
`signals to control reading and writing data to and from the
`memory array block 54 as explained in more detail with
`respect to FIG. 19. A read bit complement RBC 90 and a
`read bit true RBT 92 signal are output by the column select
`circuit 78 and carry the read bit data when the circuitry of the
`memory device 50 is in the read mode. The signals RBC 90
`and RBT 92 are input to a sense amp circuit 94 which
`operates to sense read data in a manner well known in the
`art.
`
`Referring to FIG. 3. the row address circuit 105 includes
`an address decoder 107 which receives address information
`
`and outputs decoded address information to a word line and
`block select circuit 104. Additional address decode circuitry
`including an input buifer 106. an even/odd row selector 108
`and a word line select circuit 110 are part of the address
`decode circuitry. The word line select circuit 110 provides
`signals to a local word line driver circuit 112 which outputs
`signals LWLl and LWLO to drive individual word lines of
`the memory array block 54. As will be appreciated. the
`appropriate address decoder circuitry for the column address
`
`Petitioner AMD Ex-1009, 0025
`
`Petitioner AMD Ex-1009, 0025
`
`

`

`Petitioner AMD Ex-1009, 0026
`
`

`

`5.784.331
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`7
`further alternative embodiment. the burst controller 30 is
`coupled to receive the output on line 26 from the column
`decoder 100 and reencode this output to determine the
`interleaved direction in the event it is operating in the
`interleaved mode.
`
`FIG. 11 is a more detailed block diagram of another
`embodiment of the present invention. This embodiment is
`similar to that previously described with reference to FIG.
`10. In this embodiment. however. the burst controller 30 is
`coupled to the column address predecoder 110 and receives
`the first stage predecoded address information on line 22.
`The burst controller 30 in this embodiment contains an
`encoder circuit for reestablishing the original column
`address signal from the predecoded column address infor-
`mation Yx received on line 22. The burst controller 30
`
`outputs signals on line 38 to control the burst counter 40 as
`explained in more detail herein.
`The column address signal 101 is input to the column
`address input butfer and master latch circuit 104 on indi-
`vidual column address lines 98. This circuit 104 is made of
`a number of individual buffer and master latch circuits 103
`and is equivalent to the column address input butfer 104 of
`FIG. 10. The outputs of each of the circuits 103 is input to
`the column address driver circuit 106. which is made of
`individual driver circuits 105 and corresponds to the column
`address driver 106 of FIG. 10. The outputs of each of the
`column address driver circuits 105 is input to the column
`address predecoder circuit 110. which is made of individual
`predecoders 107 and is shown in block form as the column
`address predecoder 110 in FIG. 10. The outputs of each of
`the individual column address predecoders 107 is input to a
`column address decoder circuit 100. The circuit 100 includes
`
`a plurality of individual column address decoder circuits
`109. The outputs from the individual decoders 109 are
`coupled to a slave latch circuit 111 which includes a plurality
`of individual slave latches 102. The slave latch circuit 111 is
`within the burst counter 40 in FIG. 10. Each of the individual
`slave latch circuits 102 outputs one of the column select
`signals 130 from the slave latch circuit 111. These individual
`column select signals 130 therefore correspond to the single
`column select line 130 of FIGS. 2 and 10. In one embodi-
`ment of the present invention. the individual slave latches
`102 are grouped in groups of four. In each group of four.
`each individual slave latch 102 is connected to the adjacent
`slave latch by lines 112 and the top slave latch is connected
`to the bottom slave latch by lines 113 as shown by the lines
`and arrows in FIG. 11.
`
`The output of the column address predecoder circuit 110
`is. as previously mentioned. input to the burst controller 30.
`on lines 22. and the burst controller outputs signals to the
`slave latch circuit 111 on lines 38 for controlling the selec-
`tion of the various columns in the memory array block 54
`under control of the slave latch circuit even though the
`address in the input bufl'er and master latch circuit 104 does
`not change. as explained in more detail herein.
`The circuit shown in FIG. 11 illustrates the circuitry for
`four individual column address iines 98. the column address
`101 as a whole being made up of the individual address lines
`98. While only four column address lines 98 are used as
`shown in FIG. 11. in an alternative embodiment there are
`sixteen such individual column address lines and the cir-
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`cuitry shown in FIG. 11 is provided four times on the
`alternative memory device 50 to permit a burst counter 40 of
`16 bits. Depending on the number of column addresses
`controlled by the burst counter 40 (four address pins. as
`preferred in the circuit herein. or 16 pins). the circuitry is
`provided and connected as needed. Some memory devices
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`50 may have only twelve address pins. and any other number
`of column addresses may be controlled by the burst counter
`40.
`FIG. 12 is a detailed schematic of one of the column
`address input buffer and master latch circuits 103 of FIG. 11.
`The individual input bufler and master latch 103 includes a
`TI‘L input buifer 115 of a standard type which outputs the
`complemented column address input data on line 117 to an
`inverter 119 on line 121. The column address input data is
`delayed and presented to a transfer gate 123. The transfer
`gate 123 is enabled or disabled by the internal clock K on
`complementary signal lines KINT and KINC. When the
`transfer gate 123 is enabled. the column address input data
`is transferred to a master latch 124 having a pair of cross-
`coupled inverters 126 and 128 for holding the address
`information. When the internal K clock is high. a transfer
`gate 125 is enabled to maintain the logic level in the master
`latch 124. The state of the logic level in the master latch 124
`does not change until new address data is positively inserted
`via transfer gate 123 by the clock K going low. The column
`address data complement output is provided on a line 131
`labeled OUTC. When the clock K is high. the transfer gate
`123 is disabled and the transfer gate 125 is enabled to block
`the change of address information in the master latch 124.
`FIG. 13 shows a detailed schematic of one individual
`column address driver circuit 105 shown in FIG. 11. The
`complement column address data CAxC is generated on line
`137 from the input OUTC on a line 131 by two inverters in
`series 138 and 135. In addition. the true column address data
`is output on line 139 as CAXT by being passed through an
`inverter 141 when a transfer gate 143 is enabled by a
`complementary pair of signals A0? and AON. The remain-
`ing inputs to the column address driver circuit 105 labeled
`FOFFB and FUN provide signals when carrying out certain
`tests of the memory device 50 and do not relate to the
`passing of column address signals during normal circuit
`operation and therefore are not discussed in detail here.
`FIG. 14 is a schematic of one example of an individual
`column address predecoder circuit 107 of FIG. 11. The
`design and operation of such predecoder circuits 107 are
`well known in the art and need not be described in detail.
`The address input data from two different column address
`driver circuits 105. labeled A1 and A2 in FIG. 14. corre-
`spond to CAxT or CAxC for two address bits from two
`driver circuits 105 shown in FIGS. 11 and 13. These address
`inputs A1 and A2 are provided to the column address
`predecoder 107 on lines 137 and 147. respectively. The
`output of the column address predecoder circuit 107 con—
`tains first stage predecoded data on line 151. Preferably. a
`second set of predecoder circuits are used to predecode other
`portions of the address input signals (not shown here).
`Alternatively. the column address decoder circuit 100 may
`be used instead of one or more column address predecoder
`circuits 110. However. use of one or two stages of column
`address predecoders 110 prior to a column address decoder
`circuit 100 usually simplifies the circuitry required for
`selecting individual columns.
`FIG. 15 is a detailed schematic of an individual column
`address decoder 109 and a slave latch 102 as shown in FIG.
`11 and constructed according to principles of one embodi-
`ment of the present invention. A signal YA is input at
`terminal 150 and a signal YB is input at terminal 152 of the
`address decoder 109. The signals YA and YB are column
`address signals which have been output by two column
`address predecoder circuits 107 shown in FIGS. 11 and 14.
`The column address decoder 109 is a simple address decoder
`and takes advantage of having predecoder stages prior to the
`
`Petitioner AMD Ex-1009, 0027
`
`Petitioner AMD Ex-1009, 0027
`
`

`

`5,784.33]
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`signal YA on line 150 and YB on line 152 being presented
`to the address decoder. In alternative embodiments.
`the
`column address decoder circuit 109 is a much more complex
`circuit which performs the complete decoding of the column
`address information in a single decoding circuit. As will be
`appreciated. any acceptable decoding circuit could be used
`in place of the one shown herein.
`The column address decoder circuit 109 completes the
`decoding of the column address signals YA and YB and
`presents a decoded column address signal on line 154. The
`decoded column address signal on line 154 is provided to an
`input of a first storage latch 500. Specifically. the decoded
`column address signal on line 154 is input to a transfer gate
`502. The transfer gate 502 is controlled by a clock K1C and
`a clock KIT. When the clock KIC goes low and the clock
`KlT goes high. the transfer gate 502 is enabled. When the
`transfer gate 502 is enabled. the decoded column address
`signal on line 154 is output on a line 504. A pair of
`cross-coupled inverters 506 and 508 operate to store the
`decoded column address signal on line 504. The stored
`decoded column address signal is output by the pair of
`cross-coupled inverters 506 and 508 on line 510. which is
`the output of the first storage latch 500. After the value of the
`decoded column address signal is stored on line 510. the
`transfer gate 502 is disabl