`Petition for Inter Partes Review
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
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`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
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`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`
`
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E. IN SUPPORT OF
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,651,134
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`
`
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`Petitioner AMD Ex-1002, 0001
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`TABLE OF CONTENTS
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`Page
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`TABLE OF CONTENTS
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`I.
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`BACKGROUND AND QUALIFICATIONS ................................................ 1
`A.
`Industry Experience .............................................................................. 2
`B.
`Academic Experience ........................................................................... 5
`C.
`Other Relevant Experience ................................................................... 7
`OVERVIEW OF THE TECHNOLOGY ........................................................ 8
`II.
`SUMMARY OF GROUNDS ....................................................................... 10
`III.
`IV. LEGAL STANDARDS ................................................................................ 12
`V.
`THE CHALLENGED PATENT .................................................................. 15
`VI. PATENT PROSECUTION HISTORY ........................................................ 18
`VII. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 20
`VIII. CLAIM CONSTRUCTION ......................................................................... 20
`A.
`“non-interruptible” (claims 1, 16, 17) ................................................ 21
`B.
`“means for reading data . . . / means for generating a
`predetermined number of said internal address signals” (claim
`16) ....................................................................................................... 22
`“external address signal” (claims 1, 13, 15-17) ................................. 24
`“burst” (claim 2) ................................................................................. 24
`“internal address signal” (claims 1, 2, 12, 15-17) .............................. 24
`“logic circuit” (claims 1, 12) .............................................................. 25
`“predetermined number of [said] internal address signals”
`(claims 1-4, 12, 15-17) ....................................................................... 25
`“memory” (claims 1, 8-9, 14, 17)....................................................... 26
`H.
`“address signal” (claims 1-4, 10-13, 16-17) ....................................... 26
`I.
`IX. SPECIFIC EXPLANATION OF GROUNDS ............................................. 26
`
`C.
`D.
`E.
`F.
`G.
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`Petitioner AMD Ex-1002, 0002
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`TABLE OF CONTENTS
`(continued)
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`Page
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`B.
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`A. Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by
`US 6,115,280 (“Wada”) ..................................................................... 26
`1. Wada ........................................................................................ 26
`2.
`Independent Claim 1 ................................................................ 33
`3.
`Dependent Claim 2 .................................................................. 39
`4.
`Dependent Claim 3 .................................................................. 41
`5.
`Dependent Claim 8 .................................................................. 43
`6.
`Dependent Claim 12 ................................................................ 44
`7.
`Dependent Claim 13 ................................................................ 45
`8.
`Independent Claim 16 .............................................................. 48
`9.
`Independent Claim 17 .............................................................. 55
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are obvious over
`Wada in view of the knowledge of a POSITA ................................... 56
`1.
`Independent Claims 1 and 16 ................................................... 56
`2.
`Dependent Claims 2-3, 8, 12-13, and 17 ................................. 56
`3.
`Dependent Claim 4 .................................................................. 57
`4.
`Dependent Claim 14 ................................................................ 58
`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered
`obvious by the combination of Wada and US 5,584,033
`(“Barrett”) in view of the knowledge of a POSITA ........................... 59
`1.
`Barrett ....................................................................................... 59
`2.
`Claims 1-4, 8, 12-14, 16, and 17 .............................................. 62
`D. Ground 3: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada and U.S. 6,185,149 (“Fujioka”) in view
`of the knowledge of a POSITA. ......................................................... 62
`1.
`Fujioka ..................................................................................... 62
`2.
`Dependent Claim 4 .................................................................. 66
`3.
`Dependent Claim 5 .................................................................. 66
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`C.
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`ii
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`Petitioner AMD Ex-1002, 0003
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`TABLE OF CONTENTS
`(continued)
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`Page
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`E.
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`F.
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`4.
`Dependent Claim 6 .................................................................. 67
`Dependent Claim 7 .................................................................. 67
`5.
`Dependent Claim 18 ................................................................ 68
`6.
`Dependent Claim 19 ................................................................ 68
`7.
`Dependent Claim 20 ................................................................ 69
`8.
`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada, Barrett, and Fujioka in view of the
`knowledge of a POSITA. ................................................................... 69
`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by the
`combination of Wada and US 6,226,755 (“Reeves”) in view of
`the knowledge of a POSITA .............................................................. 69
`1.
`Reeves ...................................................................................... 69
`2.
`Dependent Claim 9 .................................................................. 72
`3.
`Dependent Claim 10 ................................................................ 72
`4.
`Dependent Claim 14 ................................................................ 73
`5.
`Dependent Claim 21 ................................................................ 74
`G. Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by
`the combination of Wada, Barrett, and Reeves in view of the
`knowledge of one of ordinary skill in the art ..................................... 74
`H. Ground 5: Claims 11 and 15 are rendered obvious by the
`combination of Wada and US 5,784,331 (“Lysinger”) in view
`of the knowledge of one of ordinary skill in the art ........................... 75
`1.
`Lysinger ................................................................................... 75
`2.
`Dependent Claim 11 ................................................................ 78
`3.
`Dependent Claim 15 ................................................................ 79
`Ground 5a: Claims 11 and 15 are rendered obvious by the
`combination of Wada, Barrett, and Lysinger in view of the
`knowledge of one of ordinary skill in the art ..................................... 81
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`I.
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`iii
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`Petitioner AMD Ex-1002, 0004
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`U.S. Patent No. 6,651,134
`Baker Declaration
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`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
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`1. My name is R. Jacob Baker. I have prepared this declaration as an
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`expert witness retained by Advanced Micro Devices, Inc. In this declaration, I
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`present my opinions, and technical basis for those opinions, that claims 1-21 of
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`U.S. Patent No. 6,651,134 (“the ’134 Patent”) are invalid.
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`2.
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`This declaration contains statements of my opinions formed to date
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`and the reasons for those opinions. I may offer additional opinions based on further
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`review of materials in this case, including opinions and/or testimony of other
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`expert witnesses. I make this declaration based upon my own personal knowledge
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`and, if called upon to testify, would testify competently to the matters contained
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`herein.
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`I.
`
`BACKGROUND AND QUALIFICATIONS
`1.
`I have been working as an Engineer since 1985, and I have been
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`teaching Electrical and Computer Engineering courses since 1991. I am currently
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`a Professor of Electrical and Computer Engineering at the University of Nevada,
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`Las Vegas (“UNLV”). I am also currently an industry consultant for Freedom
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`Photonics. I am the named inventor on over 150 U.S. patents resulting from my
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`industry work.
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`1
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`Petitioner AMD Ex-1002, 0005
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`U.S. Patent No. 6,651,134
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`I received the B.S. and M.S. degrees in Electrical Engineering from
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`2.
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`UNLV in 1986 and 1988, respectively. I received my Ph.D. in Electrical
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`Engineering from the University of Nevada, Reno, in 1993.
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`3. My doctoral research, culminating in the award of a Ph.D.,
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`investigated the use of power MOSFETs in the design of very high peak power,
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`and high-speed, instrumentation. I developed techniques to reliably stack power
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`MOSFETs to switch higher voltages, that is, greater than 1,000 V and 100 Amps of
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`current with nanosecond switching times. This work was reported in the paper
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`entitled “Transformerless Capacitive Coupling of Gate Signals for Series Operation
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`of Power MOSFET Devices,” published in the IEEE Transactions on Power
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`Electronics. The paper received the Best Paper Award in 2000.
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`A.
`4.
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`Industry Experience
`From 1985 to 1993 I worked for EG&G Energy Measurements and
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`the Lawrence Livermore National Laboratory designing nuclear diagnostic
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`instrumentation for underground nuclear weapon tests at the Nevada test site.
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`During this time I designed, and oversaw the fabrication of, over 30 electronic and
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`electro-optic instruments including high-speed cable and fiber-optic
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`receiver/transmitters, PLLs, frame and bit-syncs, data converters, streak-camera
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`sweep circuits, Pockel’s cell drivers, micro-channel plate gating circuits, charging
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`Petitioner AMD Ex-1002, 0006
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`U.S. Patent No. 6,651,134
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`circuits for battery backup of equipment for recording test data, and analog
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`oscilloscope electronics.
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`5.
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` My work during this time, as one example, had a direct impact on my
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`doctoral research work using power MOSFETs, subsequent publishing efforts, and
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`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
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`Electronics Society, I published several other papers in related areas while working
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`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply
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`design, titled, “Adaptively biased voltage regulator and operating method,” which
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`was issued on February 23, 1999. I have designed dozens of linear and switching
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`power supplies for commercial products and scientific instrumentation.
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`6.
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`I am a licensed Professional Engineer and have extensive industry
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`experience in circuit design, fabrication, and manufacture of Dynamic Random
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`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
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`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
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`Micron Technology, Inc. (“Micron”) in Boise, Idaho. I spent considerable time
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`working on the development of Flash memory chips while at Micron. My efforts
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`resulted in more than a dozen patents relating to Flash memory. One of my
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`projects at Micron included the development, design, and testing of circuit design
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`techniques for a multi-level cell (MLC) Flash memory using signal processing.
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`Among many other experiences, I led the development of the delay locked loop
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`3
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`Petitioner AMD Ex-1002, 0007
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`U.S. Patent No. 6,651,134
`Baker Declaration
`(DLL) in the late 1990s so that Micron DRAM products could transition to the
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`DDR memory protocol for addressing and controlling accesses to memory via
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`interprocess communications (IPC) with the memory controller (MC). I provided
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`technical assistance with Micron’s acquisition of Photobit during 2001 and 2002,
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`including transitioning the manufacture of CIS products into Micron’s process
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`technology. Further, I did consulting work at Sun Microsystems and then Oracle
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`on the design of memory modules during 2009 and 2010. This work entailed the
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`design of low-power, high-speed, and wide interconnection methods with the goal
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`of transmitting data to/from the memory module and the MC at higher speeds.
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`7.
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`I have extensive experience in the development of instrumentation and
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`commercial products in a multitude of areas including: integrated
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`electrical/biological circuits and systems, array (memory, imagers, and displays)
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`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
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`electro-optic instrumentation for scientific research, CAD tool development and
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`online tutorials, low-power interconnect and packaging techniques, design of
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`communication/interface circuits (to meet commercial standards such as USB,
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`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
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`energy, and power electronics. For example, a part of my research at Boise State,
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`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
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`Vias (TWVs), for high-density packaging. These packaging techniques were
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`U.S. Patent No. 6,651,134
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`utilized in the memory module development work I did with Sun Microsystems
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`and Oracle. As another example, I’ve designed circuitry for use in implementing
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`Universal Serial Bus (USB) interfaces circuits while I did consulting at Tower
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`Semiconductor. I designed PCI communication circuits for IPC between a
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`Graphics Processor Unit (GPU) and memory while consulting for Rendition, Inc.
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`8. My current research work is focused in part on the design of
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`integrated circuits for wireless sensing using LIDAR (LIght Detection And
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`Ranging). I have worked with several companies in the development of these
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`circuits and systems including Aerius Photonics and FLIR. In the early 1990s I
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`worked on wireless systems for wideband impulse radar while at Lawrence
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`Livermore Laboratory. Further, part of my research for several years focused on
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`the digitization of IQ channels using delta-sigma modulation. The knowledge and
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`experience gained from this effort are reflected in my book CMOS Mixed-Signal
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`Circuit Design and a presentation, which I presented at several companies and
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`universities, http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
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`B. Academic Experience
`9.
`I was an adjunct faculty member in the Electrical Engineering
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`department of the University of Nevada, Las Vegas in 1991 and 1992. From 1993
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`to 2000, I served on the faculty at the University of Idaho as an Assistant Professor
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`and then as a tenured Associate Professor of Electrical Engineering. In 2000, I
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`Petitioner AMD Ex-1002, 0009
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`U.S. Patent No. 6,651,134
`Baker Declaration
`joined a new Electrical and Computer Engineering program at Boise State
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`University (“BSU”) where I served as department chair from 2004 to 2007. At
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`BSU, I helped establish graduate programs in Electrical and Computer Engineering
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`including, in 2006, the university’s second Ph.D. degree. In 2012, I re-joined the
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`faculty at UNLV. Over the course of my career as a professor I have advised over
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`85 masters and doctoral students.
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`10.
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`I have been recognized for my contributions as an educator in the
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`field. While at Boise State University, I received the President’s Research and
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`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
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`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
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`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
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`Valley”). The Terman Award is bestowed annually upon an outstanding young
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`electrical/computer engineering educator in recognition of the educator’s
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`contributions to the profession. In 2011 I received the IEEE Circuits and Systems
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`Education Award. I received the Tau Beta Pi Outstanding Electrical and Computer
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`Engineering Professor Award every year it was awarded while I have been back at
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`UNLV.
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`11.
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`I have authored several books and papers in the electrical and
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`computer engineering area. My published books include CMOS Circuit Design,
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`Layout, and Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed.,
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`Petitioner AMD Ex-1002, 0010
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`U.S. Patent No. 6,651,134
`Baker Declaration
`2019)) and CMOS Mixed-Signal Circuit Design (Baker, R.J., Wiley-IEEE, ISBN:
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`9780470290262 (2nded., 2009) and ISBN: 9780471227540 (1st ed., 2002)). I co-
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`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
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`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
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`and DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE,
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`ISBN: 0780360141 (2001)) I contributed as an editor and co-author on several
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`other electrical and computer engineering books.
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`C. Other Relevant Experience
`12.
`I have performed technical and expert witness consulting for over 100
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`companies and laboratories and given more than 50 invited talks at conferences,
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`companies, and Universities. Further, I am the author and co-author of more than
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`100 papers and presentations in the areas of electrical and computer engineering
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`design, fabrication and packaging.
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`13.
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`I currently serve, or have served, as a volunteer on: the IEEE Press
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`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
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`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
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`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
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`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
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`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); and as the
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`Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE
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`Petitioner AMD Ex-1002, 0011
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`U.S. Patent No. 6,651,134
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`Solid-State Circuits Magazine. These meetings, groups, and publications are
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`intended to allow researchers to share and coordinate research. My active
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`participation in these meetings, groups, and publications allowed me to see what
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`other researchers in the field have been doing.
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`14.
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`In addition to the above, I am an IEEE Fellow for contributions to
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`memory circuit design and a member of the honor societies Eta Kappa Nu and Tau
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`Beta Pi.
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`15.
`
`I understand my CV is being filed herewith as Exhibit Ex-1003.
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`II. OVERVIEW OF THE TECHNOLOGY
`16. As of early 2000, when the ’134 Patent was filed, integrated circuit
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`memories had been well known for decades and were in use widely throughout the
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`semiconductor, computer, and other industries. At a basic level, memories are
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`comprised of circuit elements that store information to represent one of two logic
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`states, a 1 (true or ON) or a 0 (false or OFF).
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`17.
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` The most common form of memory is dynamic random access
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`memory, or DRAM. DRAM uses a transistor and a capacitor to form a memory
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`cell. A charged capacitor represents a 1, and a discharged capacitor represents a 0.
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`A charged capacitor, however, tends to leak charge, and it must be periodically
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`refreshed. Thus, the DRAM must read and write back data to each DRAM cell
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`periodically to refresh the DRAM memory cell’s contents.
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`8
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`Petitioner AMD Ex-1002, 0012
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`U.S. Patent No. 6,651,134
`Baker Declaration
`18. Another form of integrated circuit memory is static random access
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`memory, or SRAM. Instead of a capacitor to store charge, SRAM uses transistors
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`in each memory cell arranged as a flip-flop. An advantage of SRAM is that
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`because it does not use a capacitor to maintain a data state. Therefore the leakage
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`that happens in a DRAM is not a concern in an SRAM. The SRAM does not need
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`to be refreshed. However, the disadvantage is that an SRAM cell takes up more
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`area on a chip than DRAM, so it has lower storage capacity for a given chip area.
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`For a fixed amount of memory SRAM is therefore more expensive than DRAM.
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`19. Memory cells are typically arranged in an array of columns (bitlines)
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`and rows (wordlines). The intersection of a bitline and a wordline is the address of
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`the memory cell at that location. When a controller asserts an address of a given
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`cell then data can be read from or written to that cell.
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`20. Often, the data to be accessed in a memory array is stored in
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`contiguous cells. Thus, in the late 1980’s or early 1980’s, it was realized that more
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`efficient data throughput could be achieved by reading or writing data to or from
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`memory in bursts. In other words, the controller would assert a single address, and
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`then circuit logic would automatically generate a series of addresses offset from
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`that initial address to transfer a series of data values in response to a single address.
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`See, for example, U.S. Patent No. 4,366,539 to Johnson et al., entitled “Memory
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`9
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`Petitioner AMD Ex-1002, 0013
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`U.S. Patent No. 6,651,134
`Baker Declaration
`controller with burst mode capability,” issued in 1982. Such burst transfers reduce
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`overhead and allow for higher data throughput.
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`21.
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`In an SRAM system, because no refresh is required, burst data
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`transfers can be initiated and allowed to run to completion with no need to
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`interrupt them. In a DRAM system, however, periodic refresh of the memory cells
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`is required, and if the timing is not managed efficiently, a data burst might be
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`interrupted in order to carry out a refresh cycle. However, this problem was
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`overcome by arranging different memory partitions in such a way that a refresh
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`cycle for one partition was hidden behind a burst read or write of another partition,
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`a technique called “hidden memory refresh.” See, for example, U.S. Patent No.
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`4,357,686 to Scheuneman, issued in 1982 and entitled “Hidden memory refresh,”
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`which discusses hidden memory refresh operations in a system using burst-mode
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`memory transactions.
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`III. SUMMARY OF GROUNDS
`22.
`I understand that AMD is seeking review and cancellation of all 21
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`claims of the ’134 Patent under 35 U.S.C. §102 and/or §103 based on the following
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`grounds:
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`Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by US 6,115,280
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`(“Wada”);
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`Petitioner AMD Ex-1002, 0014
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`U.S. Patent No. 6,651,134
`Baker Declaration
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
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`in view of the knowledge of a person of ordinary skill in the art (“POSITA”);
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`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
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`and US 5,584,033 (“Barrett”) in view of the knowledge of a POSITA;
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`Ground 3: Claims 4-7, and 18-20 are rendered obvious by Wada and U.S.
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`6,185,149 (“Fujioka”) in view of the knowledge of a POSITA.
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`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by Wada, Barrett,
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`and Fujioka in view of the knowledge of a POSITA
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`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by Wada and US
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`6,226,755 (“Reeves”) in view of the knowledge of a POSITA;
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`Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by Wada, Barrett,
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`and Reeves in view of the knowledge of a POSITA;
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`Ground 5: Claims 11 and 15 are rendered obvious by Wada and US
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`5,784,331 (“Lysinger”) in view of the knowledge of a POSITA; and
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`Ground 5a: Claims 11 and 15 are rendered obvious by Wada, Barrett, and
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`Lysinger in view of the knowledge of one a POSITA.
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`23. None of the references relied upon in the Petition was cited by the
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`Examiner during prosecution of the ’134 Patent. Ex-1001, 1.
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`11
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`Petitioner AMD Ex-1002, 0015
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`U.S. Patent No. 6,651,134
`Baker Declaration
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`IV. LEGAL STANDARDS
`24.
`I am not an attorney. In this declaration, I apply relevant legal
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`principles as they have been provided to me by attorneys to arrive at the opinions
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`set forth in this declaration.
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`25. Anticipation: I understand a challenged claim may be invalid as
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`“anticipated” if all elements of the challenged claim are disclosed in the prior art
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`reference. The prior art reference need not use the same words as the challenged
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`claim, but all elements must be disclosed so that a POSITA could make and use the
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`claimed subject matter.
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`26.
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`I understand that when a challenged claim covers several structures,
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`either generically or as alternatives, the claim is deemed anticipated if any of the
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`structures within the scope of the claim is found in the prior art reference.
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`27. Obviousness: I understand that even if a challenged claim is not
`
`anticipated, it is still invalid if the differences between the claimed subject matter
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`and the prior art are such that the claimed subject matter would have been obvious
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`to a person of ordinary skill in the pertinent art at the time the alleged invention.
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`28.
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`I understand that an obviousness analysis includes the consideration
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`of factors such as (1) the scope and content of the prior art, (2) the differences
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`between the prior art and the challenged claim, (3) the level of ordinary skill in the
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`pertinent art, and (4) “secondary” or “objective” evidence of non-obviousness.
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`12
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`Petitioner AMD Ex-1002, 0016
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`U.S. Patent No. 6,651,134
`Baker Declaration
`29. Secondary or objective evidence of non-obviousness includes
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`evidence of: (1) a long felt but unmet need in the prior art that was satisfied by the
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`claimed invention; (2) commercial success or the lack of commercial success of
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`the claimed invention; (3) unexpected results achieved by the claimed invention;
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`(4) praise of the claimed invention by others skilled in the art; (5) taking of licenses
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`under the patent by others; (6) deliberate copying of the claimed invention; and (7)
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`contemporaneous and independent invention by others. However, I understand that
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`there must be a relationship between any secondary evidence of non-obviousness
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`and the claimed invention.
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`30.
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`I understand that a challenged claim can be invalid for obviousness
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`over a combination of prior art references if a POSITA would have had a
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`motivation to combine those references. The motivation to combine may come
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`from the references themselves, from simple common sense, or market demand.
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`31. A POSITA may combine the teachings of multiple publications even
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`if they do not necessarily fit perfectly together. Therefore, I understand that
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`references for obviousness need not fit perfectly together like puzzle pieces.
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`Instead, I understand that obviousness analysis takes into account inferences,
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`creative steps, common sense, and practical logic and applications that a person of
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`ordinary skill in the art would employ under the circumstances.
`
`13
`
`Petitioner AMD Ex-1002, 0017
`
`
`
`U.S. Patent No. 6,651,134
`Baker Declaration
`I understand that a claim can be obvious in light of a single reference,
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`32.
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`if the elements of the challenged claim that are not explicitly or inherently
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`disclosed in the reference can be supplied by the common sense of one of skill in
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`the art.
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`33. Claim Construction: I understand that the interpretation of claims is
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`a legal issue the must be resolved before an invalidity analysis can be performed. I
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`have been instructed by attorneys to apply the claim constructions set forth in the
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`accompanying petition. Where competing proposals for construction have been
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`identified, I apply the prior art under all proposed constructions.
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`34.
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`I understand that certain claim limitations may be construed under 35
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`U.S.C. § 112 ¶ 6 as what is known as a “means plus function” limitation. Such
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`terms are interpreted to cover only the corresponding structure described in the
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`specification, and equivalents thereof. I understand that a structure is considered
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`structurally equivalent to the corresponding structure identified in the specification
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`if the differences between them are insubstantial, such as when the structure
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`performs the same function in substantially the same way to achieve substantially
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`the same result. I further understand that a structural equivalent must have been
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`available at the time of the issuance of the claim.
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`14
`
`Petitioner AMD Ex-1002, 0018
`
`
`
`U.S. Patent No. 6,651,134
`Baker Declaration
`
`V. THE CHALLENGED PATENT
`35. The ’134 Patent is directed to an integrated circuit comprising a
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`memory and a logic circuit and a method for addressing the memory circuit with a
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`burst of internal address signals that may be non-interruptible. Ex. 1001 at
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`Abstract. A device reads data from memory by asserting an address and receiving
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`data from the memory location specified by that address. In “burst” mode,
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`however, a controller asserts a single address, and memory circuit logic generates a
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`series of internal addresses, typically offset from the initial address as address+0,
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`address+1, address+2, etc., and returns data from multiple memory locations
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`specified by those internal addresses in response to one external addresses.
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`36. The preferred embodiment of the alleged invention seen in Fig. 1 of
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`the ‘134 patent is “configured to transfer a fixed number of words of data with
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`each access (e.g., read or write).” Id. at 2:28-30. An array of memory cells may be
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`addressed by a “burst address counter” circuit that receives an external address
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`(ADDR_EXT), a clock (CLK), and control signals (e.g., LOAD, ADV) and that
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`outputs a burst of internal addresses ADDR_INT that access the memory cells.
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`See id. at 2:31-46. Specifically, Fig. 1 depicts “Burst Address Counter / Register”
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`102, which latches in external address ADDR_EXT when the LOAD signal is
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`asserted. Id. at 3:14-19. When ADV is asserted, a fixed number of internal
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`addresses (ADDR_INT) are generated in response to the CLK signal. Id. at 3:19-
`
`15
`
`Petitioner AMD Ex-1002, 0019
`
`
`
`U.S. Patent No. 6,651,134
`Baker Declaration
`24. “Once the circuit 102 has started generating the fixed number of addresses, the
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`circuit 102 will generally not stop until the fixed number of addresses has been
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`generated (e.g., a non-interruptible burst).” Id. at 3:25-29.
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`
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`37. The ’134 Patent discloses two embodiments of the “Burst Address
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`Counter” 102, seen in Figs. 2 and 3. In Fig. 2, below, an initial address
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`(ADDR_EXT) is latched into the address counter register 126 when LOAD is
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`asserted. Id. at 4:6-8. When ADV is asserted, the BURST_CLK signal is
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`generated in response to CLK and increments the address in the address counter
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`register 126 to produce a predetermined number of internal address values
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`ADDR_INT (116). Id. at 4:6-14.
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`16
`
`Petitioner AMD Ex-1002, 0020
`
`
`
`U.S. Patent No. 6,651,134
`Baker Declaration
`
`
`
`38.
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`In Fig. 3, an n-bit external address (ADDR_EXT) is divided into an
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`m-bit portion and a k-bit portion. Id. at 4:18-25. The k-bit portion is sent to
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`counter (138) and is incremented by the CLK signal when ADV is asserted. Id. at
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`4:28-33. A multiplexer (136) selects either the latched k-bit portion of the external
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`address (142) or the k-bit output of the counter (138) and concatenates it with the
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`latched m-bit portion of the address to create the internal addresses (ADDR_INT)
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`that are used to address the memory array. Id. at 4:34-39.
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`17
`
`Petitioner AMD Ex-1002, 0021
`
`
`
`U.S. Patent No. 6,651,134
`Baker Declaration
`
`
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`VI. PATENT PROSECUTION HISTORY
`39.
`I reviewed the file history of the application that issued as the ’134
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`Patent. The application was repeatedly rejected during prosecution and eventually
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`allowed after the Examiner did not file a response to the applicant’s appeal brief.
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`40. On 10/1/2001, the Examiner rejected the 17 pending claims, rejecting
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`dependent claims 6 and 15 (which recite that the burst length is programmed by
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`“bond options”) under 35 U.S.C. §112 paragraph 1 because the specification did
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`not sufficiently support that concept. Ex. 1004 (File History) at 42. All claims
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`were also rejected as anticipated by Yip (U.S. 6,289,138). Id. at 42-44. The
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`applicant responded on 2/4/2002, and with respect to the Section 1