Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`
`__________________
`
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`TITLE: MEMORY DEVICE WITH FIXED LENGTH NON INTERRUPTIBLE
`BURST
`Issue Date: November 18, 2003
`__________________
`
`
`PATENT OWNER MONTEREY RESEARCH, LLC’S
`DEMONSTRATIVES
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`U.S. Patent No. 6,651,134
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`
`v.
`
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`
`__________________
`
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`TITLE: MEMORY DEVICE WITH FIXED LENGTH NON INTERRUPTIBLE
`BURST
`Issue Date: November 18, 2003
`__________________
`
`
`PATENT OWNER MONTEREY RESEARCH, LLC’S
`DEMONSTRATIVES
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`Monterey’s Demonstrative Exhibits
`
`Advanced Micro Devices, Inc.
`
`v.
`
`Monterey Research, LLC
`
`U.S. Patent No. 6,651,134
`
`Case IPR2020‐00985
`
`
`
`2
`
`34
`
`18
`
`3
`
`Slide
`
`Objective Indicia Of Non‐Obviousness.
`Obvious Over Wada In Combination With Barrett.
`Ground 2a: Claims 1‐4, 8, 12‐14, and 16‐17 Are Not
`Anticipated By Wada.
`Ground 1a: Claims 1‐3, 8, 12‐13, and 16‐17 Are Not
`
`Topic
`
`A
`
`B
`
`C
`
`Tab
`
`Table of Contents
`
`
`
`3
`
`POR at 2‐9; Surreply at 2‐9.
`
`and 16‐17 Are Not Anticipated By
`Ground 1a: Claims 1‐3, 8, 12‐13,
`
`Wada.
`
`Tab A
`
`
`
`4
`
`4
`
`POR at 3, 18‐19, 31; Surreply at 1, 8, 12.
`
`•Wada Does Not Disclose “wherein said generation of
`
`signals is non‐interruptible.”
`said predetermined number of internal address
`
`signals.”
`predeterminednumber of said internal address
`
`•Wada Does Not Disclose “generating a
`
`Overview of Disputes
`
`
`
`5
`
`5
`
`Institution Decision at 6.
`
`Ex. 1001 (’134 Patent) at claim 1.
`
`Wada Does Not Disclose “generating a predetermined number of said
`
`internal address signals”
`
`
`
`6
`
`POR at 24‐25.
`
`Petition at 26‐27.
`
`external address signal EXT.ADD.
`“2^k” internal address signals in response to an
`AMD alleges that Wada’s burst counter generates
`
`Wada’s Conventional Embodiment Does Not Generate A Predetermined
`
`Number Of Internal Address Signals
`
`
`
`7
`
`POR at 24‐25.
`
`Ex. 1005 (Wada) at 3:5‐9.
`
`and the clock signal CLK is at a leading edge.
`address every time the advance signal ADV is high
`less than 2^k addresses, because it increments the
`Instead, the burst counter may increment more or
`But Wada does not generate only2^k addresses.
`
`Wada’s Conventional Embodiment Does Not Generate A Predetermined
`
`Number Of Internal Address Signals –Cont’d
`
`
`
`8
`
`Surreply at 7‐8.
`
`Reply at 7‐8.
`
`internal addresses.
`actually generating a predetermined number of
`as 2^k internal addresses with the separate issue of
`AMD confuses Wada’s ability to generate as many
`
`Generating At Most 2^k States IS NOT the same as Generating A
`
`PredeterminedNumber of Internal Address Signals
`
`
`
`9
`
`Surreply at 8‐9.
`
`Ex. 1001 (’134 Patent) at 3:25‐28.
`
`Ex. 1001 (’134 Patent) at 3:7‐9.
`
`Wada’s and the ’134 Patent’s ADV Signals Are Not The Same
`
`Signal And Operate Differently
`
`
`
`10
`
`Surreply at 8‐9.
`
`Ex. 1005 (Wada) at 3:5‐9.
`
`Wada’s and the ’134 Patent’s ADV Signals Are Not The Same
`
`Signal And Operate Differently –Cont’d
`
`
`
`11
`
`11
`
`POR at 25‐27.
`
`Petition at 29.
`
`Wada’s Second Embodiment Does Not Generate A Predetermined Number
`
`Of Internal Address Signals
`
`
`
`12
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶124.
`
`POR at 26‐27; Surreply at 7‐9.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶123.
`
`Wada’s Second Embodiment Does Not Generate A Predetermined Number
`
`Of Internal Address Signals –Cont’d
`
`
`
`13
`
`POR at 27.
`
`Ex. 2006 (Baker Dep. Tr.) at 178:6‐23.
`
`burst isn't discussed in Wada.
`operation beyond what goes past the required
`generate additional internal addresses. That
`continue applying clock signals and it doesn't
`zero to three and then stops so that you can
`couple of times now, the counter counts from
`it's just as reasonable that, as I've said a
`It does not discuss that, but I don't --I think
`address signal was never introduced; correct?
`continued to run and a second external chunk
`internal address signals as long as the clock
`would prevent the generation of more than four
`implementation of the burst counter unit 8 that
`
`A.
`
`Q.…Wada does not discuss a structure or an
`
`AMD’s Expert
`Dr. Jacob Baker
`
`Dr. Baker Admitted That Wada Does Not Disclose Anything Preventing The
`
`Generation Of More Than Four Internal Address Signals
`
`
`
`14
`
`Institution Decision at 6.
`
`Ex. 1001 (’134 Patent) at claim 1.
`
`Wada Does Not Disclose “wherein said generation of said predetermined
`
`number of internal address signals is non‐interruptible”
`
`
`
`15
`
`15
`
`POR at 27.
`
`Institution Decision (Paper 13) at 8‐9.
`
`“non‐interruptible”
`
`
`
`16
`
`POR at 28‐29.
`
`Institution Decision (Paper 13) at 18.
`
`Ex. 1005 (Wada) at 1:65‐66.
`
`Wada’s Burst Can Be Terminated By Failing To Maintain The External Advance
`
`Signal (ADV)
`
`
`
`17
`
`POR at 32.
`
`Ex. 1005 (Wada) at 5:50‐53.
`
`Institution Decision (Paper 13) at 18‐19.
`
`Wada Does Not Disclose Preventing Interruptions WithinA Burst
`
`
`
`18
`
`POR at 33‐50; Surreply at 11‐13.
`
`and 16‐17 Are Not Obvious Over
`Ground 2a: Claims 1‐4, 8, 12‐14,
`
`Wada In Combination With
`
`Barrett.
`
`Tab B
`
`
`
`19
`
`19
`
`POR at 30‐50; Surreply at 11‐13.
`
`Barrett.
`Expectation Of Success In Combining Wada And
`
`•A POSITA Would Not Have Had A Reasonable
`
`•A POSITA Would Not Have Been Motivated To
`
`Combine Wada And Barrett.
`
`address signals is non‐interruptible”.
`generation of said predetermined number of internal
`
`•Wada And Barrett Do Not Disclose “wherein said
`
`•Wada And Barrett Do Not Disclose “generating a
`
`signals”.
`predetermined number of said internal address
`
`Overview of Disputes
`
`
`
`20
`
`20
`
`POR at 34
`
`Petition at 29.
`
`said internal address signals” limitation.
`“generating a predetermined number of
`AMD relies on Wada for disclosure of the
`
`Wada And Barrett Do Not Generate A Predetermined Number Of Internal
`
`Address Signals
`
`
`
`21
`
`21
`
`Institution Decision at 6.
`
`Ex. 1001 (’134 Patent) at claim 1.
`
`predetermined number of internal address signals is non‐interruptible”
`Wada And Barrett Do Not Disclose “wherein said generation of said
`
`
`
`22
`
`22
`
`POR at 35
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 150.
`
`predetermined number of internal address signals is non‐interruptible”
`Wada And Barrett Do Not Disclose “wherein said generation of said
`
`
`
`23
`
`23
`
`POR at 35‐36.
`
`Ex. 1010 (Barrett) at 3:44‐46.
`
`Ex. 1010 (Barrett) at 3:16‐19.
`
`Barrett Requires Interruptions of a Data Transmission At Specific Times By
`
`External Signals
`
`
`
`24
`
`POR at 36‐47; Surreply at 11‐14.
`
`•Wada And Barrett Are Not Directed To The Same Purpose
`
`•Combining Wada And Barrett Would Destroy A Key
`
`Objective Of Each Reference
`
`•Wada And Barrett’s Different Systems Operate According
`
`To Different Timing Requirements
`
`•Wada And Barrett’s Different Systems Operate At
`
`Different Speeds And Scales Of Data
`
`•Wada And Barrett Are Directed To Different Operational
`•Wada And Barrett Describe Different Bursts
`
`Procedures
`
`A POSITA Would Not Have Been Motivated To Combine Wada And Barrett
`
`
`
`25
`
`25
`
`POR at 37‐38.
`
`Ex. 2006 (Baker Dep. Tr.) at 134:23‐135:3.
`
`AMD’s Expert
`Dr. Jacob Baker
`
`I think I would agree with that, yes.
`manage accesses to a memory device; fair?
`not necessarily be applicable to a protocol design to
`between devices that involves a burst transfer would
`
`A.
`
`Q.…A protocol for managing communications in
`
`Wada And Barrett Describe Different Bursts
`
`
`
`26
`
`POR at 38‐42.
`
`Ex. 1010 (Barrett) at 6:1‐7.
`
`Ex. 1005 (Wada) at 6:31‐32.
`
`Barrett’s transfer protocol is asynchronous.
`Wada’s memory is synchronousto a clock.
`
`Wada And Barrett Are Directed To Different Operational Procedures
`
`
`
`27
`
`27
`
`POR at 42‐43.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 170.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 169.
`
`slower than SDRAM (Wada) in the same time frame.
`(Barrett) transferred data at a rate more than a magnitude
`Protocols for communicating data between I/O devices
`
`Wada’s And Barrett’s Different Systems Operate At Different Speeds And
`
`Scales Of Data
`
`
`
`28
`
`28
`
`POR at 45‐46.
`
`Ex. 1010 (Barrett) at 5:59‐60; 6:16‐18; 3:21‐22.
`
`…
`
`…
`
`Ex. 1005 (Wada) at 2:55‐59.
`
`Wada’s And Barrett’s Different Systems Operate According To Different
`
`Timing Requirements
`
`
`
`29
`
`29
`
`POR at 46.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 175.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 175.
`
`Combining Wada And Barrett Would Destroy A Key Objective Of Each
`
`Reference
`
`
`
`30
`
`POR at 47.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 177.
`
`Wada And Barrett Are Not Directed To The Same Purpose
`
`
`
`31
`
`POR at 40‐42, 48‐50.
`
`Ex. 1010 (Barrett) at Fig. 1.
`
`Ex. 1005 (Wada) at Fig. 3.
`
`A POSITA Would Not Have Had A Reasonable Expectation Of Success In
`
`Combining Wada And Barrett
`
`
`
`32
`
`POR at 48‐50; Ex. 2004 (Dr. Brogioli Decl.) at ¶¶ 178‐185.
`
`•A burst mode access for a semiconductor memory is a different
`
`transmission between multiple devices in a computing system.
`operation than a burst transfer protocol for managing data
`
`–Wada describes a burst operation for accessing an SRAM
`timing requirements.
`procedures, different scales of data output and speed, and different
`
`•Wada and Barrett describe different bursts, different operational
`
`communications bus within a computing system.
`protocol for transmitting data between I/O devices over a
`semiconductor memory, while Barrett describes a burst transfer
`
`reasonable expectation of success in combining Wada with Barrett.
`
`•Dr. Baker did not consider whether a POSITA would have had a
`
`A POSITA Would Not Have Had A Reasonable Expectation Of Success In
`
`Combining Wada And Barrett –Cont’d
`
`
`
`33
`
`POR at 48‐50; Ex. 2004 (Dr. Brogioli Decl.) at ¶¶ 178‐185.
`
`Ex. 2006 (Baker Dep. Tr.) at 134:23‐135:3.
`
`I think I would agree with that, yes.
`manage accesses to a memory device; fair?
`not necessarily be applicable to a protocol design to
`between devices that involves a burst transfer would
`
`A.
`
`Q.…A protocol for managing communications in
`
`AMD’s Expert
`Dr. Jacob Baker
`
`pauses are to occur, teaches away from Wada.
`devices, and then calculating on top of that when lengthy multi‐cycle
`exchanging handshake signals between the sending and receiving
`obtaining and establishing control of a communication bus,
`
`•The fact that Barrett’s protocol accounts for multiple phases, such as
`
`•Protocols for managing accesses of memory are not compatible with
`
`protocols for communicating data between different I/O devices.
`
`A POSITA Would Not Have Had A Reasonable Expectation Of Success In
`
`Combining Wada And Barrett –Cont’d
`
`
`
`34
`
`POR at 53‐67; Surreply at 14‐18.
`
`Objective Indicia Of Non‐
`
`Obviousness
`
`Tab C
`
`
`
`35
`
`35
`
`POR at 53‐67; Surreply at 14‐18.
`
`•The Claimed Invention Of The ’134 Patent Solves A Long‐
`
`Felt Need.
`
`•A Nexus Exists Between The Claimed Invention Of The
`
`Technology.
`’134 Patent And Non‐Interruptible DDR SDRAM
`
`Overview of Disputes
`
`
`
`36
`
`POR at 54‐63; Ex. 2004 (Dr. Brogioli Decl.) at ¶¶ 197‐204.
`
`Ex. 2014 (Jedec Std.) at 34; Ex. 2004 (Dr. Brogioli Decl.) at ¶ 204.
`
`Ex. 2014 (Jedec Std.) at 18; Ex. 2004 (Dr. Brogioli Decl.) at ¶ 202.
`
`.
`
`A Nexus Exists Between The Claimed Invention Of The ’134 Patent And Non‐
`
`Interruptible DDR SDRAM Technology
`
`
`
`37
`
`POR at 64‐66.
`
`Ex. 2004 (Dr. Brogioli Decl.) at ¶ 219.
`
`The Claimed Invention Of The ’134 Patent Solves A Long‐Felt Need
`
`
`
`38
`
`POR at 64‐66.
`
`Ex. 2006 (Baker Dep. Tr.) at 65:22‐66:8.
`
`between the two.
`the organization address is slightly different
`A.At a high level, the answer is yes, but I mean,
`
`refreshed?
`same way that a nonsynchronous DRAM needs to be
`
`Q.…Does an SDRAM need to be refreshed in the
`
`AMD’s Expert
`Dr. Jacob Baker
`
`The Claimed Invention Of The ’134 Patent Solves A Long‐Felt Need –Cont’d
`
`
`
`39
`
`POR at 3‐4; Surreply at16.
`
`Ex. 1001 (’134 Patent) at 1:11‐18.
`
`The “Non‐Interruptible Bursts” For The ’134 Patent Apply To SRAM Memories
`
`As Well As DRAM Memories
`
`
`
`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`
`Dated: August 27, 2021
`
`Respectfully submitted,
`
`/Theodoros Konstantakopoulos/
`Theodoros Konstantakopoulos, Ph.D.
`(Reg. No. 74,155)
`tkonstantakopoulos@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`Telephone: 212-351-3400
`Facsimile: 212-351-3401
`
`Lead Counsel for Patent Owner
`Avanos Medical Sales, LLC
`
`
`
`1
`
`
`
`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`
`CERTIFICATE OF SERVICE
`
`Pursuant to 37 C.F.R. § 42.6(e), the undersigned certifies that a complete copy
`
`of Patent Owner’s Demonstratives was served on counsel of record for the Petitioner
`by filing this document through PTAB E2E and by sending this document via
`electronic mail to the following addresses:
`
`Xin-Yi Zhou (Reg. No. 63,366)
`O’Melveny & Myers LLP
`400 S. Hope Street
`Los Angeles, CA 90071
`Tel: 213-430-6000
`vzhou@omm.com
`
`Nicholas J. Whilt (Reg. No. 72,081)
`O’Melveny & Myers LLP
`400 S. Hope Street
`Los Angeles, CA 90071
`Tel: 213-430-6000
`nwhilt@omm.com
`
`OMMAMDMONTEREY@omm.com
`
`Dated: August 27, 2021
`
`Ryan K. Yagura (Reg. No. 47,191)
`O’Melveny & Myers LLP
`400 S. Hope Street
`Los Angeles, CA 90071
`Tel: 213-430-6000
`ryagura@omm.com
`
`Brian M. Cook (Reg. No. 59,356)
`O’Melveny & Myers LLP
`400 S. Hope Street
`Los Angeles, CA 90071
`Tel: 213-430-6000
`bcook@omm.com
`
`Respectfully submitted,
`
`/Theodoros Konstantakopoulos/
`Theodoros Konstantakopoulos, Ph.D.
`(Reg. No. 74,155)
`tkonstantakopoulos@desmaraisllp.com
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`Telephone: 212-351-3400
`Facsimile: 212-351-3401
`
`
`2
`
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`
`
`
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