(12) United States Patent
`Reeves
`
`USOO6226755B1
`(10) Patent No.:
`US 6,226,755 B1
`(45) Date of Patent:
`May 1, 2001
`
`(54) APPARATUS AND METHOD FOR
`ENHANCING DATA TRANSFER TO OR
`FROMA SDRAM SYSTEM
`
`(75) Inventor: Earl C. Reeves, Tomball, TX (US)
`(73)
`C
`C
`C
`73) ASSignee: Compaq Computer Corp., Houston,
`TX (US)
`
`c:
`(*) Notice:
`
`0
`-
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/236,871
`1-1.
`(22) Filed:
`Jan. 26, 1999
`(51) Int. Cl." .................................................... G06F 1/04
`(52) U.S. Cl. ............................................. 713/400; 713/600
`(58) Field of Search ..................................... 713/400, 500
`713/600; 711/105 106 1. 67
`s
`s
`s
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`6/1980 White, Jr. et al..
`4,207,618
`9/1994 Chan et al. .
`5,345,577
`8/1995 Ware et al. .
`5,446,696
`5,684.978 * 11/1997 Sarma et al...
`5,802,597 * 9/1998 Nelsen ..............
`6,078.986 * 6/2000 Uchiyama et al.
`
`... 395/496
`... 711/169
`
`- - - - - - - - - - - - - - - - - - 711/105
`
`10/2000 Sherman .............................. 713/400
`6,141,765
`* cited by examiner
`Primary Examiner Dennis M. Butler
`(74) Attorney, Agent, or Firm--Kevin L. Daffer; Conley,
`Rose & Tayon
`ABSTRACT
`(57)
`A computer System, buS interface unit employing a memory
`controller, and method are presented for optimizing the
`bandwidth data, address, and control transfer rates acroSS a
`memory bus coupled to an SDRAM system. The SDRAM
`System is partitioned Such that one partition will undergo
`pre-charge or refresh in the interim between times in which
`another partition (or a pair of partitions) initiate a burst read.
`The burst read cycles coincide with an initial column
`address of the burst, and are spaced a number of cycles equal
`to the burst length. Proper spacing of the initial column
`address, or read request, relative to a non-read requested
`partition ensures data read from the activated partition will
`be placed on the memory data bus in Seamless fashion. That
`is, there are no non-data transferS occurring between data
`burst cycles, even though refresh or pre-charge operations
`are performed on a non-read partition. Careful placement of
`the hidden refresh cycles encountered by one partition
`relative to read cycles on other partitions ensures the data
`flow resulting therefrom will be optimized to Sustain peak
`bandwidth on a synchronous DRAM memory bus.
`20 Claims, 4 Drawing Sheets
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`Processor
`Or
`Memory
`Controller
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`Refresh
`Counter
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`Decoder
`44
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`
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`Internally
`Banked
`Memory
`Array
`48
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`Column
`Latch/Amp.
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`Petitioner AMD Ex-1008, 0001
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`

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`U.S. Patent
`
`May 1, 2001
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`Sheet 1 of 4
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`US 6,226,755 B1
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`Processor
`12
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`CPU
`Bus
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`BuS I/F Unit
`14
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`Frame
`Buffer
`20
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`Display
`22
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`B PC
`P
`eripheral Bus (PCI)
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`Bud I/F Unit
`26
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`I/O
`24
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`ISA/IDE/I2C
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`Kevbd
`Flopp
`Par/Ser
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`Super I/O
`30
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`I/O
`32
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`FIG. 1
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`Petitioner AMD Ex-1008, 0002
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`

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`U.S. Patent
`U.S. Patent
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`May1, 2001
`May 1, 2001
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`Sheet 2 of 4
`Sheet 2 of 4
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`US 6,226,755 B1
`US 6,226,755 B1
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`FIG. 2
`FIG. 2
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`Petitioner AMD Ex-1008, 0003
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`Petitioner AMD Ex-1008, 0003
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`U.S. Patent
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`May 1, 2001
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`Sheet 3 of 4
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`US 6,226,755 B1
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`Processor
`Or
`Memory
`Controller
`42
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`Bank Sel.
`&
`Refresh
`Sel.
`50
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`Internally
`Banked
`Memory
`Array
`48
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`Column
`Latch/Amp.
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`FIG.3
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`Petitioner AMD Ex-1008, 0004
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`U.S. Patent
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`Sheet 4 of 4
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`US 6,226,755 B1
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`May1, 2001
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`6V-OV
` Oc6h
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`€90d-00d
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`Petitioner AMD Ex-1008, 0005
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`Petitioner AMD Ex-1008, 0005
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`US 6,226,755 B1
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`1
`APPARATUS AND METHOD FOR
`ENHANCING DATA TRANSFER TO OR
`FROMA SDRAM SYSTEM
`
`2
`ally employs a counter which moves through rows of the
`array during each count cycle, refreshing charge from cor
`responding column amplifiers in its wake. Because each
`SDRAM integrated circuit or chip is typically divided into
`internal, or logical banks, read and write operations associ
`ated with each row refresh must be performed on each bank.
`All data for the SDRAM device is generally written or
`read in burst fashion. Given a row address and an initial
`column address, the SDRAM internally accesses a Sequence
`of locations beginning at the initial column address and
`proceeding to Succeeding column addresses depending on
`the programmed length of the burst Sequence. The Sequence
`can be programmed to follow either a Serial-burst Sequence
`within one of the internal banks or an interleaved-burst
`Sequence among the pair of internal bankS. Conventional
`SDRAMs can be programmed to read or write a burst of one,
`two, four, eight, or more bits.
`Reading N-bits of data during a read burst operation
`beneficially reduces the control Signal overhead needed to
`transfer that burst of data across the System memory bus and
`to the memory requester. An additional benefit would be
`gained if Several SDRAM chips can be grouped together and
`Selected from a common chip Select Signal. For example, the
`SDRAM system can be partitioned and each partition may
`contain at least one SDRAM chip. If multiple SDRAMs are
`implemented in a single partition, then that partition can be
`interconnected on a printed circuit board, often denoted as a
`memory module, DIMM or SIMM. The chip select signal is
`thereby used to Select a Single partition among many
`partitions, each partition containing one or more SDRAM
`chips.
`Abenefit would be gained if the SDRAM system employs
`a relatively wide memory bus, possibly one which can
`transfer an entire cache line of 256 bits during a four System
`clock cycle-assuming a 64-bit wide Single clock cycle
`transfer. However, it is contemplated that an entire cache
`line could be transferred if the memory bus is to exceed 64
`bits in width, i.e., the memory bus is an entire cache line in
`width. Such a bus transfer architecture could be achieved by
`configuring each partition with a DIMM. In this fashion, a
`partition could transfer four quadwords from, for example,
`a 64 data pin DIMMs during each clocking cycle of the
`System clock. Transferring an entire cache line would prove
`especially useful when fetching a cache line of data to the
`processor cache, or when performing cache-line direct
`memory access ("DMA") transfers.
`However, to take full advantage of any transfer efficiency
`upon the memory bus, the pre-charge and refresh operations
`must be accounted for and, more particularly, must be
`“hidden from cycles present on the memory bus. An
`improved transfer technique must therefore be employed to
`ensure data transferS are not broken whenever a portion of
`the SDRAM system is being pre-charged or refreshed. In
`this manner, the cache lines of data are Seamlessly forwarded
`on each clocking Signal cycle for optimum memory bus
`bandwidth.
`SUMMARY OF THE INVENTION
`The problems outlined above are in large part solved by
`an improved memory bus transfer technique hereof. The
`present transfer technique is one which can perform three of
`more consecutive and unbroken fetches of cache line data
`from the memory to a requesting device. The requesting
`device can be either the processor or a peripheral performing
`access through a DMA cycle. The three consecutive fetches
`incur a data transfer that occupies no more than 12 System
`clock cycles, given a burst length of four cycles per burst.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to computer System and, more
`particularly, to a System and method for maximizing data
`transfer efficiency acroSS a memory buS employing Synchro
`nous dynamic random access memory (“SDRAM”).
`2. Description of the Related Art
`A dynamic random access memory (“DRAM”) device is
`generally well-known as containing an array of memory
`elements organized within rows and columns. A read or
`write access begins by transmitting a row address on the
`address buS and asserting the RAS control Signal to latch the
`address to an appropriate row within the DRAM. The RAS
`control Signal must be maintained, while the column address
`is transmitted on the multiplexed address bus and the CAS
`control signal is asserted. Strobing the CAS control Signal
`will select the desired data word to be sensed from the
`addressed row. This word can then be transmitted back to the
`processor or direct memory access ("DMA") device via a
`memory controller, in the case of a read access. In instances
`of write access, the information on the data bus is written
`into the column amplifiers and the modified row is restored
`within the memory array.
`An important requirement of DRAM technology is that
`the RAS control Signal must be maintained during the time
`in which access is desired. If a burst of data is to be read,
`then the amount of time at which the RAS control signal is
`maintained asserted is limited by the need to periodically
`pre-charge the row being read. An improved memory
`architecture, known as synchronous DRAM (“SDRAM”),
`minimizes the need to maintain assertion of the RAS control
`Signal during a read access. SDRAM merely requires puls
`ing of the RAS control Signal only for the Set-up and hold
`times relative to a particular clock edge. The row being
`addressed by the pulsed RAS control signal will remain
`active until a deactivate command is given. In addition to the
`benefits of merely Strobing a RAS control Signal and there
`fore maximizing pre-charge time, the SDRAM architecture
`beneficially Synchronizes its commands to the memory bus
`clock, which is derived as a ratio of the processor clock.
`Thus, an SDRAM operation is said to be synchronized with
`the clock which operates the processor or central processing
`unit (“CPU”).
`The various commands, Such as RAS, CAS, activate, and
`deactivate, are given on a rising edge of the System clock.
`The deactivate command initiates the pre-charge operation
`of the previously accessed row, whereby Voltage upon the
`memory elements being read is restored from the latched
`values on the corresponding column amplifiers. The pre
`charge operation thereby Serves to restore charge on the read
`capacitors occurring during a Sense operation. Over time,
`however, the pre-charge operation will not be Sufficient to
`replace charge which "leaks” from the Storage capacitor. The
`Storage cell and, more particularly, capacitors within respec
`tive cells must therefore be periodically refreshed. Typically
`there is a maximum time over which every cell must be read
`and then written back (i.e., refreshed) to guarantee proper
`data retention. As such, the refresh operation of an SDRAM
`must be monitored So that each cell is timely recharged,
`either through a self-refresh technique or a CAS-before
`RAS (“CBR') refresh technique, for example. Regardless of
`the refresh technique chosen, the refresh mechanism gener
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`US 6,226,755 B1
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`The fetched data arise from partitions within the SDRAM
`System. Those partitions may include a minimum of one
`SDRAM chip. If an entire cache line is desired to be
`transferred within a Single System clock cycle, then the
`partition being read includes a plurality of SDRAM chips
`commonly connected through a chip Select Signal. The
`partitioned group of chips can be arranged on a Separate
`printed circuit board, such as that attributed to a DIMM.
`During the time in which one partition is being read (i.e.,
`data being transferred therefrom), another partition may
`undergo a refresh or pre-charge operation. However, the
`refresh or pre-charge operations which occur within any
`given partition do not occur consecutively between read
`requests attributed to another partition or another pair of
`partitions. In other words, the present transfer technique
`ensures the refresh and pre-fetch operations of one partition
`be separated in time by a read request attributed to another
`partition. In the example in which three partitions are used,
`the present transfer technique purposely interposes a read
`request to a Second partition between a pre-charge and
`refresh operations associated with a third partition. In this
`fashion, a read request to a first partition can initiate data
`transfer of N burst cycles (where N is preferably four or
`more), followed immediately by data burst cycles attributed
`to the Second partition read request, even though a pre
`charge or refresh operation may occur on the third partition
`in the interim.
`Enhancements to the data transfer bandwidth across the
`System memory bus appears "seamless', in that every Sys
`tem clock cycle performs a data transfer between the time in
`which the first data transfer cycle from the first partition
`begins, through the data transfer of the Second partition and
`culminating with the last data transfer of the first partition,
`even through refresh or pre-charge conditions exist within
`the third partition. The example of using three partitions
`within the SDRAM system is merely an example, and is
`used only to illustrate a particular instance in which overall
`data transfer is improved. It is understood, however, that
`other partition examples for transferS among those partitions
`can be employed to increase data transfer provided the
`partition not participating in data transferS undergoes non
`consecutive refresh and pre-charge, with a read request of
`another transfer interspersed therebetween, and the read
`request of one partition be spaced from the read request of
`another partition by the data burst length.
`According to one embodiment, a computer System is
`provided. The computer System comprises a partitioned
`SDRAM System operably coupled to, for example, a display.
`A first one of the partitions may be adapted to receive a read
`request N number of cycles after a Second one of the
`partitions receives a read request for dispatching N cycles of
`data to the display. A third one of the partitions initiates and
`concludes a refresh operation between the time in which the
`first and Second ones of the partitions receives correspond
`ing read requests. The refresh operation therefore begins and
`ends during the N cycles of the System clock which Separate
`the read request on the Second partition and the read request
`on the first partition. The partitions can comprise at least one
`SDRAM chip, wherein a grouping of SDRAM chips com
`prises a DIMM. Activating the chip Select Signal among the
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`chips of a partition will activate at least one internal bank
`among each of those chips consistent with the read request
`accepted by those chips.
`According to another embodiment, a synchronous DRAM
`system is provided. The SDRAM system includes a clocking
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`circuit coupled to produce a Sequence of clocking cycles
`upon the memory bus and initiated from the processor. The
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`clocking circuit forwards the clocking cycles to a first,
`second, and third set of SDRAM integrated circuits grouped
`into respective partitions. The first set of SDRAM chips is
`coupled to read a data burst of N clock cycles initiated from
`a first read request. The second set of SDRAM chips is
`coupled to read a data burst of N clock cycles initiated from
`a Second read request that occurs N clock cycles after the
`first read request. The first set of SDRAM chips is further
`coupled to read a data burst of N clock cycles initiated from
`a third read request that occurs N clock cycles after the
`second read request. A third set of SDRAM chips is coupled
`to initiate and culminate a Sequence of refresh cycles in the
`interim between the Second read request and the first read
`request.
`According to yet another embodiment, a method is pro
`vided for transferring data from an SDRAM system. The
`method includes providing a plurality of Successive clocking
`cycles to a first, second, and third partition of the SDRAM
`system. A first burst of data is transferred from the first
`partition. Immediately following transferal of the first burst
`of data, and absent any intervening clocking cycles, a Second
`burst of data is transferred from the second partition. While
`a portion of the third partition undergoes a refresh operation,
`a third burst of data is transferred from the first partition
`immediately after transferring the Second burst of data and
`absent any clocking cycles in the interim between transfer
`ring the second burst of data and the third burst of data.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Other objects and advantages of the invention will
`become apparent upon reading the following detailed
`description and upon reference to the accompanying draw
`ings in which:
`FIG. 1 is a block diagram of a computer System compris
`ing various buses and buS interface units,
`FIG. 2 is a block diagram of a partitioned SDRAM system
`which includes a group of data lines associated with at least
`one SDRAM integrated circuit, or chip, that is selectable via
`a chip Select Signal;
`FIG. 3 is a block diagram of a single SDRAM chip
`employing a mechanism for refreshing at least a portion of
`the of the SDRAM chip during times when banks internal to
`the chip are deactivated; and
`FIG. 4 is a timing diagram of a hidden refresh performed
`on one partition of the SDRAM system while the data
`transfer among the other partitions occurs in consecutive,
`seamless SDRAM clock cycles.
`While the invention may be modified and have alternative
`forms, specific embodiments thereof are shown by way of
`example in the drawings and will herein be described in
`detail. It should be understood, however, that the drawings
`and detailed description thereto are not intended to limit the
`invention to the particular form disclosed, but on the
`contrary, the intention is to cover all modifications, equiva
`lents and alternatives falling within the Spirit and Scope of
`the present invention as defined by the appended claims.
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`Turning to the drawings, FIG. 1 illustrates a computer 10
`having multiple buses, including a CPU bus, a meZZanine or
`PCI bus, and multiple peripheral buses. In the example
`shown, the peripheral buses include an ISA bus, an IDE bus
`and a IC bus. The CPU bus connects a CPU, or processor
`12, to a bus interface unit or northbridge 14. A cache
`memory 16 can be embodied within or external to CPU 12.
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`Petitioner AMD Ex-1008, 0007
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`Northbridge 14 provides an interface between compo
`nents clocked at dissimilar rates. According to one
`embodiment, northbridge 14 interfaces a slower PCI bus and
`a faster CPU bus. Northbridge 14 may also contain a
`memory controller which allows communication to and
`from system memory 18. A suitable system memory 18
`comprises SDRAM arranged in partitions. Four partitions 19
`are shown, however, it is noted that at least three partitions
`are needed and more than four partitions may be employed.
`Each partition may include at least one chip, wherein a
`plurality of chips, labeled “C”, may be interconnected by a
`chip select signal to form a DIMM, labeled “D’.
`Northbridge 14 may also include graphics Support to
`allow communication to a graphics accelerator and buffer
`20. A graphics Support, included within an advanced graph
`ics port such as the Accelerated Graphics Port (AGP),
`provides a high performance, component level interconnect
`targeted at three dimensional graphics display applications
`and is based on performance extensions or enhancements to
`PCI.
`AGP interfaces are generally Standard in the industry, the
`description of which is available from Intel Corporation.
`Generally Speaking, AGP is physically, logically, and elec
`trically independent of the PCI bus and is intended for the
`exclusive use of a display device 22. Display 22 is any
`electronic display upon which an image or text can be
`presented. A Suitable display 22 includes a cathode ray tube
`(CRT), a liquid crystal display (LCD), etc.
`Northbridge 14 is generally considered an application
`Specific chip Set, or application Specific integrated circuit
`(ASIC) that provides connectivity to various buses, and
`integrates other System functions Such as memory interface
`and P1394. System memory 18 is considered the main
`memory and refers to a portion of addressable memory that
`35
`the majority of memory accesses target. System memory 18
`is considered the largest continuous memory Space of com
`puter 10.
`Northbridge 14 contains various Sub-components, Some
`of which Serve as an interface to processor 12, System
`memory 18 and the graphics accelerator or frame buffer
`associated with display 22. A PCI interface is also included
`within northbridge 14 to allow accesses to and from input/
`output (I/O) devices 24 connected to the PCI bus.
`Also connected to the PCI bus is a Southbridge 26.
`Southbridge 26, similar to northbridge 14, includes various
`interfaces or controllers connected to respective buses. In the
`example shown, a controller or interface exists within South
`bridge 26 to handle communication between devices on the
`PCI bus, the IDE bus, the ISA bus and the I°C bus. The
`controllers, or interface units, Serve to adapt transfer proto
`cols from one bus to that of another. The interfaces also
`provide buffers to handle what could be substantially dis
`Similar transfer rates between buses.
`ASSociated with each bus is a hardware resource. For
`example, an IDE bus includes peripheral devices, a popular
`such device being an IDE hard disk drive. Of course,
`numerous other peripheral devices may be connected to the
`IDE bus, and thereby granted access to computer System 10.
`In the example shown, an ISA bus is also connected to
`Southbridge 26. According to known terminology, various
`controllers of multiple ISA type devices can be embodied
`upon a Single monolithic Substrate, deemed a Super I/O 30.
`For example, a floppy drive, a keyboard, and a Serial/parallel
`port may be coupled to the ISA bus via controllers within
`Super I/O 30. Information regarding Super I/O 30 can be
`obtained from, e.g., National Semiconductor Corp.
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`Coupled to Southbridge 26 may be another peripheral bus,
`such as the I°C bus. The I°C bus is a fairly well documented
`peripheral bus having a recognized buS transfer protocol,
`similar to the ISAbus and the IDE bus. An IC bus typically
`contains a Serial data line and a Serial clock line which make
`available numerous IC devices and illustrate connectivity
`of those devices with the I°C bus protocol.
`The input/output device, noted as reference numeral 32
`thereby includes any device which can operate according to
`the connected bus protocol, similar to I/O device 24 which
`operates according to, e.g., a PCI bus protocol. The I/O
`device 32 Serves to Send or receive command, addresses,
`and/or data to and from computer System 10 and, according
`to the present implementation, to and from System memory
`18.
`FIG. 2 illustrates one exemplary implementation of the
`partitioned SDRAM system 18. SDRAM system 18 is
`shown in FIG. 1 as having four partitions, and is shown in
`FIG. 2 has having at least three partitions 19a, 19b, and 19c.
`Each partition is shown having four SDRAM chips 34, 36
`and 38, respectively. However, it is noted that each partition
`19 need only contain one chip, depending on the desired
`memory bus throughput. Provided each partition contains at
`least one SDRAM chip, and therefore at least two internal
`(logical) banks of that chip, the partition can achieve Seam
`less data flow transfer hereof.
`Activation of one partition relative to the other occurs by
`forwarding a chip Select signal to the appropriate chip. For
`example, activating partition 19a occurs by presenting an
`activation Signal on the common chip Select Signal SX. The
`same applies to the other partitions 19b and 19c. If multiple
`chips are used within each partition, then the chip Select
`Signal is common to all chips within that partition. A benefit
`of linking multiple chips by a single chip Select within a
`DIMM is particularly beneficial if data bits are desired
`exceeding those from a Single chip. Thus, while a single
`SDRAM chip can currently output one or more data bits to
`a requester, linking multiple chips can provide whatever data
`width is needed, for example, linking Such chips can provide
`multiples of 8 or 16 bits in parallel (i.e., multiples of
`DQ0-DQ7 or multiples of DQ0-DQ15). In the example
`shown, four chips can be interconnected to concurrently
`output 32 bits during a single System clocking cycle. By
`coupling eight SDRAM chips together, each of which output
`eight bits, an entire cache line of four quadwords can be
`forwarded during four System clock cycles. Accordingly,
`each partition can be configured as, for example, a 64 pin
`single or dual bank DIMM. Details regarding the data
`transfer characteristics and the timing of the 8, 16, or
`possibly 64 bit data transfer from system memory 18 is
`described hereinbelow.
`FIG. 3 is a block diagram of various components used to
`illustrate operation of a single SDRAM chip 40. Chip 40 can
`be found within any of the various partitions 19, shown in
`FIGS. 1 and 2. The RAS, CAS, and CS signals are for
`warded from the processor or memory controller 42 to chip
`40 upon a control bus. A clocking Signal forwards a
`Sequence of clock cycles from the processor or memory
`controller 42 to various components within chip 40. Thus, all
`inputs and outputs of chip 42 are Synchronized with the
`System clock (CLK) to simplify System design with high
`Speed microprocessors.
`Row decoder 44 decodes an address during assertion of
`RAS, and column decoder 46 will decode an address during
`assertion of CAS. ASSertion of RAS occurs during activation
`of a bank to which a read request will be initiated. The read
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`Petitioner AMD Ex-1008, 0008
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`request will occur Several cycles later during the time in
`which CAS is asserted and a column address is read by
`column decoder 46. Depending on the status of address A11
`during assertion of RAS, an internal bank within memory
`array 48 will be selected by a bank selector 50. Selection
`involves activating that particular bank So that a Subsequent
`read cycle can occur from a column of the Selected row
`within that bank. The read cycle is initiated on a particular
`column and Subsequent, Successive columns are read in
`burst fashion without having to reassert RAS. Strobing the
`first column within the burst Sequence causes the data within
`the corresponding capacitor to be Sensed and placed within
`the column latch/amplifier 52. Depending on the CAS
`latency, the Sensed (latched) data will thereafter be placed on
`the data bus and transferred to the requesting device.
`A mode register 54 is included with SDRAM 40, which
`can be programmed with a CAS latency amount, a burst
`type, and a burst length. Details regarding the programmable
`mode register are generally known to those skilled in
`SDRAM integrated circuits and especially to those familiar
`with execution of an MRS command associated with con
`ventional SDRAM mode registers. Typically, the CAS
`latency, known as the delay between the read request com
`mand and the first output burst cycle, is a programmed
`number of minimum system clocking cycles. In most
`instances, the CAS latency can be programmed as one, two,
`or three clock cycles of the System clock.
`The SDRAM array 48 typically contains two independent
`array banks than can be accessed individually or in an
`interleaved fashion. Each bank can have one row activated
`at any given time. This is achieved by executing a bank
`activate command (ACTD) with the bank selected by the
`State of address terminal A11 and the specific row Selected
`by the state of address terminals A0-A10. Each bank must
`be deactivated before it can be activated again with a new
`row address. The two-bank design allows faster access of
`information on random rows at a higher rate of operation
`than that possible with a standard DRAM. This is accom
`plished by activating one bank with a row address as
`described previously, then while the data Stream is being
`accessed to/from that bank, the other bank is activated with
`another row address. Accordingly, a read request of the other
`bank can occur while the first bank data transfer occurs.
`When the data stream to or from the first bank is complete,
`the data Stream to or from the Second bank commences
`without interruption, i.e., is "seamless'. Operations can
`continue in this interleaved ping-pong fashion. The mecha
`nism for activating and deactivating a bank is generally
`known and set forth in numerous SDRAM specifications,
`Such as the technical reference for Texas Instruments, Part
`No. TMS626162 (herein incorporated by reference).
`Either a Single bank or both banks can be deactivated, or
`placed in a pre-charge mode where deactivation of the banks
`is dependent on the status of the address A10 terminal. The
`chip select, CS, attributed to each SDRAM chip is used to
`Select or deselect that chip for command entry. The chip
`Select input therefore provides a means for using multiple
`SDRAM chips in SDRAM systems that require multiple
`memory device decoding. Details regarding a SeamleSS read
`among multiple partitions operable from the chip Select
`Signal are set forth in the timing diagram of FIG. 4.
`FIG. 4 illustrates three partitions, a first partition trans
`action diagram 60, a Second partition transaction diagram
`62, and a third partition transaction diagram 64. Each
`partition can comprise at least one SDRAM chip, having a
`pair of internal, or logical, banks. In the example shown,
`internal banks of partition 60 are shown; however, banks for
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`the other partitions are not shown for Sake of drawing
`brevity and clarity. In the example provided, only three
`partitions are shown, wherein the first partition initiates a
`first read request cycle, followed by a read request within the
`Second partition, and then followed by a read request again
`in the first partition (albeit in another internal bank of that
`partition). The example illustrates three consecutive fetches
`from the partitioned SDRAM system, beginning with an
`activation operation occurring at the first System clock cycle
`activation operation, or command. It is assumed that all
`three partitions have been activated by an appropriately
`timed activate command prior to the respective read request
`commands. The result of activation operation is to Select a
`particular bank 60a of partition 60. Assuming the activation
`command to the first bank 60a from the first partition
`pre-exists the read request command, a chip Select Signal
`will be sent to the SDRAM chip or chips within the first
`partition, as noted by the assertion of CSX at clocking cycle
`4. While not shown, activation is triggered from the status of
`address A11 and a row address on the memory address bus
`A0-A9. The read request “R” on bank 60a is triggered at the
`first column address on the address bus A0-A9, indicated by
`column CXN, denoted as column N of the first partition X.
`After a CAS latency has expired, t, data appears upon
`the data bus, wherein the first cycle of data is denoted as
`DOX, attributed to data of the first read request within the
`first partition X. In the interim between the read request of
`the first partition and data thereafter being transmitted, the
`Second partition (Z) can be activated and the third partition
`(Y) deactivated. Activation of the second partition is shown
`by reference numeral A attributed to, for example, DIMM Z
`or partition Z. A pre-charge command can be issued to the
`third partition 64 in the interim between the read request of
`partition 60 and the data transfer resulting from that read
`request. The pre-charge command is shown as PR of third
`partition 64. Proper timing of the activation command of the
`Second partition 62 is not dependent on timing of the
`pre-charge command of the third partition 64. Specifically,
`the read request resulting from the activation command of
`the Second partition occurs approximately four clock cycles
`after the first partition read request. Thus, the first partition
`read request is shown as occurring on the fourth clocking
`cycle, and the read request of the Second partition is shown
`to occur on the eighth clocking cycle. Thus, the third
`partition read request is concurrent with the chip Select of the
`Z (second) partition, and is concurrent with the starting
`column address CSN forwarded to that parti