Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2020-00985
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER RESPONSE
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`Page
`Introduction ...................................................................................................... 1
`Overview Of The ’134 Patent. ......................................................................... 3
`A.
`Technical Background ........................................................................... 4
`1.
`SRAM/DRAM ............................................................................ 4
`2.
`On-Chip Memories ..................................................................... 5
`3.
`Input/Output Devices .................................................................. 5
`4.
`Burst Memory Access ................................................................. 6
`Advantages Of The ’134 Patent. ........................................................... 7
`1.
`Advantages Over The Prior Art ................................................ 10
`III. AMD’s Prior Art References Differ From The Teachings Of The ’134
`Patent. ............................................................................................................ 11
`A. Wada Is Directed To Preventing Interruptions In Between
`Bursts. .................................................................................................. 11
`Barrett Is Directed To Improving High Speed Mass Data
`Communications Between Input/Output (I/O) Devices Over A
`Bus. ...................................................................................................... 12
`1.
`Technical Background Of Burst Transfer
`Communications Between I/O Devices In Computing
`Systems. .................................................................................... 16
`IV. Person Of Ordinary Skill In The Art. ............................................................ 20
`V.
`Claim Construction ........................................................................................ 21
`A. All Challenged Claims: “non-interruptible” ....................................... 21
`B.
`Claim 16: “means for reading data ... / means for generating a
`predetermined number of said internal address signals in
`
`B.
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`B.
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`U.S. Patent No. 6,651,134
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ....................................................... 21
`VI. Ground 1a: Claims 1-3, 8, 12-13, and 16-17 Are Not Anticipated By
`Wada. ............................................................................................................. 22
`A. Wada Does Not Disclose “generating a predetermined number
`of said internal address signals”. ....................................................... 23
`1. Wada’s Conventional Embodiment Does Not Generate A
`Predetermined Number Of Internal Address Signals. .............. 24
`2. Wada’s Second Embodiment Does Not Generate A
`Predetermined Number Of Internal Address Signals. .............. 25
`B. Wada Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 27
`1.
`The Burst Procedure In Wada’s Conventional And
`Second Embodiments May Be Terminated By Failing To
`Maintain The External Advance Signal. ................................... 28
`2. Wada Does Not Disclose Preventing Interruptions Within
`A Burst. ..................................................................................... 32
`VII. Ground 2: Claims 1-4, 8, 12-14, and 16-17 Are Not Obvious Over
`Wada. ............................................................................................................. 32
`VIII. Ground 2a: Claims 1-4, 8, 12-14, and 16-17 Are Not Obvious Over
`Wada In Combination With Barrett. ¶ ........................................................... 33
`A.
`The Combination Of Wada And Barrett Does Not Render
`Obvious “generating a predetermined number of said internal
`address signals”. ................................................................................. 34
`The Combination Of Wada And Barrett Does Not Render
`Obvious “wherein said generation of said predetermined
`number of internal address signals is non-interruptible”. ................. 35
`C. A POSITA Would Not Have Been Motivated To Combine
`Wada And Barrett To Arrive At The Challenged Claims. .................. 36
`
`B.
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`U.S. Patent No. 6,651,134
`1. Wada And Barrett Describe Different Bursts. .......................... 37
`2. Wada And Barrett Are Directed To Different Operational
`Procedures. ................................................................................ 38
`3. Wada And Barrett’s Different Systems Operate At
`Different Speeds And Scales Of Data. ...................................... 42
`4. Wada And Barrett’s Different Systems Operate
`According To Different Timing Requirements. ....................... 43
`Combining Wada And Barrett Would Destroy A Key
`Objective Of Each Reference. ................................................... 46
`6. Wada And Barrett Are Not Directed To The Same
`Purpose. ..................................................................................... 47
`AMD Has Not Provided A Reason Why A POSITA
`Would Have Combined Elements From Wada And
`Barrett In The Way The Invention Of The ’134 Patent
`Does........................................................................................... 47
`D. A POSITA Would Not Have Had A Reasonable Expectation Of
`Success In Combining Wada And Barrett. ......................................... 48
`IX. Claims 4-7, 18-20 Are Not Obvious Over Wada Alone, Wada In
`Combination With Barrett, Or In Combination With The Asserted
`Secondary References. ................................................................................... 50
`A.
`Claims 4-7 and 18-20 Are Not Obvious Over Wada In
`Combination With Fujioka (Ground 3). .............................................. 50
`Claims 9-11, 14-15, And 21 Are Not Obvious Over Wada In
`Combination With Reeves or Lysinger. .............................................. 51
`Claims 4-7 and 18-20 Are Not Obvious Over Wada In
`Combination With Barrett And Fujioka (Ground 3a). ........................ 52
`Claims 9-11, 14-15, And 21 Are Not Obvious Over Wada In
`Combination With Barrett and Reeves or Lysinger. ........................... 52
`
`C.
`
`D.
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`iii
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`5.
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`7.
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`B.
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`Case IPR2020-00985
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`U.S. Patent No. 6,651,134
`X. Objective Indicia Of Non-Obviousness Further Demonstrate That The
`Challenged Claims Are Not Obvious Over Wada, Alone Or In
`Combination With The Secondary References. ............................................ 53
`A. A Nexus Exists Between The Claimed Invention Of The ’134
`Patent And Non-Interruptible DDR SDRAM Technology. ................ 54
`1.
`Claim 1 ...................................................................................... 58
`Element 1p: A circuit comprising ................................... 58
`
`Element 1a: a memory comprising a plurality of
`
`storage elements each configured to read and write
`data in response to an internal address signal; and ......... 58
`Element 1b: a logic circuit configured to generate a
`predetermined number of said internal address
`signals in response to (i) an external address
`signal, (ii) a clock signal and (iii) one or more
`control signals, wherein said generation of said
`predetermined number of internal address signals
`is non-interruptible. ........................................................ 60
`2.
`Claims 16 and 17....................................................................... 63
`The Claimed Invention Of The ’134 Patent Solves A Long-Felt
`Need. .................................................................................................... 64
`The Secondary Considerations Of Non-Obviousness Provide
`An Independent Basis For Confirming The Patentability Of All
`Claims. ................................................................................................. 67
`XI. Conclusion ..................................................................................................... 67
`
`
`B.
`
`C.
`
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`ActiveVideo Networks, Inc. v. Verizon Comm’ns, Inc.,
`694 F.3d 1312 (Fed. Cir. 2012) .....................................................................47
`Apple Inc. v. Int’l Trade Comm’n,
`725 F.3d 1356 (Fed. Cir. 2013) .............................................................. 53, 54
`Cont’l Can Co. v. Monsanto Co.,
`948 F.2d 1264 (Fed. Cir. 1991) .....................................................................22
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) ........................................................ 51, 52, 53
`In re Huai-Hung Kao,
`639 F.3d 1057 (Fed. Cir. 2011) .....................................................................54
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) .....................................................................48
`Johns Manville Corp. v. Knauf Insulation, Inc.,
`Case IPR2018-00827, Paper 9 (PTAB Oct. 16, 2018) (precedential) ...........48
`KSR Int’l. Co. v. Teleflex Inc.,
`550 U.S. 398, 127 S. Ct. 1727 (2007) ...........................................................48
`Lectrosonics, Inc. v. Zaxcom, Inc.,
`Case IPR2018-01129, Paper 33 (PTAB Jan. 24, 2020) ................................54
`Metalcraft of Mayville, Inc. v. Toro Co.,
`848 F.3d 1358 (Fed. Cir. 2017) .....................................................................38
`Microsoft Corp. v. Biscotti, Inc.,
`878 F.3d 1052 (Fed. Cir. 2017) .....................................................................22
`Mintz v. Dietz & Watson, Inc.,
`679 F.3d 1372 (Fed. Cir. 2012) .....................................................................53
`
`v
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`Page(s)
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359 (Fed. Cir. 2008) .....................................................................22
`PAR Pharm., Inc. v. TWI Pharms., Inc.,
`773 F.3d 1186 (Fed. Cir. 2014) .....................................................................22
`Samsung Elecs. Co., Ltd. v. Elm 3DS Innovations, LLC,
`925 F.3d 1373 (Fed. Cir. 2019) .....................................................................49
`Stratoflex, Inc. v. Aeroquip Corp.,
`713 F.2d 1530 (Fed. Cir. 1983) .....................................................................53
`TQ Delta, LLC v. Cisco Sys., Inc. et al.,
`942 F.3d 1352 (Fed. Cir. 2019) .....................................................................47
`Transocean Offshore Deepwater Drilling, Inc. v. Maersk Drilling USA, Inc.,
`699 F.3d 1340 (Fed. Cir. 2012) .............................................................. 53, 54
`Trivascular, Inc. v. Samuels,
`812 F.3d 1056 (Fed. Cir. 2016) .....................................................................36
`Unigene Labs., Inc. v. Apotex, Inc.,
`655 F.3d 1352 (Fed. Cir. 2011) .....................................................................33
`Wyers v. Master Lock Co.,
`616 F.3d 1231 (Fed. Cir. 2010) .....................................................................54
`
`
`
`
`
`All emphases are added unless otherwise indicated.
`
`This paper includes color illustrations and should be viewed in color.
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
`
`Exhibit No.
`2001
`2002
`2003
`
`2004
`2005
`2006
`2007
`
`2008
`2009
`
`2010
`
`2011
`
`2012
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`2013
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`2014
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`2015
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`2016
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`2017
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`2018
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`2019
`2020
`
`DESCRIPTION
`U.S. Patent No. 5,729,504 to Cowles (“Cowles”)
`U.S. Patent No. 6,289,138 to Yip (“Yip”)
`Declaration In Support Of Patent Owner Monterey Research, LLC’s
`Unopposed Motion For Admission Pro Hac Vice Of Michael A.
`Wueste.
`Declaration Of Michael C. Brogioli, Ph.D.
`Curriculum Vitae Of Michael C. Brogioli, Ph.D.
`2021-02-12 Deposition Transcript of Dr. R. Jacob Baker.
`Excerpts Of R. JACOB BAKER ET AL., DRAM CIRCUIT DESIGN
`FUNDAMENTAL AND HIGH-SPEED TOPICS, IEEE Press (2008)
`https://www.transcend-info.com/Support/FAQ-296
`PCI Local Bus Specification, Production Version Revision 2.1 (June
`1, 1995)
`JEDEC Standard – Double Data Rate (DDR) SDRAM, JESD79F,
`JEDEC Solid State Technology Association.
`JEDEC Standard – DDR2 SDRAM Specification, JESD79-2B,
`JEDEC Solid State Technology Association.
`JEDEC Standard – Low Power Double Data Rate 3 (LPDDR3),
`JESD209-3, JEDEC Solid State Technology Association.
`JEDEC Standard – Low Power Double Data Rate 4 (LPDDR4),
`JESD209-4, JEDEC Solid State Technology Association.
`JEDEC Standard – DDR3 SDRAM Standard, JESD79-3F, JEDEC
`Solid State Technology Association.
`JEDEC Standard – DDR4 SDRAM, JESD79-4B, JEDEC Solid State
`Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR5) SGRAM
`Standard, JESD212C, JEDEC Solid State Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR5X) SGRAM
`Standard, JESD232A, JEDEC Solid State Technology Association.
`JEDEC Standard – Graphics Double Data Rate (GDDR6) SGRAM
`Standard, JESD250B, JEDEC Solid State Technology Association.
`https://www.intel.com/pressroom/kits/quickrefyr.htm
`https://web.archive.org/web/20000818114318/http://www.cypress.c
`om/press/releases/990726.html
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`All citations to specific pages of exhibits follow the pagination added to those
`
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
`
`
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`Case IPR2020-00985
`U.S. Patent No. 6,651,134
`Introduction
`I.
`
`The Board should reject all Grounds of AMD’s Petition. The ’134 Patent—
`
`which was filed in February 2000 based on the work of inventor Cathal Phelan at
`
`Cypress Semiconductor Corporation—is directed to novel and non-obvious designs
`
`and procedures for improving the efficiency and speed of memories conducting
`
`“burst” operations to generate multiple memory addresses using a single initial
`
`address. Particularly, the ’134 Patent improves upon prior art burst operations by
`
`generating a predetermined number of addresses and rendering the generation of
`
`such addresses non-interruptible. The novel designs and procedures of the ’134
`
`Patent greatly improved the performance and efficiency of dynamic random access
`
`memory (“DRAM”), as well as synchronous DRAM (“SDRAM”) and double data
`
`rate SDRAM (“DDR SDRAM”).
`
`But Wada, the foundation for each of AMD’s grounds, does not disclose non-
`
`interruptible generation of a predetermined number of addresses. As the Board
`
`recognized in the Institution Decision (Paper 13, “DI”), Wada only describes
`
`eliminating data-free periods between bursts, not making any single burst operation
`
`non-interruptible. And Wada does not disclose generating a predetermined number
`
`of addresses. Instead, Wada allows for both (1) termination of a burst and (2)
`
`generation of more than AMD’s alleged number of internal addresses. Indeed,
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`AMD’s own expert admits that Wada discloses no means of preventing the
`
`generation of more than the alleged numbers of internal addresses.
`
`Faced with Wada’s deficiencies, AMD attempts to combine Wada with
`
`Barrett. But Barrett does not cure those problems. Barrett describes a burst transfer
`
`protocol for managing data transmissions between multiple diverse devices, such as
`
`peripheral devices like printers and keypads, attached to a common bus in a
`
`computing system, not accessing data within a memory. Though they share similar
`
`nomenclature, burst modes in memories and burst transfer protocols for
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`communication between diverse devices are considerably different, and involve
`
`different timing requirements, different operational considerations, and different
`
`technical specifications. Indeed, AMD’s expert admits that protocols for managing
`
`communications between devices—like in Barrett—would not necessarily apply to
`
`a protocol designed to manage accesses to memory—like in Wada. Moreover,
`
`Barrett’s burst transfer protocol does not disclose the non-interruptible generation of
`
`internal address signals—it explicitly requires pauses during a data transmission
`
`between sending and receiving devices attached to a bus to give the sending device
`
`the time necessary to buffer data for transmission. A person of ordinary skill in the
`
`art (“POSITA”) would not have been motivated to combine Wada and Barrett to
`
`prevent interrupting bursts. In short, all of AMD’s Grounds based upon the
`
`combination of Wada and Barrett also fail.
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`U.S. Patent No. 6,651,134
`AMD’s various other secondary references do not salvage its Petition. And
`
`compelling objective evidence of nonobviousness—long-felt but unmet need—
`
`further counsels against any of AMD’s proposed obviousness combinations.
`
`AMD’s Petition should be rejected in full.
`
`II. Overview Of The ’134 Patent.
`The ’134 patent teaches a novel design and operation for memories, such as a
`
`Static Random Access Memory (SRAM) or a Dynamic Random Access Memory
`
`(DRAM), operating in burst mode. In burst mode, a memory can provide data from
`
`multiple locations within the memory using a single external address, thereby
`
`increasing efficiency and reducing activity on address and control buses connected
`
`to the memory. (Ex-1001, 1:11-13; Brogioli Declaration (“Ex-2004”), ¶72.) Before
`
`the ’134 Patent, burst mode in both conventional SRAMs and DRAMs had
`
`drawbacks, particularly a susceptibility to interruptions. In a conventional SRAM,
`
`burst mode could be “started and stopped in response to a control signal.” (Ex-1001,
`
`1:15-18; Ex-2004, ¶72.) Using burst mode in a conventional DRAM was “difficult
`
`because of the need to refresh” data within the memory cell (Ex-1001, 1:26-27; Ex-
`
`2004, ¶72), which might necessitate interrupting the burst application and thus
`
`greatly lengthen the amount of time required for accessing data. (Ex-1001, 1:27-36;
`
`Ex-2004, ¶72.) As such, the ’134 Patent explains that it “would be desirable to have
`
`a memory device that has a fixed burst length.” (Ex-1001, 1:44-45; Ex-2004, ¶72.)
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`To address these issues, the’134 Patent proposes an integrated circuit comprising a
`
`memory and a logic circuit which fixes the length of the burst and renders it non-
`
`interruptible. (Ex-1001, Abstract, 1:44-45; Ex-2004, ¶73.)
`
`A. Technical Background
`SRAM/DRAM
`1.
`At the time of the ’134 patent, two common types of memory used in digital
`
`computer systems were Static Random Access Memory (“SRAM”), and Dynamic
`
`Random Access Memory (“ DRAM”). (Ex-2004, ¶48.) SRAMs use transistors to
`
`implement each memory cell within a given SRAM. (Ex-2004, ¶49.) DRAMs use
`
`a capacitor in addition to transistors to implement memory cells. (Ex-2004, ¶50.)
`
`However, capacitors leak charge over time. (Ex-1001, 1:19-24; Ex-2004, ¶50.) As
`
`such, each capacitor and respective memory cell in a DRAM implementation must
`
`be periodically recharged (or “refreshed”) so as to maintain the correct state. (Ex-
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`1001, 1:19-24; Ex-2004, ¶50.)
`
`In some memories,
`
`including, for example, synchronous DRAMs
`
`(“SDRAMs”), access to the memory is synchronous with a clock. (Ex-2008, 1; Ex-
`
`2004, ¶51.) For example, in synchronous DRAMs, data is transferred on the rising
`
`edge of a clock signal. (See, e.g., Ex-2006, 64:18-65:9; Ex-2004, ¶51.) In contrast,
`
`non-synchronous or asynchronous devices transfer data when a request is issued,
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`rather than in synchronicity with a clock signal. (See, e.g., Ex-2006, 63:21-64:17;
`
`Ex-2004, ¶52.)
`
`2. On-Chip Memories
`On-chip memory refers to memory that is included on the same die as a central
`
`processing unit (“CPU”) and other components. (Ex-2004, ¶53.) On-chip memory
`
`is typically mapped to an on-chip data bus, which means it is accessible very quickly.
`
`(Ex-2004, ¶53.) For example, load and store operations from a CPU to an on-chip
`
`memory may be of 8/16/32 bits in nature, and occur at rates in the hundreds of
`
`megahertz (“MHz”). (Ex-2004, ¶53.)
`
`Input/Output Devices
`
`3.
`Input/Output (“I/O”) devices include devices such as network cards, sound
`
`cards, graphics cards, and the like. (Ex-2004, ¶54.) Such I/O devices typically use
`
`a shared bus or interconnect that transmits data at much lower clock rates compared
`
`to accesses of on-chip memory. (Ex-2004, ¶¶54-55.) In addition, such data transfers
`
`between I/O devices may explicitly require intermediate pauses during the
`
`transmission phase depending on local buffer resources or the differing speeds of
`
`each I/O device. (See, e.g., Ex-1010, 2:30-41; Ex-2004, ¶55.)
`
`Additionally, I/O devices that request access to a shared bus must adhere to
`
`the processes and procedures of the protocol used to implement said shared bus.
`
`(Ex-2004, ¶55.) For example, an I/O device may need to request access to the bus,
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`wait for grant of access, and then only transmit data across said bus during the
`
`window of access. (Ex-2004, ¶56.) A sending I/O device may also need to handle
`
`various acknowledgements sent from a receiver of the data, or vice versa. (Ex-2004,
`
`¶56.) Lastly, access to the shared bus is typically arbitrated amongst multiple
`
`devices competing for access to it at any given point in time. (Ex-2004, ¶¶56-57.)
`
`Burst Memory Access
`
`4.
`During operation, a CPU issues read and write instructions to and from
`
`memory, including, for example, SRAM or DRAM. (Ex-2004, ¶58.) Such
`
`instructions read data into the CPU for computation or processing, and subsequently
`
`write data back into memory. (Ex-2004, ¶58.) Each of the operations incur overhead
`
`from the CPU in addition to the read/write instruction itself. (Ex-2004, ¶58.) For
`
`example, to read 32-bits of data from a given address, the CPU must first calculate
`
`the address to read from, issue a read instruction, and issue additional instructions to
`
`increment the already read address to a next address. (Ex-2004, ¶58.) Larger reads
`
`from memory may require multiple read/write instructions, and increase the
`
`associated overhead. (Ex-2004, ¶58.)
`
`Memory bursts improve upon this inefficiency. (Ex-2004, ¶59.) Rather than
`
`have a CPU explicitly generate all of the addresses and associated overhead for a
`
`given read/write instruction, a burst, or burst mode access, utilizes circuit logic to
`
`generate a series of memory address offsets automatically and return the series of
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`data to the CPU without the CPU explicitly having to generate each of said
`
`addresses. (Ex-2004, ¶59.) Increasing efficiency is important when designing
`
`memories, because it improves the data transfer rate: the speed with which data can
`
`be written to or read from the memory. (Ex-2004, ¶60.) The data transfer rate of a
`
`memory is particularly important because the speed of a CPU in a computer is
`
`limited by the speed with which the CPU can access the memory. (Ex-2004, ¶60.)
`
`If the memory reads data at a rate much slower than the processing speed of the
`
`CPU, the CPU will be waiting for data and will waste processing cycles. (See, e.g.,
`
`Ex-2006, 104:15-22; Ex-2004, ¶60.) As such, memory designs strove for data
`
`transfer rates as close to CPU speeds as possible. (Ex-2004, ¶61.)
`
`Further, the efficiency of burst mode access differed when employed in
`
`SRAM and DRAM memories, due to the need to refresh DRAMs. (Ex-1001, 1:19-
`
`24; Ex-2004, ¶62.) As such, integrated DRAMs “interrupted” the burst to refresh
`
`the capacitor, which increased the amount of time necessary to access data. (Ex-
`
`1001, 1:24-36; Ex-2004, ¶62.) This resulted in suboptimal burst performance for a
`
`given DRAM technology. (Ex-2004, ¶62.)
`
`B. Advantages Of The ’134 Patent.
`The benefits and advantages of the ’134 Patent include, inter alia, the ability
`
`to set a fixed burst length to suit application needs, have non-interruptible bursts,
`
`hide required DRAM refreshes inside a known fixed burst length of data words, and
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`operate at higher frequencies without needing interrupts to refresh data. (Ex-1001,
`
`1:58-67; Ex-2004, ¶84.)
`
`The disclosed memories of the ’134 Patent “may be configured to transfer a
`
`fixed number of words to or from the memory 104 in response to” internal and
`
`external signals. (Ex-1001, 3:6-8; Ex-2004, ¶¶73-79.) For example, in one
`
`embodiment shown in Figure 2, reproduced below, the address counter register 126
`
`of circuit 102 receives the signals ADDR_EXT, LOAD, and CLK, while the burst
`
`counter 128 receives the signals ADV and BURST. (Ex-1001, 3:65 – 4:2; Ex-2004,
`
`¶80.) The burst counter 128 presents a signal BURST_CLK—which contains “a
`
`number of pulses that has been programmed by the signal BURST”—to the address
`
`counter 126 when the signal ADV is asserted. (Ex-1001, 4:10-14; Ex-2004, ¶80.)
`
`An initial address may be loaded into the address counter register 126 by presenting
`
`the initial address in the external address signal ADDR_EXT and asserting the signal
`
`LOAD. (Ex-1001, 4:6-8; Ex-2004, ¶80.) The initial address identifies the starting
`
`point for accessing the memory array. (Ex-2004, ¶80.) The address counter register
`
`126 then “increment[s] an address in response to the signal BURST_CLK,” for a
`
`number of times that equals the number of pulses in the signal BURST_CLK as
`
`programmed by the burst counter 128 in response to the signal BURST. (Ex-1001,
`
`4:8-10; Ex-2004, ¶80.) As such, the predetermined number of internal addresses is
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`generated by incrementing the initial address based on the number of pulses from
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`the signal BURST_CLK.
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`(Ex-1001, Figure 2.)
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`The ’134 Patent teaches that the burst can be non-interruptible by preventing
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`the burst counter 128 from stopping the generation of internal addresses until the
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`fixed number is reached:
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`• “When the signal ADV is asserted, the circuit 100 will generally
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`begin transferring a predetermined number of words. The
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`transfer is generally non-interruptible.” (Ex-1001, 3:6-13.)
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`• “Once the circuit 102 has started generating the fixed number
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`of addresses, the circuit 102 will generally not stop until the
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`fixed number of addresses has been generated (e.g., a non-
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`interruptible burst).”
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`(Ex-1001, 3:25-28; Ex-2004, ¶¶81-83.)
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`Advantages Over The Prior Art
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`1.
`The non-interruptible generation of internal address signals presents an
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`advantage over prior art solutions that merely read or write a preset number of data
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`words or present options for continuously reading data from or writing data to the
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`memory. (Ex-2004, ¶85.) For example, the Patent and Trademark Office (“PTO”)
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`allowed the ’134 Patent over prior art such as US Patent No. 6,289,138 to Yip et al.
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`(Ex-2002, “Yip”.) Yip disclosed restricting rearbitration for a DRAM device so that
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`an interruptible burst is not interrupted until a preset number of data words has been
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`transferred. (Ex-1004, 0065; Ex-2004, ¶85.) But an interruptible burst “is not the
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`same as generating a predetermined number of internal address signals that is non-
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`interruptible.” (Ex-1004, 0065; Ex-2004, ¶85.)
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`Similarly, the ’134 Patent was allowed, and provides advantages, over prior
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`art that merely presented methods for continuously bursting data in and/or out of the
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`memory. (Ex-2004, ¶86.) For example, the PTO allowed the ’134 Patent over U.S.
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`Patent No. 5,729,504 to Cowles (Ex-2001 “Cowles”), which was directed to “an
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`ability to access a second row of memory while bursting data out of a first row (a
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`so-called ‘continuous BEDO,’ or ‘CBEDO’ architecture ...).” (Ex-1004, ¶¶0107-
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`0108; Ex-2004, ¶86). But the “ability to access a second row of memory while
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`bursting data out of a first row has little or nothing to do with whether a “burst”
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`can be interrupted.” (Ex-1004, 0107-0108; Ex-2004, ¶86.)
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`III. AMD’s Prior Art References Differ From The Teachings Of The ’134
`Patent.
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`A. Wada Is Directed To Preventing Interruptions In Between Bursts.
`Unlike the disclosed memories of the ’134 Patent, which address burst
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`memory access problems by fixing the length of the burst and rendering it non-
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`interruptible (Ex-1001, Abstract, 1:44-45), Wada is directed to a different problem
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`and provides a different solution. (Ex-2004, ¶87.) As the Board acknowledged,
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`Wada seeks to prevent “‘data output interruptions’ between bursts associated with
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`different addresses.” (DI, 13; Ex-2004, ¶89.) According to Wada, a problem with
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`conventional SRAMs is that data is not read in between burst memory operations:
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`“That is, a data free-period (an interruption in the flow of data output) is bound
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`to occur between two burst outputs [of data].” (Ex-1005, 5:50-51; Ex-2004, ¶88.)
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`To that end, as Dr. Brogioli confirms, Wada adds multiple “output registers”
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`(Ex-1005, Abstract) to conventional SRAMs, which registers retain data from the
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`memory array, such that the “semiconductor memory outputs in burst mode the
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`retained data from one output register while transferring the data read from memory
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`cells of the memory cell array to another output register. This makes it possible to
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`output a plurality of target data items in burst mode without interruption
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`therebetween.” (Ex-1005, 6:56-61; Ex-2004, ¶89.) In fact, as Dr. Brogioli confirms
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`(Ex-2004, ¶90), Wada describes preventing interruptions as preventing “data-free
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`periods” in between burst operations by overlapping burst outputs using multiple
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`output registers, and not preventing interruptions of the burst operations themselves,
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`e.g.:
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`“Operating in this fashion, the semiconductor memory of the
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`invention outputs in burst mode the retained data from one output
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`register while transferring the data read from the memory cell array to
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`another output register. This makes it possible to output a plurality of
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`target data items in burst mode without interruption therebetween.”
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`(Ex-1005, 7:62-67);
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`B.
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`Barrett Is Directed To Improving High Speed Mass Data
`Communications Between Input/Output (I/O) Devices Over A Bus.
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`Whereas the ’134 Patent describes an improved burst mode for accessing a
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`memory, Barrett is directed to “improving the speed and reducing the cost of burst
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`communications between different devices in a computer system.” (Ex-1010, 1:10-
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`13; Ex-2004, ¶91.) Burst access operations for memories and protocols that allow
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`burst data transfers between different devices in a computing system are
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`considerably different. (Ex-2004, ¶63.)
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`According to Barrett, modern computer systems must have several “defined
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`paths for communications” between processors and I/O devices, including “several
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`paths which must support high speed mass data transfer.” (Ex-1010, 1:26-31; Ex-
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`2004, ¶91.) The processors include, for example, CPUs. (Ex-1010, 1:19-26; Ex-
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`2004, ¶91.) The I/O devices include, for example, hard drives, printers, terminals,
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`input keypads, or other computers over a network. (Ex-1010, 1:19-26; Ex-2004,
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`¶91.) Support for such mass data transfers may be provided through a “burst data
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`transfer protocol.” (Ex-1010, 1:36-37; Ex-2004, ¶91.)
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`But burst communications between I/O devices in a computing system raise
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`problems, particularly where the sending and receiving devic