JEDEC
`STANDARD
`
`GRAPHICS DOUBLE DATA RATE
`(GDDR5X) SGRAM STANDARD
`
`Des m arais LLP
`
`JESD232A
`
`(Revision of JESD232, November 2015)
`
`AUGUST 2016
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
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`NOTICE
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`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
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`PLEASE!
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`This document is copyrighted by the JEDEC Solid State Technology Association
`and may not be reproduced without permission.
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`JEDEC Standard No. 232A
`
`Contents
`
`3
`
`SCOPE .................................................................................................................................................................. 1
`1
`2 GDDR5X SGRAM STANDARD OVERVIEW .............................................................................................2
`2.1
` Features ......................................................................................................................................................2
`FUNCTIONAL DESCRIPTION .......................................................................................................................3
`3.1
` Functional Overview ................................................................................................................................3
`3.2
` Signal State Terminology .........................................................................................................................4
`3.3
` Clocking .....................................................................................................................................................4
`3.4
` Addressing .................................................................................................................................................7
`3.5
` Bank Groups ............................................................................................................................................10
`3.6
` Address Bus Inversion (ABI) .................................................................................................................12
`3.7
` Read and Write Data Bus Inversion (DBI) ..........................................................................................13
`3.8
` Error Detection Code (EDC) ................................................................................................................. 15
`3.9
` VREFC and VREFD ............................................................................................................................... 19
`3.10 Temperature Sensor ................................................................................................................................22
`3.11 Duty Cycle Corrector ..............................................................................................................................23
`4 MODE REGISTERS ........................................................................................................................................ 24
`4.1
` Mode Register 0 .......................................................................................................................................26
`4.2
` Mode Register 1 .......................................................................................................................................28
`4.3
` Mode Register 2 .......................................................................................................................................30
`4.4
` Mode Register 3 .......................................................................................................................................32
`4.5
` Mode Register 4 .......................................................................................................................................33
`4.6
` Mode Register 5 ...................................................................................................................................... 35
`4.7
` Mode Register 6 ...................................................................................................................................... 36
`4.8
` Mode Register 7 .......................................................................................................................................37
`4.9
` Mode Register 8 .......................................................................................................................................39
`4.10 Mode Register 9 .......................................................................................................................................40
`4.11 Mode Register 10 .....................................................................................................................................40
`4.12 Mode Register 11 .....................................................................................................................................41
`4.13 Mode Register 12 to 14 ...........................................................................................................................41
`4.14 Mode Register 15 .....................................................................................................................................42
`5 DEVICE INITIALIZATION ...........................................................................................................................43
`5.1
` Power-up Sequence ................................................................................................................................43
`5.2
` Initialization with Stable Power ........................................................................................................... 45
`5.3
` Vendor ID ................................................................................................................................................ 46
`6 TRAINING .........................................................................................................................................................48
`6.1
` Interface Training Sequence ...................................................................................................................48
`6.2
` Address Training ....................................................................................................................................49
`6.3
` WCK2CK Training ..................................................................................................................................50
`6.3.1
` WCK Alignment at Pin Mode ............................................................................................................53
`6.3.2
` WCK Auto Synchronization ...............................................................................................................53
`6.3.3
` WCK2CK Training Examples .............................................................................................................53
`6.3.4
` Read and Write Latencies ...................................................................................................................55
`6.4
` READ Training........................................................................................................................................ 56
`6.4.1
` LDFF Command ...................................................................................................................................57
`6.4.2
` RDTR Command ..................................................................................................................................60
`6.5
` WRITE Training ......................................................................................................................................61
`6.5.1
` WRTR Command .................................................................................................................................62
`7 OPERATION .....................................................................................................................................................64
`7.1
` Commands .............................................................................................................................................. 64
`7.2
` Command, Address And Write Data Input Timings ........................................................................65
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`JEDEC Standard No. 232A
`
` No Operation (NOP) ..............................................................................................................................65
`7.3
` Mode Register Set ...................................................................................................................................66
`7.4
` Row Activation ........................................................................................................................................67
`7.5
` Write (WOM)............................................................................................................................................69
`7.6
` DQ Write Preamble ..............................................................................................................................76
`7.6.1
` Write Lower And Upper Bytes (WOML/WOMU)..............................................................................76
`7.7
` Write Data Mask (WDM/WSM).............................................................................................................78
`7.8
` READ ........................................................................................................................................................ 87
`7.9
` DQ Read Preamble ...............................................................................................................................94
`7.9.1
` READ with RDQS Mode .....................................................................................................................95
`7.9.2
`7.10 Precharge ..................................................................................................................................................96
`7.10.1 Auto Precharge .....................................................................................................................................97
`7.11 Refresh ......................................................................................................................................................97
`7.11.1 Refresh Command ...............................................................................................................................97
`7.11.2 Per-Bank Refresh Command ..............................................................................................................98
`7.12 Self Refresh ........................................................................................................................................... 101
`7.12.1 Hibernate Self Refresh .......................................................................................................................104
`7.12.2 Partial Array Self Refresh .................................................................................................................105
`7.13 Power-Down ..........................................................................................................................................105
`7.14 Low Frequency Modes .........................................................................................................................107
`7.15 Clock Frequency Change Sequence ...................................................................................................108
`7.16 Command Truth Tables .......................................................................................................................108
`8 OPERATING CONDITIONS .......................................................................................................................112
`8.1
` Absolute Maximum Ratings ................................................................................................................112
`8.2
` Pad Capacitances ..................................................................................................................................112
`8.3
` Package Electrical Specification...........................................................................................................113
`8.4
` Package Thermal Characteristics ........................................................................................................113
`8.5
` Electrostatic Discharge Sensitivity Characteristics ..........................................................................114
`8.6
` DC & AC Operating Conditions .........................................................................................................115
`8.7
` IDD Specifications and Test Conditions ............................................................................................119
`8.8
` AC Timings ............................................................................................................................................125
`8.9
` Clock-To-Data Timing Sensitivity ......................................................................................................131
`8.10 POD I/O System ....................................................................................................................................132
`PIN DEFINITION AND BALLOUT ...........................................................................................................137
`9.1
` Signal Description .................................................................................................................................137
`9.2
` Clamshell (x16) Mode ...........................................................................................................................138
`9.3
` Mirror Function (MF) Enable ..............................................................................................................141
`9.4
` Ballout .....................................................................................................................................................142
`10 PACKAGE OUTLINE ....................................................................................................................................144
`11 BOUNDARY SCAN .......................................................................................................................................145
`11.1 Test Pins .................................................................................................................................................145
`11.2 TAP Controller ......................................................................................................................................145
`11.3 TAP Registers ........................................................................................................................................147
`11.4 TAP Instruction Set ...............................................................................................................................150
`11.5 Boundary Scan Operation ....................................................................................................................151
`11.6 Interaction Between Boundary Scan and Normal Device Operation ...........................................152
`
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`JEDEC Standard No. 232A
`Page 1
`
`GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD
`(From JEDEC Board Ballot JCB-16-39, formulated under the cognizance of the JC-42.3 Subcommittee on
`DRAM Memories, item number 1827.99B (V1.2).
`
`1
`
`SCOPE
`
`This document defines the GDDR5X SGRAM memory standard, including features, device operation,
`electrical charactersitics, timings, signal pin assignments and package.
`The purpose of this standard is to define the minimum set of requirements for JEDEC standard compatible
`4 Gb through 16 Gb x32 GDDR5X SGRAM devices. System designs based on the required aspects of this
`standard will be supported by all GDDR5X SGRAM vendors providing JEDEC standard compatible
`devices. Some aspects of the GDDR5X standard such as AC timings were not standardized. Some features
`are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted
`for specifics.
`This standard was created based on the GDDR5 SGRAM standard (JESD212). Each aspect of the changes
`were considered and balloted. The accumulation of these ballots were then incorporated to prepare this
`GDDR5X SGRAM standard.
`
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`JEDEC Standard No. 232A
`Page 2
`
`2
`
`GDDR5X SGRAM STANDARD OVERVIEW
`
`/ 256 Mb x 16 (16 Mb x 16 x 16 banks)
`= 128 Mb x 32 ( 8 Mb x 32 x 16 banks)
`4 Gb
`= 192 Mb x 32 (12 Mb x 32 x 16 banks) / 384 Mb x 16 (24 Mb x 16 x 16 banks)
`6 Gb
`= 256 Mb x 32 (16 Mb x 32 x 16 banks) / 512 Mb x 16 (32 Mb x 16 x 16 banks)
`8 Gb
`12 Gb = 384 Mb x 32 (24 Mb x 32 x 16 banks) / 768 Mb x 16 (48 Mb x 16 x 16 banks)
`16 Gb = 512 Mb x 32 (32 Mb x 32 x 16 banks) / 1 Gb x 16
`(64 Mb x 16 x 16 banks)
`
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`
` FEATURES
`2.1
`• Single ended interface for command, address and data
`• Differential clock input CK_t/CK_c for ADD/CMD
`• Two differential clock inputs WCK_t/WCK_c, each associated with two data bytes (DQ, DBI_n, EDC)
`• Single Data Rate (SDR) commands (CK)
`• Double Data Rate (DDR) addresses (CK)
`• QDR and DDR operating modes:
`• QDR mode: Quad Data Rate (QDR) data (WCK); 16n prefetch architecture with 512 bit per array
`read or write access; burst length 16
`• DDR mode: Double Data Rate (DDR) data (WCK); 8n prefetch architecture with 256 bit per array
`read or write access; burst length 8
`• 16 internal banks
`• 4 bank groups for tCCDL = 3 tCK and 4 tCK
`• Programmable read latency: 5 to 36 tCK; programmable write latency: 1 to 7 tCK
`• Write data mask function via address bus (single/double/quad byte mask)
`• Data bus inversion (DBI) & address bus inversion (ABI)
`• Input/output PLL/DLL
`• Address training: address input monitoring via DQ/DBI_n/EDC pins
`• WCK2CK clock training with phase information via EDC pins
`• Data read and write training via READ FIFO (depth = 6)
`• Read FIFO pattern preload by LDFF command
`• Direct write data load to READ FIFO via WRTR command
`• Consecutive read of READ FIFO via RDTR command
`• Read/write EDC on/off mode
`• Programmable EDC hold pattern for CDR
`• Read/write data transmission integrity secured by cyclic redundancy check (CRC-8)
`• Programmable CRC read latency = 1 to 4 tCK; programmable CRC write latency = 7 to 14 tCK
`• Low Power modes
`• RDQS mode on EDC pins
`• On-chip temperature sensor with read-out
`• Auto precharge option for each burst access
`• Auto refresh mode with per-bank refresh option
`• Temperature sensor controlled self refresh rate
`• Optional digital tRAS lockout
`• On-die termination (ODT) for all high-speed inputs
`• Pseudo open drain (POD-135) compatible outputs
`• ODT and output driver strength auto-calibration with external resistor ZQ pin (120 Ω)
`• Programmable termination and driver strength offsets
`• Internal VREF for data inputs with programmable levels
`• Selectable external or internal VREF for address / command inputs
`• Vendor ID for device identification
`• Mirror function with MF pin
`• IEEE 1149.1 compliant boundary scan
`• 1.35 V supply voltage for device operation (VDD) and I/O interface (VDDQ)
`• 1.8 V pump voltage (VPP)
`• 190 ball BGA package
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`JEDEC Standard No. 232A
`Page 3
`
`3
`
`FUNCTIONAL DESCRIPTION
`
` FUNCTIONAL OVERVIEW
`3.1
`The GDDR5X SGRAM is a high speed dynamic random-access memory designed for applications
`requiring high bandwidth. It is internally configured as 16-bank memory and contains the following
`number of bits:
`4 Gb has 4,294,967,296 bits
`6 Gb has 6,442,450,944 bits
`8 Gb has 8,589,934,592 bits
`12 Gb has 12,884,901,888 bits
`16 Gb has 17,179,869,184 bits
`The GDDR5X SGRAM’s high-speed interface is optimized for point-to-point connections to a host
`controller. On-die termination (ODT) is provided for all high-speed interface signals to eliminate the need
`for termination resistors in the system.
`The GDDR5X SGRAM supports two operating modes which mainly differ in the internal prefetch and
`DQ/DBI_n pin to WCK clock frequency ratio. The operating mode is set by a mode register bit:
`• In Quad Data Rate (QDR) mode the interface transfers four 32-bit wide data words per WCK clock
`cycle to/from the I/O pins. Corresponding to the 16-n prefetch a single write or read access consists of a
`512 bit wide, two CK clock cycle data transfer at the internal memory core and sixteen corresponding
`32 bit wide one-quarter WCK clock cycle data transfers to the I/O pins.
`• In Double Data Rate (DDR) mode the interface transfers two 32-bit wide data words per WCK clock
`cycle to/from the I/O pins. Corresponding to the 8-n prefetch a single write or read access consists of a
`256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding 32
`bit wide one-half WCK clock cycle data transfers to the I/O pins.
`Read and write accesses to the GDDR5X SGRAM are burst oriented; an access starts at a selected location
`and consists of a total of sixteen data words in QDR mode and eight data words in DDR mode. Accesses
`begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE
`command. The address bits registered coincident with the ACTIVATE command and the next rising CK_c
`edge are used to select the bank and the row to be accessed. The address bits registered coincident with the
`READ or WRITE command and the next rising CK_c edge are used to select the bank and the column
`location for the burst access.
`This standard includes all features and functionality required for JEDEC GDDR5X SGRAM devices. Users
`benefit from knowing that any system design based on the required aspects of the standard are supported
`by all GDDR5X SGRAM vendors; conversely users seeking to use any superset specifications bear the
`responsibility to verify support with individual vendors.
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`JEDEC Standard No. 232A
`Page 4
`
` SIGNAL STATE TERMINOLOGY
`3.2
`The GDDR5X SGRAM will be operated in both ODT enable (terminated) and ODT disable (unterminated)
`modes. For highest data rates it is recommended to operate in the ODT enable mode. ODT disable mode is
`designed to reduce power and may operate at reduced data rates. There exist situations where ODT enable
`mode can not be guaranteed for a short period of time, for example during power-up.
`Four terminologies define the state of a device pin (GDDR5X SGRAM or controller) during operation. The
`state of the bus will be determined by the combination of the device pins connected to the bus in the
`system. For example, with GDDR5X it is possible for the device pin to be tristated while the controller pin
`is High or ODT. In both cases the bus would be High if the ODT is enabled.
`Device pin signal level:
`• High: a device pin drives the Logic “1” state.
`• Low: a device pin drives the Logic “0” state.
`• High-Z: a device pin is tristate.
`• ODT: a device pin terminates with ODT setting, which could be terminating or tristate depending on
`mode register setting.
`Bus signal level:
`• High: one device on the bus is High and all other devices on bus are either ODT or High-Z. The voltage
`level on the bus would be nominally VDDQ.
`• Low: one device on the bus is Low and all other devices on bus are either ODT or High-Z. The voltage
`level on the bus would be nominally VOL(DC) if ODT is enabled, or VSSQ if High -Z.
`• High-Z: all devices on the bus are High-Z. The voltage level on bus is undefined as the bus is floating.
`• ODT: at least one device on the bus is ODT and all others are High-Z. The voltage level on the bus
`would be nominally VDDQ.
`
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` CLOCKING
`3.3
`The GDDR5X SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at
`every rising edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of
`CK_c.
`The data interface uses two differential forwarded clocks WCK_t and WCK_c, each associated with two
`data bytes. WCK_t and WCK_c are continuously running and operate at twice the frequency of the
`command/address clock (CK_t/CK_c). A PLL/DLL is associated with each WCK pair. The use of the PLL/
`DLL is mandatory in QDR mode and vendor specific in DDR mode.
`• QDR mode uses a quad data rate data interface and a 16n-prefetch architecture for DQ/DBI_n, and a
`double data rate data interface and 8n-prefetch architecture for EDC. The PLL/DLL generates four
`equally spaced clock edges per WCK clock cycle. QDR means that four DQ/DBI_n data words per
`WCK cycle are registered at these internally generated clock edges. DDR means that two EDC data
`words per WCK cycle are registered at every second of these internally generated clock edges.
`• DDR mode uses a double data rate data interface and an 8n-prefetch architecture for DQ/DBI_n/EDC.
`DDR means that the data is registered at every rising edge of WCK_t and rising edge of WCK_c.
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`JEDEC Standard No. 232A
`Page 5
`
`CLOCKING (cont’d)
`3.3
`Table 1 and Figure 1 illustrate the clock and interface signal relationship for both QDR and DDR operating
`modes.
`Table 1 — Example Clock and Interface Signal Frequency Relationship
`
`PIN
`CK_t, CK_c
`Command
`Address
`WCK_t, WCK_c
`DQ, DBI_n
`EDC
`
`QDR MODE
`1.5
`1.5
`3.0
`3.0
`12.0
`6.0
`
`DDR MODE
`1.5
`1.5
`3.0
`3.0
`6.0
`6.0
`
`UNIT
`GHz
`Gbps/pin
`Gbps/pin
`GHz
`Gbps/pin
`Gbps/pin
`
`CK_c
`CK_t
`
`COMMAND
`
`ADDRESS
`
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`WCK_t
`WCK_c
`DQ, DBI_n
`(QDR Mode)
`DQ, DBI_n
`(DDR Mode)
`EDC
`(QDR + DDR Modes)
`NOTE 1 Figure 1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram.
`
`Figure 1 — GDDR5X Clocking and Interface Relationship
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`JEDEC Standard No. 232A
`Page 6
`
`3.3
`
`CLOCKING (cont’d)
`
`Controller
`
`ADD/CMD centered with CK_t/CK_c
`
`ADD/CMD
`
`QD
`
`ADD/CMD
`
`CK_t/CK_c
`(1.5 GHz)
`
`Oscillator
`
`PLL/DLL
`Data Tx/Rx
`
`early/late
`
`core
`logic
`
`Clock Phase
`Controller
`
`Phase detector/
`accumulator
`
`DQ
`
`Receiver
`clock
`
`WCK_t/
`WCK_c
`(3 GHz)
`
`DATA
`(QDR mode:
`12 Gbps)
`(DDR mode:
`6 Gbps)
`
`early/late from
`calibration data
`
`DQ
`
`D Q
`
`Clock Phase
`Controller
`
`GDDR5X SGRAM
`CMD sampled by CK_t/CK_c as SDR
`ADD sampled by CK_t/CK_c as DDR
`
`QD
`
`DRAM
`core
`
`WCK2CK
`Alignment
`
`D Q
`
`To EDC pin
`
`PLL/DLL
`
`/2
`
`(DDR mode only)
`
`DQ
`
`WCKint
`QDR mode: 3.0 GHz
`DDR mode: 1.5 GHz
`
`QD
`
`DRAM
`core
`
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`Figure 2 — Block Diagram of an Example Clock System
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`JEDEC Standard No. 232A
`Page 7
`
` ADDRESSING
`3.4
`GDDR5X SGRAMs use a double data rate address scheme to reduce pins required on the device as shown
`in Table 2. The addresses should be provided in two parts; the first half is latched on the rising edge of
`CK_t along with the command pins such as RAS_n, CAS_n and WE_n; the second half is latched on the
`next rising edge of CK_c.
`The use of DDR addressing allows all address values to be latched in at the same rate as the SDR
`commands. All addresses related to command access have been positioned for latching on the initial rising
`edge for faster decoding.
`
`Clock
`
`Rising CK_t
`
`Rising CK_c
`
`Table 2 — Address Pairs
`
`Address Pins
`
`BA3
`
`A3
`
`BA2
`
`A4
`
`BA1
`
`A5
`
`BA0
`
`A2
`
`A14
`
`A15
`
`A12
`
`A13
`
`A11
`
`A6
`
`A10
`
`A0
`
`A9
`
`A1
`
`A8
`
`A7
`
`The addressing includes support for 4 Gb to 16 Gb densities and both QDR and DDR operating modes as
`shown in Table 3.
`
`Density
`I/O Configuration
`
`x32
`
`4 Gb
`
`Table 3 — Addressing Scheme
`6 Gb
`8 Gb
`
`x16
`
`x32
`
`x16
`
`x32
`
`x16
`
`12 Gb
`x32
`x16
`
`16 Gb
`x32
`x16
`
`A0~A12 A0~A13 A0-A13 A0-A14 A0~A13 A0~A14 A0~A14 A0~A15 A0~A14 A0~A15
`
`A0~A5
`
`A0~A6
`
`A0~A5
`
`A0~A6
`
`A0~A5
`
`A0~A6
`
`A7,A9,A12~A15
`
`A7,A9,A12~A15
`
`A7,A9,A12~A15
`
`A0~A5
`
`A0~A6
`
`A0~A5
`
`A0~A6
`
`A7,A9,A12~A15
`
`A7,A9,A12~A15
`
`A7,A9,A12~A15,A6 A7,A9,A12~A15,A6 A7,A9,A12~A15,A6 A7,A9,A12~A15,A6 A7,A9,A12~A15,A6
`
`Des m arais LLP
`
`Row address
`Column
`address
`DQ[15:0]
`Column
`address
`DQ[31:16]
`Bank address
`
`QDR Mode
`
`DDR Mode
`
`QDR Mode
`
`DDR Mode
`
`Autoprecharge
`
`Page Size
`
`Refresh
`
`BA0~BA3
`
`BA0~BA3
`
`BA0~BA3
`
`A8
`
`A8
`
`A8
`
`4K
`
`2K
`
`4K
`
`2K
`
`4K
`
`2K
`
`16K/32ms
`
`16K/32ms
`
`16K/32ms
`
`BA0~BA3
`
`BA0~BA3
`
`A8
`
`A8
`
`4K
`
`2K
`
`4K
`
`2K
`
`16K/32ms
`
`1.9us
`
`16K/32ms
`
`1.9us
`
`Refresh period
`
`1.9us
`
`1.9us
`
`1.9us
`
`NOTE 1 The burst order is fixed for Reads and Writes, and the GDDR5X SGRAM does not assign column address bits to
`distinguish between the UIs of a burst. A memory controller may internally assign such column address bits but these
`column address bits are not transmitted on the colum address bus to the GDDR5X SGRAM.
`NOTE 2 Row address range with A[13:12] = 11 (x32 mode) or A[14:13] = 11 (x16 mode) is not present for 6 Gb density. Row
`address range with A[14:13] = 11 (x32 mode) or A[15:14] = 11 (x16 mode) is not present for 12 Gb density. ACT/RD/WR
`commands to these memory locations are illegal.
`NOTE 3 Two column addresses CAL and CAU with shared bank addresses are provided with each WRITE and READ
`command.
`