JEDEC
`STANDARD
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`DDR4 SDRAM
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`JESD79-4B
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`(Revision of JESD79-4A, November 2013)
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`JUNE 2017
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`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0001
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`NOTICE
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0002
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0003
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`

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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0004
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0004
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`

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`DDR4 SDRAM STANDARD
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`JEDEC Standard No. 79-4B
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`Contents
`Scope ............................................................................................................................................................................1
`1
`2 DDR4 SDRAM Package Pinout and Addressing ......................................................................................................2
`2.1 DDR4 SDRAM Row for X4, X8 and X16.......................................................................................................................2
`2.2 DDR4 SDRAM Ball Pitch ...............................................................................................................................................2
`2.3 DDR4 SDRAM Columns for X4,X8 and X16..................................................................................................................2
`2.4 DDR4 SDRAM X4/8 Ballout using MO-207 ................................................................................................................ 2
`2.5 DDR4 SDRAM X16 Ballout using MO-207 ....................................................................................................................3
`2.6 DDR4 SDRAM X32 Ballout using MO-XXX ...................................................................................................................4
`2.7 Pinout Description..........................................................................................................................................................6
`2.8 DDR4 SDRAM Addressing.............................................................................................................................................7
`2.9 DDP Single Rank(SR) x16 from two x8 .........................................................................................................................9
`3
`Functional Description .............................................................................................................................................11
`3.1 Simplified State Diagram .......................................................................................................................................... 11
`3.2 Basic Functionality .......................................................................................................................................................12
`3.3 RESET and Initialization Procedure.............................................................................................................................12
`3.3.1 Power-up Initialization Sequence ..............................................................................................................................12
`3.3.2 VDD Slew rate at Power-up Initialization Sequence .................................................................................................13
`3.3.3 Reset Initialization with Stable Power .......................................................................................................................14
`3.4 Register Definition........................................................................................................................................................14
`3.4.1 Programming the mode registers ..............................................................................................................................14
`3.5 Mode Register..............................................................................................................................................................17
`4 DDR4 SDRAM Command Description and Operation ...........................................................................................28
`4.1 Command Truth Table..................................................................................................................................................28
`4.2 CKE Truth Table ...........................................................................................................................................................29
`4.3 Burst Length, Type and Order......................................................................................................................................30
`4.3.1 BL8 Burst order with CRC Enabled ...........................................................................................................................30
`4.4 DLL-off Mode & DLL on/off Switching procedure ........................................................................................................31
`4.4.1 DLL on/off switching procedure .................................................................................................................................31
`4.4.2 DLL “on” to DLL “off” Procedure ................................................................................................................................31
`4.4.3 DLL “off” to DLL “on” Procedure ................................................................................................................................32
`4.5 DLL-off Mode ...............................................................................................................................................................33
`4.6 Input Clock Frequency Change ...................................................................................................................................34
`4.7 Write Leveling ..............................................................................................................................................................35
`4.7.1 DRAM setting for write leveling & DRAM termination function in that mode .............................................................36
`4.7.2 Procedure Description................................................................................................................................................36
`4.7.3 Write Leveling Mode Exit............................................................................................................................................37
`4.8 Temperature controlled Refresh modes.......................................................................................................................38
`4.8.1 Normal temperature mode ( 0°C =< TCASE =< 85°C ) ............................................................................................38
`4.8.2 Extended temperature mode ( 0°C =< TCASE =< 95°C ) .........................................................................................38
`4.9 Fine Granularity Refresh Mode....................................................................................................................................39
`4.9.1 Mode Register and Command Truth Table................................................................................................................39
`4.9.2 tREFI and tRFC parameters.......................................................................................................................................40
`4.9.3 Changing Refresh Rate..............................................................................................................................................40
`4.9.4 Usage with Temperature Controlled Refresh mode...................................................................................................41
`4.9.5 Self Refresh entry and exit.........................................................................................................................................41
`4.10 Multi Purpose Register................................................................................................................................................41
`4.10.1 DQ Training with MPR..............................................................................................................................................41
`4.10.2 MR3 definition .........................................................................................................................................................41
`4.10.3 MPR Reads .............................................................................................................................................................42
`4.10.4 MPR Writes .............................................................................................................................................................44
`4.10.5 MPR Read Data format ...........................................................................................................................................47
`4.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS................................................................................................52
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`-i-
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0005
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`

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`JEDEC Standard No. 79-4B
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`4.12 ZQ Calibration Commands ......................................................................................................................................... 54
`4.12.1 ZQ Calibration Description ...................................................................................................................................... 54
`4.13 DQ Vref Training ......................................................................................................................................................... 55
`4.13.1 Example scripts for VREFDQ Calibration Mode ..................................................................................................... 58
`4.14 Per DRAM Addressability ........................................................................................................................................... 61
`4.15 CAL Mode (CS_n to Command Address Latency) ..................................................................................................... 61
`4.15.1 CAL Mode Description ............................................................................................................................................ 63
`4.15.2 Self Refresh Entry, Exit Timing with CAL ................................................................................................................ 66
`4.15.3 Power Down Entry, Exit Timing with CAL ............................................................................................................... 66
`4.16 CRC............................................................................................................................................................................ 68
`4.16.1 CRC Polynomial and logic equation ....................................................................................................................... 68
`4.16.2 CRC data bit mapping for x8 devices ..................................................................................................................... 69
`4.16.3 CRC data bit mapping for x4 devices ..................................................................................................................... 69
`4.16.4 CRC data bit mapping for x16 devices ................................................................................................................... 69
`4.16.5 Write CRC for x4, x8 and x16 devices .................................................................................................................... 70
`4.16.6 CRC Error Handling ................................................................................................................................................ 70
`4.16.7 CRC Frame format with BC4 .................................................................................................................................. 71
`4.16.8 Simultaneous DM and CRC Functionality .............................................................................................................. 73
`4.16.9 Simultaneous MPR Write, Per DRAM Addressability and CRC Functionality ........................................................ 73
`4.17 Command Address Parity (CA Parity)......................................................................................................................... 74
`4.17.1 CA Parity Error Log Readout .................................................................................................................................. 80
`4.18 Control Gear-down Mode ........................................................................................................................................... 81
`4.19 DDR4 Key Core Timing .............................................................................................................................................. 83
`4.20 Programmable Preamble............................................................................................................................................ 86
`4.20.1 Write Preamble ....................................................................................................................................................... 86
`4.20.2 Read Preamble ....................................................................................................................................................... 88
`4.20.3 Read Preamble Training ......................................................................................................................................... 88
`4.21 Postamble................................................................................................................................................................... 89
`4.21.1 Read Postamble ..................................................................................................................................................... 89
`4.21.2 Write Postamble ..................................................................................................................................................... 89
`4.22 ACTIVATE Command ................................................................................................................................................. 89
`4.23 Precharge Command ................................................................................................................................................. 89
`4.24 Read Operation .......................................................................................................................................................... 90
`4.24.1 READ Timing Definitions ........................................................................................................................................ 90
`4.24.1.1 READ Timing; Clock to Data Strobe relationship ................................................................................................. 92
`4.24.1.2 READ Timing; Data Strobe to Data relationship ................................................................................................... 93
`4.24.1.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ........................................................................................... 94
`4.24.1.4 tRPRE Calculation ................................................................................................................................................ 96
`4.24.1.5 tRPST Calculation ................................................................................................................................................ 97
`4.24.2 READ Burst Operation ........................................................................................................................................... 98
`4.24.3 Burst Read Operation followed by a Precharge ................................................................................................... 109
`4.24.4 Burst Read Operation with Read DBI (Data Bus Inversion) ................................................................................. 111
`4.24.5 Burst Read Operation with Command/Address Parity .......................................................................................... 112
`4.24.6 Read to Write with Write CRC .............................................................................................................................. 113
`4.24.7 Read to Read with CS to CA Latency ....................................................................................................................114
`4.25 Write Operation..........................................................................................................................................................115
`4.25.1 Write Timing Parameters .......................................................................................................................................115
`4.25.2 Write Data Mask ....................................................................................................................................................116
`4.25.3 tWPRE Calculation ................................................................................................................................................117
`4.25.4 tWPST Calculation .................................................................................................................................................118
`4.25.5 Write Burst Operation ............................................................................................................................................119
`4.25.6 Read and Write Command Interval ...................................................................................................................... 134
`4.25.7 Write Timing Violations ......................................................................................................................................... 135
`4.25.7.1 Motivation .......................................................................................................................................................... 135
`4.25.7.2 Data Setup and Hold Offset Violations .............................................................................................................. 135
`4.25.7.3 Strobe and Strobe to Clock Timing Violations ................................................................................................... 135
`4.26 Refresh Command ................................................................................................................................................... 135
`4.27 Self refresh Operation .............................................................................................................................................. 137
`4.27.1 Low Power Auto Self Refresh ............................................................................................................................... 138
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`-ii-
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0006
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`

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`JEDEC Standard No. 79-4B
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`4.27.2 Self Refresh Exit with No Operation command .................................................................................................... 139
`4.28 Power down Mode................................................................................................................................................... 140
`4.28.1 Power-Down Entry and Exit .................................................................................................................................. 140
`4.28.2 Power-Down clarifications .................................................................................................................................... 144
`4.28.3 Power Down Entry and Exit timing during Command/Address Parity Mode is Enable.......................................... 145
`4.29 Maximum Power Saving Mode................................................................................................................................ 146
`4.29.1 Maximum power saving mode .............................................................................................................................. 146
`4.29.2 Mode entry ............................................................................................................................................................ 146
`4.29.3 CKE transition during the mode ............................................................................................................................ 147
`4.29.4 Mode exit .............................................................................................................................................................. 147
`4.29.5 Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200................. 148
`4.30 Connectivity Test Mode ........................................................................................................................................... 148
`4.30.1 Introduction ........................................................................................................................................................... 148
`4.30.2 Pin Mapping .......................................................................................................................................................... 148
`4.30.3 Logic Equations .................................................................................................................................................... 149
`4.30.3.1 Min Term Equations ........................................................................................................................................... 149
`4.30.3.2 Output equations for x16 devices ...................................................................................................................... 150
`4.30.3.3 Output equations for x8 devices ........................................................................................................................ 150
`40.30.3.4 Output equations for x4 devices ...................................................................................................................... 150
`4.30.4 Input level and Timing Requirement ..................................................................................................................... 151
`4.30.5 Connectivity Test ( CT ) Mode Input Levels .......................................................................................................... 152
`4.30.5.1 Input Levels for RESET_n .................................................................................................................................. 153
`4.30.5.2 Input Levels for ALERT_n ................................................................................................................................. 153
`4.31 CLK to Read DQS timing parameters ..................................................................................................................... 154
`4.32 Post Package Repair (hPPR).................................................................................................................................. 156
`4.32.1 Hard Fail Row Address Repair (WRA Case) ........................................................................................................ 156
`4.32.2 Hard Fail Row Address Repair (WR Case) ........................................................................................................... 157
`4.32.3 Hard Fail Row Address Repair MR bits and timing diagram ................................................................................. 157
`4.32.4 Programming hPPR & sPPR support in MPR0 page2 ........................................................................................ 158
`4.32.5 Required Timing Parameters ................................................................................................................................ 159
`4.33 Soft Post Package Repair (sPPR)........................................................................................................................... 159
`4.33.1 Soft Repair of a Fail Row Address ........................................................................................................................ 160
`5 On-Die Termination ................................................................................................................................................ 161
`5.1 ODT Mode Register and ODT State Table ................................................................................................................ 161
`5.2 Synchronous ODT Mode ........................................................................................................................................... 163
`5.2.1 ODT Latency and Posted ODT ............................................................................................................................... 164
`5.2.2 Timing Parameters ................................................................................................................................................. 164
`5.2.3 ODT during Reads................................................................................................................................................... 166
`5.3 Dynamic ODT............................................................................................................................................................ 167
`5.3.1 Functional Description ............................................................................................................................................ 167
`5.3.2 ODT Timing Diagrams ............................................................................................................................................ 168
`5.4 Asynchronous ODT mode ......................................................................................................................................... 169
`5.5 ODT buffer disabled mode for Power down .............................................................................................................. 170
`5.6 ODT Timing Definitions.............................................................................................................................................. 171
`5.6.1 Test Load for ODT Timings .................................................................................................................................... 171
`5.6.2 ODT Timing Definitions ........................................................................................................................................... 174
`6 Absolute Maximum Ratings .................................................................................................................................. 174
`7 AC and DC Operating Conditions ......................................................................................................................... 174
`8 AC and DC Input Measurement Levels ................................................................................................................. 174
`8.1 AC and DC Logic input levels for single-ended signals............................................................................................. 174
`8.2 AC and DC Input Measurement Levels: VREF Tolerances ....................................................................................... 175
`8.3 AC and DC Logic Input Levels for Differential Signals .............................................................................................. 176
`8.3.1 Differential signal definition ..................................................................................................................................... 176
`8.3.2 Differential swing requirements for clock (CK_t - CK_c) ......................................................................................... 176
`8.3.3 Single-ended requirements for differential signals .................................................................................................. 177
`8.3.4 Address, Command and Control Overshoot and Undershoot specifications .......................................................... 178
`8.3.5 Clock Overshoot and Undershoot Specifications ................................................................................................... 179
`8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications ........................................................................ 180
`8.4 Slew Rate Definitions ............................................................................................................................................... 181
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`Patent Owner Monterey Research, LLC
`Exhibit 2015, 0007
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`

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`JEDEC Standard No. 79-4B
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`8.4.1 Slew Rate Definitions for Differential Input Signals ( CK ) ...................................................................................... 181
`8.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ) ........................................................................ 182
`8.5 Differential Input Cross Point Voltage........................................................................................................................ 182
`8.6 CMOS rail to rail Input Levels.................................................................................................................................... 183
`8.6.1 CMOS rail to rail Input Levels for RESET_n ........................................................................................................... 183
`8.7 AC and DC Logic Input Levels for DQS Signals........................................................................................................ 184
`8.7.1 Differential signal definition ..................................................................................................................................... 184
`8.7.2 Differential swing requirements for DQS (DQS_t - DQS_c) .........................