JEDEC
`STANDARD
`
`Low Power Double Data Rate 4
`(LPDDR4)
`
`JESD209-4
`
`AUGUST 2014
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0001
`
`

`

`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the
`JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings
`between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the
`purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC
`members, whether the standard is to be used either domestically or internationally.
`
`JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents
`or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor
`does it assume any obligation whatever to parties adopting the JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to product specification
`and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization
`there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an
`ANSI standard.
`
`No claims to be in conformance with this standard may be made unless all requirements stated in the standard are
`met.
`
`Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be
`addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative
`contact information.
`Published by
`©JEDEC Solid State Technology Association 2014
`3103 North 10th Street
`Suite 240 South
`Arlington, VA 22201-2107
`
`This document may be downloaded free of charge; however JEDEC retains the
`copyright on this material. By downloading this file the individual agrees not to
`charge for or resell the resulting material.
`PRICE: Contact JEDEC
`
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0002
`
`

`

`PLEASE!
`
`DON'T VIOLATE
`THE
`LAW!
`
`This document is copyrighted by the JEDEC and may not be
`reproduced without permission.
`
`For information, contact:
`
`JEDEC Solid State Technology Association
`3103 North 10th Street, Suite 240 South
`Arlington, Virginia 22201-2107
`
`or refer to www.jedec.org under Standards-Documents/Copyright Information
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0003
`
`

`

`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0004
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0004
`
`

`

`LOW POWER DOUBLE DATA RATE 4 (LPDDR4)
`
`(From JEDEC Board Ballot JCB-14-41, formulated under the cognizance of the JC-42.6 Subcommittee on
`Low Power Memories.)
`
`JEDEC Standard No. 209-4
`Page 1
`
`1
`
`Scope
`
`This document defines the LPDDR4 standard, including features, functionalities, AC and DC
`characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the
`minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16x2channel SDRAM
`devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3
`(JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3).
`
`Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of
`these ballots was then incorporated to prepare the LPDDR4 standard.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0005
`
`

`

`Ch. B Top
`101
`VDD2
`102
`VSS
`103
`VDD1
`104
`VDD2
`105
`VSS
`106
`VSSQ
`107
`DQ8_B
`108
`VDDQ
`109
`DQ9_B
`110
`VSSQ
`111 DQ10_B
`112
`VDDQ
`113 DQ11_B
`114
`VSSQ
`115 DQS1_t_B
`116 DQS1_c_B
`117
`VDDQ
`118 DMI1_B
`119
`VSSQ
`120 DQ12_B
`121
`VDDQ
`122 DQ13_B
`123
`VSSQ
`124 DQ14_B
`125
`VDDQ
`126 DQ15_B
`127
`VSSQ
`128 RESET_n
`129
`VDDQ
`130
`VDD2
`131
`VDD1
`132
`VSS
`133
`CA5_B
`134
`CA4_B
`135
`VDD2
`136
`CA3_B
`137
`CA2_B
`138
`VSS
`139 CK_c_B
`140 CK_t_B
`
`VDD2
`141
`CKE_B
`142
`CS_B
`143
`VSS
`144
`CA1_B
`145
`CA0_B
`146
`VDD2
`147
`148 ODT(ca)_B
`149
`VSS
`150
`VDD1
`151
`VSSQ
`152
`DQ7_B
`153
`VDDQ
`154
`DQ6_B
`155
`VSSQ
`156
`DQ5_B
`157
`VDDQ
`158
`DQ4_B
`159
`VSSQ
`160 DMI0_B
`161
`VDDQ
`162 DQS0_c_B
`163 DQS0_t_B
`164
`VSSQ
`165
`DQ3_B
`166
`VDDQ
`167
`DQ2_B
`168
`VSSQ
`169
`DQ1_B
`170
`VDDQ
`171
`DQ0_B
`172
`VSSQ
`173
`VSS
`174
`VDD2
`175
`VDD1
`176
`VSS
`177
`VDD2
`Ch. B Bottom
`
`Top
`
`Channel B
`
`Channel A
`
`BoƩom
`
`JEDEC Standard No. 209-4
`Page 2
`
`Package Ballout & Pin Definition
`
`1 2
`
`2.1
`
`Pad Order
`Ch. A Top
`1
`VDD2
`2
`VSS
`3
`VDD1
`4
`VDD2
`5
`VSS
`6
`VSSQ
`DQ8_A
`7
`8
`VDDQ
`DQ9_A
`9
`10
`VSSQ
`DQ10_A
`11
`12
`VDDQ
`DQ11_A
`13
`14
`VSSQ
`15 DQS1_t_A
`16 DQS1_c_A
`17
`VDDQ
`18
`DMI1_A
`19
`VSSQ
`20
`DQ12_A
`21
`VDDQ
`22
`DQ13_A
`23
`VSSQ
`24
`DQ14_A
`25
`VDDQ
`26
`DQ15_A
`27
`VSSQ
`28
`ZQ
`29
`VDDQ
`30
`VDD2
`31
`VDD1
`32
`VSS
`33
`CA5_A
`34
`CA4_A
`35
`VDD2
`36
`CA3_A
`37
`CA2_A
`38
`VSS
`39
`CK_c_A
`40
`CK_t_A
`
`VDD2
`41
`CKE_A
`42
`CS_A
`43
`VSS
`44
`CA1_A
`45
`CA0_A
`46
`47
`VDD2
`48 ODT(ca)_A
`49
`VSS
`50
`VDD1
`51
`VSSQ
`52
`DQ7_A
`53
`VDDQ
`54
`DQ6_A
`55
`VSSQ
`56
`DQ5_A
`57
`VDDQ
`58
`DQ4_A
`59
`VSSQ
`60
`DMI0_A
`61
`VDDQ
`62 DQS0_c_A
`63 DQS0_t_A
`64
`VSSQ
`65
`DQ3_A
`66
`VDDQ
`67
`DQ2_A
`68
`VSSQ
`69
`DQ1_A
`70
`VDDQ
`71
`DQ0_A
`72
`VSSQ
`73
`VSS
`74
`VDD2
`75
`VDD1
`76
`VSS
`77
`VDD2
`Ch. A Bottom
`
`NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level
`requires review of MR and calibration features assigned to specific data bits/bytes.
`NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the
`extra pads are grouped with like-named pads.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0006
`
`

`

`JEDEC Standard No. 209-4
`Page 3
`
`2.2
`
`Package Ballout
`
`2.2.1
`
`272-ball 15mm x 15mm 0.4mm pitch, Quad-Channel POP FBGA (top view)
`
`Using Variation VFFCDB for MO-273
`
`NOTE 1 15mm x 15mm, 0.4mm ball pitch
`NOTE 2 272 ball count, 36 rows
`NOTE 3 Top View, A1 in top left corner
`NOTE 4 ODT ca_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if
`present) are disabled in the package.
`NOTE 5 Package Channel a and Channel c shall be assigned to die Channel A of different DRAM die.
`NOTE 6 Die pad VSS and VSSQ signals are combined to VSS package balls.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0007
`
`

`

`JEDEC Standard No. 209-4
`Page 4
`
`2.2.2
`
`A
`
`B
`
`C
`
`D
`
`200-ball x32 Discrete Package, 0.80mm x 0.65mm using MO-311
`0.80mm Pitch
`6
`7
`
`1
`
`2
`
`3
`
`4
`
`5
`
`8
`
`9
`
`DNU
`
`DNU
`
`VSS
`
`VDD2
`
`ZQ0
`
`ZQ1
`
`VDD2
`
`DNU
`
`DQ0_A
`
`VDDQ
`
`DQ7_A
`
`VDDQ
`
`VDDQ
`
`DQ15_A
`
`VDDQ
`
`DQ8_A
`
`DNU
`
`VSS
`
`DQ1_A
`
`DMI0_A
`
`DQ6_A
`
`VSS
`
`VSS
`
`DQ14_A
`
`DMI1_A
`
`DQ9_A
`
`VSS
`
`VDDQ
`
`VSS
`
`DQS0_T_A
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DQS1_T_A
`
`VSS
`
`VDDQ
`
`10
`
`VSS
`
`11
`
`12
`
`DNU
`
`DNU
`
`E
`
`F
`
`G
`
`H
`
`J
`
`VSS
`
`DQ2_A DQS0_C_
`A
`
`DQ5_A
`
`VSS
`
`VSS
`
`DQ13_A DQS1_C_
`A
`
`DQ10_A
`
`VSS
`
`VDD1
`
`DQ3_A
`
`VDDQ
`
`DQ4_A
`
`VDD2
`
`VDD2
`
`DQ12_A
`
`VDDQ
`
`DQ11_A
`
`VDD1
`
`VSS
`
`ODT_CA_
`A
`
`VSS
`
`VDD1
`
`VSS
`
`VSS
`
`VDD1
`
`VSS
`
`ZQ2
`
`VSS
`
`VDD2
`
`CA0_A
`
`CS1_A
`
`CS0_A
`
`VDD2
`
`VDD2
`
`CA2_A
`
`CA3_A
`
`CA4_A
`
`VDD2
`
`VSS
`
`CA1_A
`
`VSS
`
`CKE0_A CKE1_A
`
`CK_t_A
`
`CK_c_A
`
`VSS
`
`CA5_A
`
`VSS
`
`CKE2_A
`
`VSS
`
`VDD2
`
`VSS
`
`VDD2
`
`VDD2
`
`VSS
`
`VDD2
`
`VSS
`
`CS2_A
`
`VDD2
`
`VSS
`
`VDD2
`
`VSS
`
`CS2_B
`
`CKE2_B
`
`VSS
`
`VDD2
`
`VSS
`
`VDD2
`
`VSS
`
`CA1_B
`
`VSS
`
`CKE0_B CKE1_B
`
`CK_T_B CK_C_B
`
`VSS
`
`CA5_B
`
`VSS
`
`VDD2
`
`CA0_B
`
`CS1_B
`
`CS0_B
`
`VDD2
`
`VDD2
`
`CA2_B
`
`CA3_B
`
`CA4_B
`
`VDD2
`
`VSS
`
`ODT_CA_
`B
`
`VSS
`
`VDD1
`
`VSS
`
`VSS
`
`VDD1
`
`VSS
`
`RESET_N
`
`VSS
`
`DQ4_B
`
`VDD2
`
`VDD2
`
`DQ12_B
`
`VDDQ
`
`DQ11_B
`
`VDD1
`
`K
`
`L M N
`
`P
`
`R
`
`T
`
`U
`
`0.65mm Pitch
`
`VDD1
`
`DQ3_B
`
`VDDQ
`
`V
`
`VSS
`
`DQ2_B DQS0_C_
`B
`
`DQ5_B
`
`VSS
`
`VSS
`
`DQ13_B DQS1_C_
`B
`
`DQ10_B
`
`VSS
`
`W VDDQ
`
`VSS
`
`DQS0_T_B
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DQS1_T_B
`
`VSS
`
`VDDQ
`
`Y
`
`VSS
`
`DQ1_B
`
`DMI0_B
`
`DQ6_B
`
`VSS
`
`VSS
`
`DQ14_B
`
`DMI1_B
`
`DQ9_B
`
`VSS
`
`AA
`
`DNU
`
`DQ0_B
`
`VDDQ
`
`DQ7_B
`
`VDDQ
`
`VDDQ
`
`DQ15_B
`
`VDDQ
`
`DQ8_B
`
`DNU
`
`AB
`
`DNU
`
`DNU
`
`VSS
`
`VDD2
`
`VSS
`
`VSS
`
`VDD2
`
`VSS
`
`DNU
`
`DNU
`
`NOTE 1 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows.
`NOTE 2 Top View, A1 in top left corner.
`NOTE 3 ODT_CA_[x] balls are wired to ODT_CA)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks
`(if present) are disabled in the package.
`NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and
`2-rank package those balls are NC.
`NOTE 5 Die pad VSS and VSSQ signals are combined to VSS package balls.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0008
`
`

`

`2.2.3
`
`432-ball x64 HDI Discrete Package, 0.50mm x 0.50mm (MO: TBD)
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD2
`
`VDD2
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD2
`
`VDD2
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`CA4_C
`
`VSS
`
`DQ8_C
`
`VDD1
`
`VDDQ
`
`A
`
`B
`
`A
`
`B
`
`VDDQ
`
`VDD1
`
`DQ0_A
`
`VSS
`
`CA0_A
`
`VDD2
`
`VDD2
`
`CA4_A
`
`VSS
`
`DQ8_A
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`DQ0_C
`
`VSS
`
`CA0_C
`
`VDD2
`
`VDD2
`
`VDDQ DQ1_A
`
`VSS
`
`DQ5_A
`
`VSS
`
`CA2_A
`
`CA3_A
`
`VSS
`
`DQ13_A
`
`VSS
`
`DQ9_A
`
`VDDQ
`
`VDDQ DQ1_C
`
`VSS
`
`DQ5_C
`
`VSS
`
`CA2_C
`
`CA3_C
`
`VSS
`
`DQ13_C
`
`VSS
`
`DQ9_C
`
`VDDQ
`
`VSS
`
`DQ12_A
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DQ4_C
`
`VSS
`
`CA1_C
`
`VDD2
`
`VDD2
`
`CA5_C
`
`VSS
`
`DQ12_C
`
`VSS
`
`VDDQ
`
`C
`
`D
`
`C
`
`D
`
`VDDQ
`
`VSS
`
`DQ4_A
`
`VSS
`
`CA1_A
`
`VDD2
`
`VDD2
`
`CA5_A
`
`E
`
`F
`
`G
`
`VDDQ DQ2_A
`
`VSS
`
`DQ6_A
`
`VSS
`
`CLK_t_A
`
`CLK_c_A
`
`VSS
`
`DQ14_A
`
`VSS
`
`DQ10_A VDDQ
`
`VDDQ DQ2_C
`
`VSS
`
`DQ6_C
`
`VSS
`
`CLK_t_C
`
`CLK_c_C
`
`VSS
`
`DQ14_C
`
`VSS
`
`DQ10_C VDDQ
`
`VDDQ
`
`VSS
`
`VSS
`
`CS1_A
`
`VDD2
`
`VDD2 CKE0_A
`
`VSS
`
`DQS1_t_
`A
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`VSS
`
`CS1_C
`
`VDD2
`
`VDD2 CKE0_C
`
`VSS
`
`DQS1_t_
`C
`
`VSS
`
`VDDQ
`
`DQ11_A VDDQ
`
`VDDQ DQ3_C
`
`VSS
`
`CS0_C
`
`CKE1_C
`
`VSS
`
`DQ11_C VDDQ
`
`E
`
`F
`
`G
`
`DQS0_t_
`A
`VSS DQS0_c_
`A
`
`VDDQ DQ3_A
`
`VSS
`
`CS0_A
`
`CKE1_A
`
`VSS DQS1_c_
`A
`
`VSS
`
`DQS0_t_
`C
`VSS DQS0_c_
`C
`
`VSS DQS1_c_
`C
`
`VDDQ
`
`VSS
`
`DMI0_A
`
`VSS
`
`DQ7_A
`
`VDD2
`
`VDD2 DQ15_A
`
`VSS
`
`DMI1_A
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DMI0_C
`
`VSS
`
`DQ7_C
`
`VDD2
`
`VDD2 DQ15_C
`
`VSS
`
`DMI1_C
`
`VSS
`
`VDDQ
`
`VDDQ
`
`ZQ3_A
`
`ZQ2_A
`
`ODT
`ca_A
`
`CS3_A CS2_A
`
`CKE3_A CKE2_A ZQ0_A
`
`VSS
`
`ZQ1_A
`
`VDDQ
`
`VDDQ ZQ3_C ZQ2_C
`
`ODT
`ca_C
`
`CS3_C CS2_C
`
`CKE3_C CKE2_C ZQ0_C
`
`VSS
`
`ZQ1_C
`
`VDDQ
`
`H
`
`J
`
`K
`
`L
`
`M
`
`N
`
`P
`
`H
`
`J
`
`K
`
`L
`
`M
`
`N
`
`P
`
`NOTE 1 0.5 mm ball pitch. MO-TBD
`NOTE 2 432 ball count
` Top view, A1 in top left corner
`NOTE 3
` ODT ca_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package
`NOTE 4
` Package Channel A and Channel C shall be assigned to die Channel A of different DRAM die
`NOTE 5
` ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. ZQ3, CKE3_A,
`NOTE 6
`CKE3_B, CS3_A, and CS3_B balls are reserved for 4-rank package. For 1-rank and 2-rank package those balls are NC
`NOTE 7
` Die pad VSS and VSSQ signals are combined to VSS package balls
`
`VDDQ
`
`VSS
`
`VSS
`
`ODT
`ca_B
`
`CS3_B CS2_B
`
`CKE3_B CKE2_B
`
`VSS
`
`VSS RESET_n VDDQ
`
`VDDQ
`
`VSS
`
`VSS
`
`ODT
`ca_D
`
`CS3_D CS2_D
`
`CKE3_D CKE2_D
`
`VSS
`
`VSS
`
`NC
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DMI0_B
`
`VSS
`
`DQ7_B
`
`VDD2
`
`VDD2 DQ15_B
`
`VSS
`
`DMI1_B
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DMI0_D
`
`VSS
`
`DQ7_D
`
`VDD2
`
`VDD2 DQ15_D
`
`VSS
`
`DMI1_D
`
`VSS
`
`VDDQ
`
`CS0_B
`
`CKE1_B
`
`VSS
`
`DQ11_B VDDQ
`
`VDDQ DQ3_D
`
`VSS
`
`CS0_D
`
`CKE1_D
`
`VSS
`
`DQ11_D VDDQ
`
`R
`
`T
`
`V
`
`W
`
`Y
`
`R
`
`T
`
`V
`
`W
`
`Y
`
`VDDQ DQ3_B
`
`VSS DQS0_c_
`B
`
`VSS
`
`VSS DQS1_c_
`B
`
`VSS DQS0_c_
`D
`
`VSS DQS1_c_
`D
`
`AA
`
`VDDQ
`
`VSS
`
`DQS0_t_
`B
`
`VSS
`
`CS1_B
`
`VDD2
`
`VDD2 CKE0_B
`
`VSS
`
`DQS1_t_
`B
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DQS0_t_
`D
`
`VSS
`
`CS1_D
`
`VDD2
`
`VDD2 CKE0_D
`
`VSS
`
`DQS1_t_
`D
`
`VSS
`
`VDDQ
`
`AA
`
`AB
`
`AC
`
`VDDQ DQ2_B
`
`VSS
`
`DQ6_B
`
`VSS
`
`CLK_t_B
`
`CLK_c_B
`
`VSS
`
`DQ14_B
`
`VSS
`
`DQ10_B VDDQ
`
`VDDQ DQ2_D
`
`VSS
`
`DQ6_D
`
`VSS
`
`CLK_t_D
`
`CLK_c_D
`
`VSS
`
`DQ14_D
`
`VSS
`
`DQ10_D VDDQ
`
`AB
`
`VDD2
`
`VDD2
`
`CA5_D
`
`VSS
`
`DQ12_D
`
`VSS
`
`VDDQ
`
`AC
`
`JEDEC Standard No.209-4
`Page 5
`
`
`
`VDDQ
`
`VDD1
`
`DQ0_B
`
`VSS
`
`CA0_B
`
`VDD2
`
`AF
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD2
`
`VDD2
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD2
`
`VDD2
`
`VDDQ
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`VDDQ
`
`AF
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`VDDQ
`
`VSS
`
`DQ4_B
`
`VSS
`
`CA1_B
`
`VDD2
`
`VDD2
`
`CA5_B
`
`VSS
`
`DQ12_B
`
`VSS
`
`VDDQ
`
`VDDQ
`
`VSS
`
`DQ4_D
`
`VSS
`
`CA1_D
`
`AD
`
`AE
`
`VDDQ DQ1_B
`
`VSS
`
`DQ5_B
`
`VSS
`
`CA2_B
`
`CA3_B
`
`VSS
`
`DQ13_B
`
`VSS
`
`DQ9_B
`
`VDDQ
`
`VDDQ DQ1_D
`
`VSS
`
`DQ5_D
`
`VSS
`
`CA2_D
`
`CA3_D
`
`VSS
`
`DQ13_D
`
`VSS
`
`DQ9_D
`
`VDDQ
`
`VDD2
`
`CA4_B
`
`VSS
`
`DQ8_B
`
`VDD1
`
`VDDQ
`
`VDDQ
`
`VDD1
`
`DQ0_D
`
`VSS
`
`CA0_D
`
`VDD2
`
`VDD2
`
`CA4_D
`
`VSS
`
`DQ8_D
`
`VDD1
`
`VDDQ
`
`AD
`
`AE
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0009
`
`

`

`JEDEC Standard No. 209-4
`Page 6
`
`2.3
`
`Pad Definition and Description
`
`Symbol
`CK_t_A,
`CK_c_A,
`CK_t_B,
`CK_c_B
`
`CKE_A
`CKE_B
`
`CS_A
`CS_B
`
`CA[5:0]_A
`CA[5:0]_B
`
`ODT_CA_A
`ODT_CA_B
`DQ[15:0]_A,
`DQ[15:0]_B
`
`DQS[1:0]_t_A,
`DQS[1:0]_c_A,
`DQS[1:0]_t_B,
`DQS[1:0]_c_B
`
`DMI[1:0]_A,
`DMI[1:0]_B
`
`Type
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`I/O
`
`I/O
`
`I/O
`
`ZQ
`
`Reference
`
`Table 1 — Pad Definition and Description
`Description
`Clock: CK_t and CK_c are differential clock inputs. All address, command,
`and control input signals are sampled on the crossing of the positive edge of
`CK_t and the negative edge of CK_c. AC timings for CA parameters are
`referenced to CK. Each channel (A & B) has its own clock pair.
`
`Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal
`clock circuits, input buffers, and output drivers. Power-saving modes are
`entered and exited via CKE transitions. CKE is part of the command code.
`Each channel (A & B) has its own CKE signal.
`
`Chip Select: CS is part of the command code. Each channel (A & B) has its
`own CS signal.
`Command/Address Inputs: CA signals provide the Command and Address
`inputs according to Table 63 — Command Truth Table. Each channel (A&B)
`has its own CA signals.
`CA ODT Control: The ODT_CA pin is used in conjunction with the Mode
`Register to turn on/off the On-Die-Termination for CA pins.
`
`Data Input/Output: Bi-direction data bus.
`
`Data Strobe: DQS_t and DQS_c are bi-directional differential output clock
`signals used to strobe data during a READ or WRITE. The Data Strobe is
`generated by the DRAM for a READ and is edge-aligned with Data. The Data
`Strobe is generated by the Memory Controller for a WRITE and must arrive
`prior to Data. Each byte of data has a Data Strobe signal pair. Each channel
`(A & B) has its own DQS strobes.
`
`Data Mask Inversion: DMI is a bi-directional signal which is driven HIGH
`when the data on the data bus is inverted, or driven LOW when the data is in
`its normal state. Data Inversion can be disabled via a mode register setting.
`Each byte of data has a DMI signal. Each channel (A & B) has its own DMI
`signals.
`Calibration Reference: Used to calibrate the output drive strength and the
`termination resistance. There is one ZQ pin per die. The ZQ pin shall be
`connected to VDDQ through a 240Ω ± 1% resistor.
`
`VDDQ,
`VDD1,
`VDD2
`VSS, VSSQ
`
`RESET_n
`
`Supply
`
`Power Supplies: Isolated on the die for improved noise immunity.
`
`GND
`
`Input
`
`Ground Reference: Power supply ground reference
`RESET: When asserted LOW, the RESET_n signal resets both channels of
`the die.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0010
`
`

`

`JEDEC Standard No. 209-4
`Page 7
`
`3
`
`Functional Description
`
`LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured as 2-channel and 8-
`bank per channel memory that is up to 16Gb density. The configuration for the device density that is
`greater than 16Gb is still TBD1.
`
`These devices contain the following number of bits:
`
` 4Gb has 4,294,967,296 bits
` 6Gb has 6,442,450,944 bits
` 8Gb has 8,589,934,592 bits
`12Gb has 12,884,901,888 bits
`16Gb has 17,179,869,184 bits
`24Gb has 25,769,803,776 bits
`32Gb has 34,359,738,368 bits
`
`LPDDR4 devices use a 2 or 4 clocks architecture on the Command/Address (CA) bus to reduce the
`number of input pins in the system. The 6-bit CA bus contains command, address, and bank information.
`
`Each command uses 1, 2 or 4 clock cycle, during which command information is transferred on the positive
`edge of the clock. See Table 63 — Command Truth Table, for details.
`
`These devices use a double data rate architecture on the DQ pins to achieve high speed operation. The
`double data rate architecture is essentially an 16n prefetch architecture with an interface designed to
`transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the
`LPDDR4 SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal
`DRAM core and eight corresponding n-bit wide, one half-clock-cycle data transfers at the I/O pins. Read
`and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location and
`continue for a programmed number of locations in a programmed sequence. Accesses begin with the
`registration of an Activate command, which is then followed by a Read, Write or Mask Write command.
`
`The address and BA bits registered coincident with the Activate command are used to select the row and
`the bank to be accessed. The address bits registered coincident with the Read, Write or Mask Write
`command are used to select the bank and the starting column location for the burst access.
`
`Prior to normal operation, the LPDDR4 SDRAM must be initialized. The following provides detailed
`information covering device initialization, register definition, command description and device operation.
`
`1. As of publication of this document, under discussion by the formulating committee.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0011
`
`

`

`JEDEC Standard No. 209-4
`Page 8
`
`3.1
`
`LPDDR4 SDRAM Addressing
`Table 2 — LPDDR4 SDRAM Addressing
`
`Memory
`Density
`(per Die)
`Memory
`Density
`(per channel)
`
`Configuration
`
`Number of
`Channels
`(per die)
`
`Number of
`Banks
`(per channel)
`
`Array
`Pre-Fetch
`(bits,
`per channel)
`
`4Gb
`
`2Gb
`
`6Gb
`
`3Gb
`
`8Gb
`
`4Gb
`
`12Gb
`
`16Gb
`
`24Gb
`
`32Gb
`
`6Gb
`
`8Gb
`
`12Gb
`
`16Gb
`
`16Mb x 16DQ
`x 8 banks
`x 2 channels
`
`24Mb x 16DQ
`x 8 banks
`x 2 channels
`
`32Mb x 16DQ
`x 8 banks
`x 2 channels
`
`48Mb x 16DQ
`x 8 banks
`x 2 channels
`
`64Mb x 16DQ
`x 8 banks
`x 2 channels
`
`TBD x 16DQ
`x TBD banks
`x 2 channels
`
`TBD x 16DQ
`x TBD banks
`x 2 channels
`
`2
`
`8
`
`2
`
`8
`
`2
`
`8
`
`2
`
`8
`
`2
`
`8
`
`2
`
`2
`
`TBD
`
`TBD
`
`256
`
`256
`
`256
`
`256
`
`256
`
`256
`
`256
`
`24,576
`
`32,768
`
`49,152
`
`65,536
`
`TBD
`
`TBD
`
`Number of
`Rows
`(per channel)
`
`Number of
`Columns
`(fetch
`boundaries)
`
`Page Size
`(Bytes)
`
`Channel
`Density
`(Bits per
`channel)
`
`Total Density
`(Bits per die)
`
`16,384
`
`64
`
`64
`
`64
`
`64
`
`64
`
`TBD
`
`TBD
`
`2048
`
`2048
`
`2048
`
`2048
`
`2048
`
`TBD
`
`TBD
`
`2,147,483,648 3,221,225,472 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184
`
`4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184 25,769,803,776 34,359,738,368
`
`Bank Address
`
`BA0 - BA2
`
`BA0 - BA2
`
`BA0 - BA2
`
`BA0 - BA2
`
`BA0 - BA2
`
`x16
`
`Row
`Addresses
`
`Column
`Addresses
`
`R0 - R13
`
`R0 - R14
`(R13=0 when
`R14=1)
`
`R0 - R14
`
`R0 - R15
`(R14=0 when
`R15=1)
`
`R0 - R15
`
`C0 - C9
`
`C0 - C9
`
`C0 - C9
`
`C0 - C9
`
`C0 - C9
`
`TBD
`
`TBD
`
`TBD
`
`TBD
`
`TBD
`
`TBD
`
`64 - bit
`
`64 - bit
`
`Burst Starting
`Address
`Boundary
`NOTE 1 The lower two column addresses (C0 - C1) are assumed to be “zero” and are not transmitted on the CA bus.
`NOTE 2 Row and Column address values on the CA bus that are not used for a particular density be at valid logic levels.
`NOTE 3 For non - binary memory densities,only half of the row address space is valid. When the MSB address bit is “HIGH”, then
`the MSB - 1 address bit must be “LOW”.
`NOTE 4 TBD, as of publication of this document, under discussion by the formulating committee.
`
`64 - bit
`
`64 - bit
`
`64 - bit
`
`64 - Bit
`
`64 - bit
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0012
`
`

`

`JEDEC Standard No. 209-4
`Page 9
`
`3.2
`
`Simplified LPDDR4 State Diagram
`
`LPDDR4-SDRAM state diagram provides a simplified illustration of allowed state transitions and the
`related commands to control them. For a complete definition of the device behavior, the information
`provided by the state diagram should be integrated with the truth tables and timing specification.
`
`The truth tables provide complementary information to the state diagram, they clarify the device behavior
`and the applied restrictions when considering the actual state of all the banks.
`
`For the command definition, see clause 4, Command Definition and Timing Diagram.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0013
`
`

`

`JEDEC Standard No. 209-4
`Page 10
`
`Command Sequence
`Automatic Sequence
`
`MRW
`
`REF
`
`Per
`Bank
`Refresh
`
`R eset_ n
`= L
`
`Power
`On
`
`MPC
`Based
`Training
`
`Reset
`
`MRW
`
`MPC
`
`R eset_n
`= H
`
`SR
`Power
`Down
`
`C K E = L
`
`MRW
`
`Command
`Bus
`Training
`
`C K E = H
`
`MRW
`
`Idle
`
`REF
`
`All
`Bank
`Refresh
`
`MPC
`
`MPC
`Based
`Training
`
`MRW
`
`MRW
`
`Command
`Bus
`Training
`
`MRR
`
`MRR
`
`MRW
`
`MRR
`
`REF
`
`RD
`
`Read
`
`RDA
`
`MRR
`
`Per
`Bank
`Refresh
`
`MPC
`Based
`Training
`
`Self
`Refresh
`
`MPC
`
`MRR
`
`MRW
`
`MRR
`
`MRW
`
`SRE
`
`SRX
`
`PDX
`
`PDE
`
`Idle
`Power
`Down
`
`ACT
`
`MRR
`
`Activating
`
`MPC
`Based
`Training
`
`Active
`Power
`Down
`
`PDE
`
`PDX
`
`MRW
`
`Bank
`Active
`
`WR or
`MWR
`
`RD
`
`WR or
`MWR
`
`Write
`or
`MWR
`
`WRA or
`MWRA
`
`WRA or
`MWRA
`
`RDA
`
`Write or
`MWR
`with Auto-
`Precharge
`
`PRE or
`PREA
`
`PRE or
`PREA
`
`Read
`with Auto-
`Precharge
`
`PRE(A) = Precharge (All)
`ACT = Activate
`WR(A) = Write (with Autoprecharge)
`MWR(A) = Mask-Write (with Autoprecharge)
`RD(A) = Read (with Autoprecharge)
`MRW = Mode Register Write
`MRR = Mode Register Read
`PDE = Enter Power Down
`PDX = Exit Power Down
`SRE = Enter Self Refresh
`SRX = Exit Self Refresh
`REF = Refresh
`MPC = Multi-Purpose Command (w/NOP)
`Figure 1 — LPDDR4: Simplified Bus Interface State Diagram-1
`
`PRE or
`PREA
`
`Pre-
`charging
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0014
`
`

`

`JEDEC Standard No. 209-4
`Page 11
`
`A) FIFO Based Write / Read Timing
`
`MPC
`
`MPC
`
`MPC
`
`FIFO
`WRTR
`
`MRW
`
`MPC
`
`FIFO
`RDTR
`
`MRW
`WRTR
`
`MPC
`
`MRW
`
`MPC
`
`MPC
`Based
`Training
`
`B) Read DQ Calibration
`
`MPC
`
`DQ
`Calibration
`
`MPC
`
`C) ZQ CAL Start
`
`MPC
`
`ZQ
`Calibration
`Start
`
`D) ZQ CAL Latch
`
`MPC
`
`ZQ
`Calibration
`Latch
`
`NOTE 1 From the Self-Refresh state the device can enter Power-Down, MRR, MRW, or MPC states. See 4.13, on
`Self-Refresh for more information.
`NOTE 2 In IDLE state, all banks are pre-charged.
`NOTE 3 In the case of a MRW command to enter a training mode, the state machine will not automatically return to
`the IDLE state at the conclusion of training. See 4.17, on Mode Register Write (MRW) for more information.
`NOTE 4 In the case of a MPC command to enter a training mode, the state machine may not automatically return to
`the IDLE state at the conclusion of training. See 4.28, Multi-Purpose Command (MPC) for more information.
`NOTE 5 This simplified State Diagram is intended to provide an overview of the possible state transitions and the
`commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
`termination, and some other events are not captured in full detail.
`NOTE 6 States that have an “automatic return” and can be accessed from more than one prior state (Ex. MRW from
`either Idle or Active states) will return to the state from when they were initiated (Ex. MRW from Idle will return to Idle).
`NOTE 7 The RESET_n pin can be asserted from any state, and will cause the SDRAM to go to the Reset State. The
`diagram shows RESET applied from the Power-On as an example, but the Diagram should not be construed as a
`restriction on RESET_n.
`
`Figure 2 — LPDDR4: Simplified Bus Interface State Diagram-2
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0015
`
`

`

`JEDEC Standard No. 209-4
`Page 12
`
`3.3
`
`Power-up, Initialization and Power-off Procedure
`
`For power-up and reset initialization, in order to prevent DRAM from functioning improperly, default values
`of the following MR settings are defined as Table 3.
`
`Item
`
`MRS
`
`Description
`
`Table 3 — MRS defaults settings
`Default
`Setting
`00B
`0B
`000B
`000B
`000B
`00B
`000B
`000B
`1B
`001101B
`1B
`001101B
`
`FSP-OP/WR
`WLS
`WL
`RL
`nWR
`DBI-WR/RD
`CA ODT
`DQ ODT
`VREF(CA) Setting
`VREF(CA) Value
`VREF(DQ) Setting
`VREF(DQ) Value
`
`MR13 OP[7:6]
`MR2 OP[6]
`MR2 OP[5:3]
`MR2 OP[2:0]
`MR1 OP[6:4]
`MR3 OP[7:6]
`MR11 OP[6:4]
`MR11 OP[2:0]
`MR12 OP[6]
`MR12 OP[5:0]
`MR14 OP[6]
`MR14 OP[5:0]
`
`FSP-OP/WR[0] are enabled
`Write Latency Set 0 is selected
`WL = 4
`RL = 6, nRTP=8
`nWR = 6
`Write & Read DBI are disabled
`CA ODT is disabled
`DQ ODT is disabled
`VREF(CA) Range[1] enabled
`Range1 : 27.2% of VDD2
`VREF(DQ) Range[1] enabled
`Range1 : 27.2% of VDDQ
`
`3.3.1
`
`Voltage Ramp and Device Initialization
`
`The following sequence shall be used to power up the LPDDR4 device. Unless specified otherwise, these
`steps are mandatory. Note that the power-up sequence of all channels must proceed simultaneously.
`
`1. While applying power (after Ta), RESET_n is recommended to be LOW (≤0.2 x VDD2) and all other
`inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while RESET_n is
`held LOW. Power supply voltage ramp requirements are provided in Table 4. VDD1 must ramp at the
`same time or earlier than VDD2. VDD2 must ramp at the same time or earlier than VDDQ.
`
`After
`
`Ta is reached
`
`Table 4 — Voltage Ramp Conditions
`Applicable Conditions
`VDD1 must be greater than VDD2
`VDD2 must be greater than VDDQ - 200mV
`
`NOTE 1 Ta is the point when any power supply first reaches 300mV.
`NOTE 2 Voltage ramp conditions in Table 4 apply between Ta and power-off (controlled or uncontrolled).
`NOTE 3 Tb is the point at which all supply and reference voltages are within their defined ranges.
`NOTE 4 Power ramp duration tINIT0 (Tb-Ta) must not exceed 20ms.
`NOTE 5 The voltage difference between any of Vss and Vssq pins must not excess 100mV.
`
`2. Following the completion of the voltage ramp (Tb), RESET_n must be maintained LOW. DQ, DMI,
`DQS_t and DQS_c voltage levels must be between Vssq and Vddq during voltage ramp to avoid
`latch-up. CKE, CK_t, CK_c, CS_n and CA input levels must be between Vss and VDD2 during voltage
`ramp to avoid latch-up.
`
`3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be
`de-asserted to HIGH(Tc). At least 10ns before RESET_n de-assertion, CKE is required to be set LOW.
`All other input signals are "Don't Care".
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0016
`
`

`

`JEDEC Standard No. 209-4
`Page 13
`
`Ta
`
`Power Ramp
`
`Tb
`
`Reset
`
`Tc
`
`Initialization
`
`Td
`
`Te
`
`Tf
`
`Tg
`
`Th
`Training
`
`Ti
`
`Tj
`
`Tk
`
`tINIT4=5tCK(min)
`
`tINIT0=20ms(max)
`
`tINIT1=200us(min)
`
`tINIT2=10ns(min)
`
`tINIT3=2ms(min)
`
`tINIT5=2us(min)
`
`tZQCAL = 1us(min)
`
`tZQLAT = Max(30ns, 8tCK)(Min)
`
`Exit PD
`
`DES
`
`MRW
`MRR
`
`DES
`
`ZQ Cal
`Start
`
`DES
`
`ZQ Cal
`Latch
`
`DES
`
`CA BUS
`Training
`
`DES
`
`Write
`Leveling
`
`DES
`
`DQ
`Training
`
`DES
`
`Valid
`
`Valid
`
`Valid
`
`Valid
`
`CK_c
`CK_t
`
`Supplies
`
`Reset_n
`
`CKE
`
`CA[5:0]
`CS
`
`DQs
`
`NOTES : 1. Training is optional and may be done at the system architects discretion. The training sequence after ZQ_CAL Latch(Th, Sequence7~9) in Figure 1 is simplified recommendation and actual training
` sequence may vary depending on systems.
`
`Figure 3 — Power Ramp and Initialization Sequence
`
`4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. Clock(CK_t,CK_c) is required to be started and stabilized for tINIT4
`before CKE goes active(Td). CS is required to be maintained LOW when controller activates CKE.
`
`5. After setting CKE high, wait minimum of tINIT5 to issue any MRR or MRW commands(Te). For both MRR and MRW commands, the clock frequency
`must be within the range defined for tCKb. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the
`system is appropriately configured.
`
`6. After completing all MRW commands to set the Pull-up, Pull-down and Rx termination values, the DRAM controller can issue ZQCAL Start command
`to the memory(Tf). This command is used to calibrate VOH level and output impedance over process, voltage and temperature. In systems where
`more than one LPDDR4 DRAM devices share one external ZQ resistor, the controller must not overlap the ZQ calibration sequence of each
`LPDDR4 device. ZQ calibration sequence is completed after tZQCAL (Tg) and the ZQCAL Latch command must be issued to update the DQ drivers
`and DQ+CA ODT to the calibrated values.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0017
`
`

`

`JEDEC Standard No. 209-4
`Page 14
`
`3.3.1
`
`Voltage Ramp and Device Initialization
`
`7. After tZQLAT is satisfied (Th) the command bus (internal VREF(ca), CS, and CA) should be trained for
`high-speed operation by issuing an MRW command (Command Bus Training Mode). This command is
`used to calibrate the device's internal VREF and align CS/CA with CK for high-speed operation. The
`LPDDR4 device will power-up with receivers configured for low-speed operations, and VREF(ca) set to a
`default factory setting. Normal device operation at clock speeds higher than tCKb may not be possible
`until command bus training has been completed.
`
`NOTE The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and
`outputs the results asynchronously on the DQ bus. See 4.21, (item 1.), MRW for information on how to enter/exit the
`training mode.
`
`8. After command bus training, DRAM controller must perform write leveling. Write leveling mode is
`enabled when MR2 OP[7] is high (Ti). See 4.23, Mode Register Write-WR Leveling Mode, for detailed
`description of write leveling entry and exit sequence. In write leveling mode, the DRAM controller adjusts
`write DQS_t/_c timing to the point where the LPDDR4 device recognizes the start of write DQ data burst
`with desired write latency.
`
`9. After write leveling, the DQ Bus (internal VREF(dq), DQS, and DQ) should be trained for high-speed
`operation using the MPC training commands and by issuing MRW commands to adjust VREF(dq)(Tj).
`The LPDDR4 device will power-up with receivers configured for low-speed operations and VREF(dq) set
`to a default factory setting. Normal device operation at clock speeds higher than tCKb should not be
`attempted until DQ Bus training has been completed. The MPC Read Calibration command is used
`together with MPC FIFO Write/Read commands to train DQ bus without disturbing the memory array
`contents. See 4.25, DQ Bus Training for detailed DQ Bus Training sequence.
`
`10. At Tk the LPDDR4 device is ready for normal operation, and is ready to accept any valid command.
`Any more registers that have not previously been set up for normal operation should be written at this
`time.
`
`Table 5 — Initialization Timing Parameters
`Value
`Unit
`Comment
`
`Parameter
`
`tINIT0
`
`tINIT1
`
`tINIT2
`
`tINIT3
`tINIT4
`
`tINIT5
`
`Min
`-
`
`200
`
`10
`
`2
`5
`
`2
`
`Max
`20
`
`-
`
`-
`
`-
`-
`
`-
`
`ms Maximum voltage-ramp time
`us Minimum RESET_n LOW time after completion of
`voltage ramp
`
`ns Minimum CKE low time before RESET_n high
`
`ms Minimum CKE low time after RESET_n high
`tCK Minimum stable clock before first CKE high
`us Minimum idle time before first MRW/MRR
`command
`us
`ZQ calibration time
`ns
`ZQCAL latch quiet time.
`ns
`Clock cycle time during boot
`
`-
`1
`tZQCAL
`-
`tZQLAT Max(30ns, 8tCK)
`Note *1,2
`Note *1,2
`tCKb
`NOTE 1 Min tCKb guaranteed by DRAM test is 18ns.
`NOTE 2 The system may boot at a higher frequency than dictated by min tCKb. The higher boot frequency is system
`dependent.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2013, 0018
`
`

`

`JEDEC Standard No. 209-4
`Page 15
`
`3.3.2 Reset Initialization with Stable Power
`The following sequence is required for RESET at no power interruption initialization.
`1. Assert RESET_n below 0.2 x VDD2 anytime when reset is needed. RESET_n needs to be maintained
`for minimum tPW_RESET. CKE must be pulled LOW at least 10 ns before de-asserting RESET_n.
`
`2. Repeat steps 4 to 10 in 3.3.1, Voltage Ramp and Device Initialization.
`
`Parameter
`
`tPW_RESET
`
`Min
`
`100
`
`Table 6 — Reset Timing Parameter
`Value
`Unit
`
`Max
`
`Comment
`
`-
`
`ns Minimum RESET_n low Time for Reset
`Initialization with stable power
`
`3.3.3 Power-off Sequence
`The following procedure is required to power off the device.
`While powering off, CKE must be held LOW (≤0.2 X VDD2) and all other inputs must be between VILmin
`and VIHmax. The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t and DQS_c
`voltage levels must be between Vssq and Vddq during voltage ramp to avoid latch-up. RESET_n, CK_t,
`CK_c, CS and CA input levels must be between VSS and VDD2 during voltage ramp to avoid latch-up.
`Tx is the point where any power supply drops below the minimum value specified.
`Tz is the point where all power supplies are below 300mV. After TZ, the device is powered off.
`
`After
`
`Table 7 — Power Supply Conditions
`Applicable Conditions
`VDD1 must be greater than VDD2
`VDD2 must be greater than VDDQ - 200mV
`The voltage difference between any of VSS, VSSQ pins must not exceed 100mV.
`
`Tx and Tz
`
`3.3.4 Uncontrolled Power-Off Sequence
`When an uncontrolled power-off occurs, the following conditions must be met:
`At Tx, when the power supply drops below the minimum values specified, all power supplies must be
`turned off and all power supply current capacity must be at zero, except any static charge remaining in