JEDEC
`STANDARD
`
`Low Power Double Data Rate 3
`(LPDDR3)
`
`JESD209-3
`
`MAY 2012
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`SPECIAL DISCLAIMER: JEDEC has received
`information that certain patents or patent applications
`may be essential to this standard. However, as of the
`publication date of this standard, no statements
`regarding an assurance or refusal to license such
`patents or patent applications have been provided.
`Contact JEDEC for further information.
`
`JEDEC does not make any determination as to the
`validity or relevancy of such patents or patent
`applications. Anyone making use of the standard
`assumes all liability resulting from such use. JEDEC
`disclaims any representation or warranty, express or
`implied, relating to the standard and its use.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0001
`
`

`

`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and approved
`through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal
`counsel.
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the
`proper product for use by those other than JEDEC members, whether the standard is to be used either
`domestically or internationally.
`JEDEC standards and publications are adopted without regard to whether or not their adoption may
`involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to
`any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or
`publications.
`The information included in JEDEC standards and publications represents a sound approach to product
`specification and application, principally from the solid state device manufacturer viewpoint. Within the
`JEDEC organization there are procedures whereby a JEDEC standard or publication may be further
`processed and ultimately become an ANSI standard.
`No claims to be in conformance with this standard may be made unless all requirements stated in the
`standard are met.
`Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should
`be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org
`
`Published by
`©JEDEC Solid State Technology Association 2012
`3103 North 10th Street
`Suite 240 South
`Arlington, VA 22201-2107
`
`This document may be downloaded free of charge; however JEDEC retains the
`copyright on this material. By downloading this file the individual agrees not to
`charge for or resell the resulting material.
`
`PRICE: Please refer to the current
`Catalog of JEDEC Engineering Standards and Publications online at
`http://www.jedec.org/Catalog/catalog.cfm
`
`Printed in the U.S.A.
`All rights reserved
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0002
`
`

`

`PLEASE!
`
`DON'T VIOLATE
`THE
`LAW!
`
`This document is copyrighted by the JEDEC Solid State Technology
`Association and may not be
`reproduced without permission.
`
`For information, contact:
`
`JEDEC Solid State Technology Association
`3103 North 10th Street, Suite 240 South
`Arlington, Virginia 22201-2107
`or call (703) 907-7559
`
`or refer to www.jedec.org under Standards-Documents/Copyright Information
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0003
`
`

`

`Special Disclaimer
`
`JEDEC has received information that certain patents or patent applications
`may be essential to this standard. However, as of the publication date of
`this standard, no statements regarding an assurance or refusal to license
`such patents or patent applications have been provided. Contact JEDEC
`for further information.
`
`JEDEC does not make any determination as to the validity or relevancy of
`such patents or patent applications. Anyone making use of the standard
`assumes all liability resulting from such use. JEDEC disclaims any
`representation or warranty, express or implied, relating to the standard and
`its use.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0004
`
`

`

`JEDEC Standard No. 209-3
`Page 1
`
`LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)
`
`(From JEDEC Board ballot JCB-(cid:20)(cid:21)-(cid:21)(cid:21), formulated under the cognizance of the JC-42.6 Subcommittee on Low
`Power Memory.)
`
`1
`
`Scope
`
`This document defines the LPDDR3 specification, including features, functionalities, ACand DC characteristics,
`packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements
`for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This specification was created using
`aspects of the following specifications: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2
`(JESD209-2). Each aspect of the specification was considered and approved by committee ballot(s). The
`accumulation of these ballots was then incorporated to prepare the LPDDR3 specification.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0005
`
`

`

`JEDEC Standard No. 209-3
`Page 2
`
`VDD1_a
`
`VDD2_a/b
`
`DQ1_a
`
`VDDQ_a
`
`VSSQ_a
`
`DQ0_a
`
`DM2_a
`
`VDDQ_a
`
`DQS2_t_a DQS2_c_a
`
`VSSQ_a
`
`DQ23_a
`
`VDDQ_a
`
`DQ22_a
`
`DQ20_a
`
`DQ21_a
`
`DQ19_a
`
`VSSQ_a
`
`DQ18_a
`
`B
`
`VSSQ_b/
`VSS
`
`NC
`
`DQ31_a
`
`VDDQ_a
`
`DQ28_a
`
`DQ27_a
`
`VDDQ_a
`
`DQ24_a
`
`VDDQ_a
`
`DQS3_t_a
`
`DM3_a
`
`DQ15_a
`
`VDDQ_a
`
`VSSQ_a Vref(DQ)_a
`
`VDD2_a
`
`DQ12_a
`
`VDDQ_a
`
`DQ8_a
`
`DQS1_c_a
`
`C VDD1_a/b
`
`DQ16_b
`
`D
`
`E
`
`F
`
`DQ17_b
`
`VDDQ_b
`
`DQ18_b
`
`DQ19_b
`
`VSSQ_b
`
`DQ20_b
`
`G DQ21_b
`
`VDDQ_b
`
`H
`
`J
`
`DQ22_b
`
`DQ23_b
`
`VSSQ_b
`
`VDDQ_b
`
`K DQS2_c_b DQS2_t_b
`
`L
`
`M
`
`DM2_b
`
`DQ0_b
`
`VSSQ_b
`
`Channel b
`
`Channel a
`
`2 Package ballout & Pin Definition
`
`2.1 POP FBGA Ball-outs
`2.1.1 216-ball 12mm x 12mm 0.4mm Pitch Dual-Channel POP FBGA (top view) Using Variation VCCCDB for MO-273
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`A
`
`DNU
`
`VSSa/b
`
`VDD2_a/b
`
`DQ30_a
`
`DQ29_a
`
`VSSQ_a
`
`DQ26_a
`
`DQ25_a
`
`VSSQ_a DQS3_c_a
`
`VSSQ_a
`
`DQ14_a
`
`DQ13_a
`
`VSS_a
`
`VDD1_a
`
`VDD2_a
`
`DQ11_a
`
`DQ10_a
`
`DQ9_a
`
`DQS1_t_a
`
`DM_1_a
`
`VDDQ_a DQS0_t_a
`
`DQ7_a
`
`DQ6_a
`
`DQ4_a
`
`DQ3_a
`
`VSS_a/b
`
`DNU
`
`VSSQ_a
`
`DM_0_a DQS0_c_a
`
`VSSQ_a
`
`VDDQ_a
`
`DQ5_a
`
`DQ2_a
`
`NC
`
`VSSQ_a
`
`Note 1: 12x12 mm, 0.4mm pitch, 29 rows
`Note 2: 216 Ball Count
`Note 3: Top View, A1 in Top Left Corner
`Note 4: See JESD21-C, Section 3.12.2
`Note 5: ODT pin is NOT supported. ODT die pads are connected to VSS inside the package.
`Note 6: VSS_a, VSS_b, VSS_a/b, VSSQ_a, VSSQ_b, VSSQ_b/VSS, VSSCA_a, and VSSCA_b, may
`be connected to a common VSS inside the package, see manufacturer datasheet for actual connection.
`As such, all balls labeled VSSxyz are equivalent to the label “VSSxyz, VSS”.
`
`Power
`
`Ground
`
`Do Not Use
`
`ZQ
`
`Clock
`
`NC
`
`VDDQ_a
`
`DQ16_a
`
`DQ17_a
`
`VDD2_b
`
`VDD1_b
`
`VSS_b
`
`CA0_b
`
`VDDCA_b
`
`CA1_b
`
`Vref(CA)_b
`
`CA2_b
`
`VSSCA_b
`
`CA3_b
`
`CA4_b
`
`CSB1_b
`
`CSB0_b
`
`CKE1_b
`
`VSSCA_b
`
`CKE0_b
`
`CK_t_b
`
`CK_c_b
`
`VDDCA_b
`
`CA5_b
`
`CA7_b
`
`CA6_b
`
`CA8_b
`
`VDDCA_b
`
`DQ1_b
`
`N
`
`P
`
`R
`
`T
`
`DQ2_b
`
`VDD1_b
`
`VSS_b
`
`VSS_b
`
`VDD1_b
`
`Vref(DQ)_b
`
`VDD2_b
`
`VDD2_b
`
`U VDDQ_b
`
`DQ3_b
`
`V
`
`DQ4_b
`
`VSSQ_b
`
`W DQ6_b
`
`DQ5_b
`
`Y
`
`VDDQ_b
`
`DQ7_b
`
`AA DQS0_t_b DQS0_c_b
`
`AB
`
`DM0_b
`
`VSSQ_b
`
`AC VDDQ_b
`
`DM1_b
`
`AD DQS1_c_b DQS1_t_b
`
`AE
`
`VSSQ_b
`
`DQ8_b
`
`AF
`
`DQ9_b
`
`VDDQ_b
`
`AG DQ10_b
`
`DQ11_b
`
`VSSCA_b
`
`CA9_b
`
`VDD2_a/b
`
`ZQ_b
`
`AH VSSQ_b
`
`VDD1_a/b VDD2_a/b
`
`DQ13_b
`
`VSSQ_b
`
`DQ15_b
`
`DM3_b
`
`DQS3_t_b
`
`VDDQ_b
`
`DQ26_b
`
`DQ27_b
`
`VDDQ_b
`
`DQ30_b
`
`VSSQ_b
`
`VDD2_a
`
`Vref(CA)_a
`
`CA9_a
`
`VSSCA_a
`
`CA7_a
`
`CA6_a
`
`CK_c_a
`
`VDDCA_a
`
`CKE0_a
`
`CSB0_a
`
`CA3_a
`
`CA2_a
`
`CA1_a
`
`VDD1_a/b VSSCA_a
`
`AJ
`
`DNU
`
`VSS_a/b
`
`DQ12_b
`
`VDDQ_b
`
`DQ14_b
`
`VDDQ_b
`
`VSSQ_b DQS3_c_b
`
`DQ24_b
`
`DQ25_b
`
`VSSQ_b
`
`DQ28_b
`
`DQ29_b
`
`DQ31_b
`
`VDD1_a
`
`VSS_a
`
`ZQ_a
`
`CA8_a
`
`VDDCA_a
`
`CA5_a
`
`CK_t_a
`
`VSSCA_a
`
`CKE1_a
`
`CSB1_a
`
`CA4_a
`
`VDDCA_a
`
`CA0_a
`
`VSS_a/b
`
`DNU
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0006
`
`

`

`2.1.2 256-ball 14mm x 14mm 0.4mm Pitch Dual-Channel POP FBGA (top view) Using Variation VEECDB for MO-273
`
`ODT_a Vref(DQ)_
`a
`DM0_a DQS0_t_a
`
`VSS
`
`2
`
`DNU
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`VDD2
`
`DQ30_a DQ28_a DQ27_a
`
`VDDQ
`
`DQ24_a DQS3_t_a VDDQ
`
`VDD2
`
`DQ15_a
`
`VDDQ
`
`DQ12_a DQ11_a
`
`VDDQ
`
`DQ8_a DQS1_t_a VDDQ
`
`VDD2
`
`VSS
`
`VDD1
`
`DQ31_a DQ29_a
`
`VSS
`
`DQ26_a DQ25_a
`
`VSS
`
`DQS3_c_a DM3_a
`
`VSS
`
`DQ14_a DQ13_a
`
`VSS
`
`DQ10_a
`
`DQ9_a
`
`VSS
`
`DQS1_c_a DM1_a
`
`VDD1
`
`VSS
`
`DQ21_b
`
`VSS
`
`DM2_b
`
`VSS
`
`DQ1_b
`
`DQ2_b
`
`VSS
`
`DQ5_b
`
`DQ6_b
`
`VSS
`
`DM0_b
`
`VSS
`
`DM1_b
`
`b
`
`VDD1
`VDD2
`VDDCA
`VDDQ
`VSS
`Vref(CA)_a, Vref(CA)_b, Vref(DQ)_a, Vref(DQ)_b
`Channel a, DQ,DQS_t,DQS_c,DM,CA,CS_n,CKE
`Channel b, DQ,DQS_t,DQS_c,DM,CA,CS_n,CKE
`CK_t,CK_c
`ZQ
`RFU
`
`VDDQ DQS0_c_a DQ7_a
`
`VDDQ
`
`DQ4_a
`
`DQ3_a
`
`VDDQ
`
`DQ0_a
`
`VDDQ
`
`VDD2
`
`DNU
`
`VSS
`
`DQ6_a
`
`DQ5_a
`
`VSS
`
`DQ2_a
`
`DQ1_a
`
`VSS
`
`DM2_a
`
`VDD1
`
`VSS
`
`VSS
`
`DQ21_a
`
`VSS
`
`VSS
`
`VDD1
`
`VSS
`
`CA0_b
`
`CA2_b
`
`VSS
`
`CA4_b
`
`VSS
`
`CK_c_b
`
`VSS
`
`JEDEC Standard No. 209-3
`Page 3
`
`1
`A DNU
`B DNU
`C VDD2
`D DQ17_b DQ16_b
`E DQ19_b DQ18_b
`F DQ20_b
`G VDDQ
`H DQ23_b DQ22_b
`J DQS2_t_b
`K VDDQ DQS2_c_b
`L VDD2
`M DQ0_b
`N VDDQ
`P DQ3_b
`R DQ4_b
`T VDDQ
`U DQ7_b
`V DQS0_c_b
`W VDDQ DQS0_t_b
`Y Vref(DQ)_
`AA ODT_b
`AB VDD2
`AC VDDQ DQS1_c_b
`AD DQS1_t_b
`AE DQ8_b
`AE VDDQ
`AG DQ11_b
`AH DQ12_b DQ13_b
`AJ VDDQ
`AK DQ15_b
`AL VDDQ
`AM VDD2
`AN DNU
`AP DNU
`1
`
`VSS
`
`DQ9_b
`
`DQ10_b
`
`VSS
`
`DQ14_b
`
`VSS
`
`DM3_b
`
`VDD1
`
`VSS
`
`DNU
`
`2
`
`DQS3_c_b
`
`VSS
`
`DQ25_b DQ26_b
`
`VSS
`
`DQ29_b DQ31_b
`
`VDDQ DQS3_t_b DQ24_b
`
`VDDQ
`
`DQ27_b DQ28_b DQ30_b
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`VSS
`
`VDD1
`
`RFU
`
`ZQ0_a
`
`CA8_a
`
`VSS
`
`CA6_a
`
`VSS
`
`Vref(CA)_a CK_c_a
`
`VSS
`
`CKE1_a CS1_n_a
`
`CA4_a
`
`VSS
`
`CA2_a
`
`CA0_a
`
`VSS
`
`VDD1
`
`VSS
`
`DNU
`
`DNU
`
`DNU
`
`DNU
`
`VDDQ
`
`VDD2
`
`ZQ1_a
`
`CA9_a
`
`VDDCA
`
`CA7_a
`
`CA5_a
`
`VDDCA
`
`VDD2
`
`CK_t_a
`
`VDDCA
`
`CKE0_a CS0_n_a
`
`CA3_a
`
`VDD2
`
`CA1_a
`
`VDDCA
`
`VSS
`
`VDD2
`
`VSS
`
`DNU
`
`DNU
`
`DNU
`
`DNU
`
`10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
`DNU A
`DNU B
`DQS2_c_a VDDQ C
`DQS2_t_a D
`DQ22_a DQ23_a E
`VDDQ F
`DQ20_a G
`DQ18_a DQ19_a H
`DQ16_a DQ17_a J
`VDDQ K
`VDD2 L
`VSS M
`VDDCA N
`CA1_b P
`VDD2 R
`CA3_b T
`CS1_n_b CS0_n_b U
`CKE1_b CKE0_b V
`VDDCA W
`CK_t_b Y
`Vref(CA)_b VDD2 AA
`VDDCA AB
`CA5_b AC
`CA7_b AD
`VDDCA AE
`CA9_b AE
`ZQ1_b AG
`VDD2 AH
`VSS AJ
`DNU AK
`DNU AL
`DNU AM
`DNU AN
`DNU AP
`10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
`
`NOTE 1 14mm x 14mm, 0.4mm pitch, 34rows x 34 columns
`NOTE 2 256 ball count
`NOTE 3 Top View, A1 in Top Left Corner
`NOTE 4 ODT will be connected to rank 0. The ODT input to rank 1 (if 2nd rank is present) will be connected to GND
`in the package.
`NOTE 5 For Channel using x32 DRAM
`- ZQ0 is connected to rank 0 DRAM and rank 1 DRAM (if 2nd rank is present).
`- ZQ1 is NC.
`NOTE 6 For Channel using x16 DRAM
`- ZQ0 is connected to Byte 0-1 of rank 0 DRAM and rank 1 DRAM (if 2nd rank is present).
`- ZQ1 is connected to Byte 2-3 of rank 0 DRAM and rank 1 DRAM (if 2nd rank is present).
`
`CA6_b
`
`VSS
`
`CA8_b
`
`ZQ0_b
`
`RFU
`
`VDD1
`
`VSS
`
`DNU
`
`DNU
`
`DNU
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0007
`
`

`

`JEDEC Standard No. 209-3
`Page 4
`
`A
`
`2.2 FBGA Package Ball-outs
`2.2.1 253-Ball 0.5mm Pitch Discrete Dual-Channel FBGA (top view) MO TBD
`
`1
`
`NC
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VDDCA_a/b VDD2_a/b
`
`VSS_a/b
`
`VDDCA_a/b Vref(CA)_a VDD2_a/b
`
`VSS_a/b
`
`VDDQ_a/b
`
`VSS_a/b
`
`VDD1_a/b VDD1_a/b
`
`17
`
`NC
`
`A
`
`B
`
`C
`
`VSS_a/b
`
`VDD1_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`CA0_a
`
`CA3_a
`
`CSB1_a
`
`CK_t_a
`
`VDDCA_a/b
`
`CA7_a
`
`ZQ0_a
`
`VDDQ_a/b
`
`DQ28_b
`
`DQ29_b
`
`DQ30_b
`
`DQ31_b
`
`VDD2_a/b B
`
`VSS_a/b
`
`VSS_a/b
`
`VDD2_a/b
`
`VSS_a/b
`
`CA1_a
`
`CA4_a
`
`CKE0_a
`
`CK_c_a
`
`CA5_a
`
`CA8_a
`
`ZQ1_a
`
`VDDQ_a/b
`
`DQ24_b
`
`DQ25_b
`
`DQ26_b
`
`DQ27_b
`
`VDD2_a/b C
`
`DQ15_b
`
`DM3_b
`
`DQS3_c_b DQS3_t_b
`
`VSS_a/b
`
`D
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`CA2_a
`
`CSB0_a
`
`CKE1_a
`
`RFU
`
`CA6_a
`
`CA9_a
`
`RFU
`
`VSS_a/b
`
`E VDDCA_a/b
`
`ZQ0_b
`
`ZQ1_b
`
`RFU
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`DQ11_b
`
`DQ12_b
`
`DQ13_b
`
`DQ14_b
`
`D
`
`VDDQ_a/b E
`
`F
`
`G
`
`VSS_a/b
`
`CA7_b
`
`CA8_b
`
`CA9_b
`
`VSS_a/b
`
`VDDCA_a/b
`
`CA5_b
`
`CA6_b
`
`VSS_a/b
`
`H VDD2_a/b
`
`CK_c_b
`
`CK_t_b
`
`RFU
`
`VSS_a/b
`
`VSS_a/b
`
`DM1_b
`
`DQ8_b
`
`DQ9_b
`
`DQ10_b
`
`VSS_a/b
`
`F
`
`VDDQ_a/b DQS1_c_b DQS1_t_b
`
`VSS_a/b
`
`VSS_a/b
`
`VDDQ_a/b G
`
`VSS_a/b
`
`ODT_b
`
`DM0_b
`
`VSS_a/b
`
`VDD2_a/b Vref(DQ)_b H
`
`Vref(CA)_b
`
`CSB1_b
`
`CKE0_b
`
`CKE1_b
`
`VSS_a/b
`
`RFU
`
`DQS0_c_b DQS0_t_b
`
`DQ6_b
`
`DQ7_b
`
`VSS_a/b
`
`VSS_a/b NOTE 1 Pins E4, H4, D8, M9, and J12 are reserved as “RFU”s.
`NOTE 2 ODT will be connected to rank 0. The ODT input to rank
`1 (if 2nd rank is present) will be connected to GND in the package.
`NOTE 3 For Channel using x32 DRAM
`- ZQ0 is connected to rank 0 DRAM and rank 1 DRAM (if
`2nd rank is present).
`- ZQ1 is NC.
`NOTE 4 For Channel using x16 DRAM
`- ZQ0 is connected to Byte 0-1 of rank 0 DRAM and rank
`1 DRAM (if 2nd rank is present).
`- ZQ1 is connected to Byte 2-3 of rank 0 DRAM and rank
`1 DRAM (if 2nd rank is present).
`
`VSS_a/b
`
`VSS_a/b
`
`J
`
`K VDDCA_a/b
`
`CA3_b
`
`CA4_b
`
`CSB0_b
`
`L VDD2_a/b
`
`CA0_b
`
`CA1_b
`
`CA2_b
`
`VDDQ_a/b
`
`DQ2_b
`
`DQ3_b
`
`DQ4_b
`
`DQ5_b
`
`VSS_a/b
`
`DQ23_b
`
`DM2_b
`
`DQ0_b
`
`DQ1_b
`
`J
`
`VDDQ_a/b K
`
`VDDQ_a/b L
`
`VSS_a/b M
`
`M VSS_a/b
`
`N VDDQ_a/b
`
`VDDQ_a/b VDDQ_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VDDQ_a/b
`
`VSS_a/b
`
`RFU
`
`VDDQ_a/b
`
`VSS_a/b
`
`VDDQ_a/b
`
`DQ21_b
`
`DQ22_b
`
`DQS2_c_b DQS2_t_b
`
`DQ19_a
`
`DQ23_a
`
`DQ0_a
`
`DQ4_a
`
`DM0_a
`
`DQS0_c_a
`
`ODT_a
`
`DQS1_c_a
`
`DQ13_a
`
`DQ24_a
`
`DQ25_a
`
`VSS_a/b
`
`DQ18_b
`
`DQ19_b
`
`DQ20_b
`
`VSS_a/b
`
`N
`
`DQ22_a
`
`DM2_a
`
`DQ3_a
`
`DQ7_a
`
`DQS0_t_a
`
`DM1_a
`
`DQS1_t_a
`
`DQ12_a
`
`DM3_a
`
`DQ26_a
`
`DQ29_a
`
`VSS_a/b
`
`DQ16_b
`
`DQ17_b
`
`VDDQ_a/b
`
`P
`
`VSS_a/b
`
`DQ18_a
`
`R VDD1_a/b
`
`T VDD1_a/b
`
`DQ17_a
`
`DQ21_a
`
`DQS2_c_a
`
`DQ2_a
`
`DQ6_a
`
`VSS_a/b
`
`VSS_a/b
`
`DQ9_a
`
`DQ11_a
`
`DQ15_a
`
`DQS3_c_a
`
`DQ28_a
`
`DQ31_a
`
`VDD2_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`DQ16_a
`
`DQ20_a
`
`DQS2_t_a
`
`DQ1_a
`
`DQ5_a
`
`VSS_a/b
`
`VDD2_a/b
`
`DQ8_a
`
`DQ10_a
`
`DQ14_a
`
`DQS3_t_a
`
`DQ27_a
`
`DQ30_a
`
`VSS_a/b
`
`VDD1_a/b
`
`VSS_a/b
`
`U
`
`NC
`
`VDD2_a/b
`
`VDD2_a/b
`
`VSS_a/b
`
`VDDQ_a/b
`
`VSS_a/b
`
`VDDQ_a/b Vref(DQ)_a
`
`VSS_a/b
`
`VDDQ_a/b VDDQ_a/b
`
`VSS_a/b
`
`VSS_a/b
`
`VDDQ_a/b VSS_a/b
`
`VSS_a/b
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`NC
`
`17
`
`P
`
`R
`
`T
`
`U
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0008
`
`

`

`JEDEC Standard No. 209-3
`Page 5
`
`2.2.2 178-Ball Discrete Single-Channel FBGA (top view) MO TBD
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`DNU
`
`DNU
`
`VDD1
`
`VDD1
`
`VDD1
`
`VDD1
`
`VDD2
`
`VDD2
`
`VDD1 VDDQ
`
`DNU
`
`DNU
`
`DNU
`
`VSS
`
`ZQ0
`
`ZQ1
`
`VSS
`
`VSSQ
`
`CA9
`
`VSSCA
`
`NC
`
`VSS
`
`VSSQ
`
`DQ31
`NC
`
`DQ27
`NC
`
`DQ30
`NC
`
`DQ26
`NC
`
`DQ29
`NC
`
`DQ25
`NC
`
`DQ28
`NC
`
`DQ24
`NC
`
`VSSQ
`
`DNU
`
`VDDQ
`
`A
`
`B
`
`C
`
`A
`
`B
`
`C
`
`D
`
`E
`
`F
`
`G
`
`H
`
`J
`
`CA8
`
`VSSCA VDD2
`
`VDD2
`
`VDD2
`
`DM3
`NC
`
`DQ15
`
`DQS3_t
`NC
`
`DQS3_c
`NC
`
`VSSQ
`
`CA7
`
`CA6
`
`VSS
`
`VSS
`
`VSSQ
`
`VDDQ
`
`DQ14
`
`DQ13
`
`DQ12
`
`VDDQ
`
`VDDCA CA5
`
`VSSCA
`
`VSS
`
`VSSQ
`
`DQ11
`
`DQ10
`
`DQ9
`
`DQ8
`
`VSSQ
`
`VDDCA VSSCA VSSCA VDD2
`
`VSSQ
`
`DM1
`
`VSSQ DQS1_t DQS1_c VDDQ
`
`VSS
`
`VDDCA Vref(CA) VDD2
`
`VDD2
`
`VDDQ VDDQ
`
`VSSQ
`
`VDDQ VDD2
`
`VSSCA VDD2
`
`VDD2
`
`ODT
`
`VDDQ VDDQ Vref(DQ) VSS
`
`D
`
`E
`
`F
`
`G
`
`H
`
`J
`
`CK_c
`
`CK_t
`
`K
`
`L
`
`M
`
`N
`
`P
`
`VSS
`
`CKE0
`
`CKE1
`
`VDD2
`
`VDD2
`
`VDDQ
`
`NC
`
`VSSQ
`
`VDDQ VDD2
`
`VDDCA CS0_n
`
`CS1_n
`
`VDD2
`
`VSS
`
`DM0
`
`VSSQ DQS0_t DQS0_c VDDQ
`
`VDDCA CA4
`
`VSSCA
`
`VSS
`
`VSSQ
`
`DQ4
`
`DQ5
`
`DQ6
`
`DQ7
`
`VSSQ
`
`CA2
`
`CA3
`
`VSS
`
`VSS
`
`VSSQ
`
`VDDQ
`
`DQ1
`
`DQ2
`
`DQ3
`
`VDDQ
`
`CA1
`
`VSSCA VDD2
`
`VDD2
`
`VDD2
`
`DM2
`
`DQ0
`
`DQS2_c
`NC
`
`VSSQ
`
`K
`
`L
`
`M
`
`N
`
`P
`
`CA0
`
`NC
`
`VSS
`
`VSS
`
`VSSQ
`
`DNU
`
`VSS
`
`VSS
`
`VSS
`
`VSS
`
`VSSQ
`
`DQS2_t
`NC
`
`DQ22
`NC
`
`DQ18
`NC
`
`DQ20
`NC
`
`DQ16
`NC
`
`DQ21
`NC
`
`DQ17
`NC
`
`DQ23
`NC
`
`DQ19
`NC
`
`VDDQ
`
`VSSQ
`
`DNU
`
`DNU
`
`DNU
`
`VDD1
`
`VDD1
`
`VDD1
`
`VDD1
`
`VDD2
`
`VDD2
`
`VDD1 VDDQ
`
`DNU
`
`DNU
`
`R
`
`T
`
`U
`
`R
`
`T
`
`U
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`NOTE 1 When using the x16 configuration DQ16 through DQ31 become NC as indicated by the second row of sig-
`nal names for those signals in the ball-out diagram.
`NOTE 2 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), x16/x32, 17 rows
`NOTE 3 Top View, A1 in Top Left Corner
`NOTE 4 See JESD21-C, Section 3.12.1
`NOTE 5 ODT will be connected to rank 0. The ODT input to rank 1 (if 2nd rank is present) will be connected to
`GND in the package.
`NOTE 6 For Channel using x32 DRAM
`- ZQ0 is connected to rank 0 DRAM and rank 1 DRAM (if present).
`- ZQ1 is NC
`NOTE 7 For Channel using x16 DRAM
`- ZQ0 is connected to Byte 0-1 of rank 0 DRAM and rank 1 DRAM (if present).
`- ZQ1 is connected to Byte 2-3 of rank 0 DRAM and rank 1 DRAM (if present).
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0009
`
`

`

`JEDEC Standard No. 209-3
`Page 6
`
`2.2.3 346-ball 0.5mm Pitch Dual-Channel Multi-Chip Package (MCP) FBGA (top view) MO TBD
`
`1
`
`2
`
`3
`
`4
`
`NC
`
`5
`
`6
`
`7
`
`NC
`
`8
`
`9
`
`10
`
`11
`
`NC
`
`12
`
`13
`
`14
`
`15
`
`NC
`
`16
`
`17
`
`18
`
`NC
`
`19
`
`20
`
`21
`
`NC
`
`DNU
`
`DNU
`
`CLEn
`NCm
`
`VCCn
`VCCQm
`
`R/B0n
`DATA5m
`
`VCCn
`VCCQm
`
`R/B1n
`CLKm
`
`VCCn
`VCCQm
`
`CEB1n
`RSTm
`
`VCCn
`VCCQm
`
`CEB0n
`NCm
`
`VCCn
`VCCQm
`
`REBn
`VCCm
`
`VCCn
`VCCm
`
`DNU
`
`NCn
`VCCQm
`
`WEBn
`NCm
`
`VSSn
`VSSQm
`
`IO6n
`DAT1m
`
`VSSn
`VSSQm
`
`IO4n
`DAT2m
`
`VSSn
`VSSQm
`
`IO2n
`NCm
`
`VSSn
`VSSQm
`
`IO0n
`NCm
`
`VSSn
`VSSQm
`
`ALEn
`VCCm
`
`VSSn
`VSSm
`
`NCn
`NCm
`
`VSSn
`VSSm
`
`VSSn
`VSSm
`
`NCn
`NCm
`
`DNU
`
`DNU
`
`NC
`
`DNU
`
`NCn
`NCm
`
`NCn
`NCm
`
`A
`
`B C
`
`D
`
`E
`
`VCCn
`VCCm
`
`NCn
`VSSQm
`
`VCCn
`VCCm
`
`NCn
`VSSQm
`
`IO14n
`DAT4m
`
`NCn
`VSSQm
`
`IO12n
`DAT6m
`
`NCn
`VSSQm
`
`IO10n
`NCm
`
`NCn
`VSSQm
`
`VCCn
`VCCm
`
`VSSn
`VSSm
`
`VSSn
`VSSm
`
`VSSn
`VSSm
`
`VCCn
`VCCm
`
`NCn
`VSSQm
`
`IO7n
`DAT0m
`
`NCn
`VSSQm
`
`IO5n
`DAT3m
`
`NCn
`VSSQm
`
`IO3n
`NCm
`
`NCn
`VSSQm
`
`NCn
`NCm
`
`IO15n
`CMDm
`
`IO13n
`DAT7m
`
`IO11n
`NCm
`
`IO9n
`NCm
`
`IO8n
`NCm
`
`IO1n
`NCm
`
`NCn
`VDDIm
`
`WPBn
`VCCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NCn
`NCm
`
`NC
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDDCA
`_a/b
`
`VDD2_a
`/b
`
`VSS_a/
`b
`
`VDDCA
`_a/b
`
`Vref(CA)
`_a
`
`VDD2_a
`/b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`VDD1_a
`/b
`
`VDD1_a
`/b
`
`NC
`
`VSS_a/
`b
`
`VDD1_a
`/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`CA0_a CA3_a CSB1_a CK_t_a VDDCA
`_a/b
`
`CA7_a ZQ0_a VDDQ_
`a/b
`
`DQ28_b DQ29_b DQ30_b DQ31_b VDD2_a
`/b
`
`F
`
`G
`
`H J K L
`
`M
`
`N
`
`P
`
`R
`
`T
`
`U
`
`V
`
`W
`
`Y
`
`AA
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDD2_a
`/b
`
`VSS_a/
`b
`
`CA1_a CA4_a CKE0_a CK_c_a CA5_a CA8_a ZQ1_a VDDQ_
`a/b
`
`DQ24_b DQ25_b DQ26_b DQ27_b VDD2_a
`/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`CA2_a CSB0_a CKE1_a RFU
`
`CA6_a CA9_a
`
`RFU
`
`VSS_a/
`b
`
`DQ15_b DM3_b DQS3_c
`_b
`
`DQS3_t
`_b
`
`VSS_a/
`b
`
`VDDCA
`_a/b
`
`ZQ0_b ZQ1_b
`
`RFU
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`DQ11_b DQ12_b DQ13_b DQ14_b VDDQ_
`a/b
`
`VSS_a/
`b
`
`CA7_b CA8_b CA9_b VSS_a/
`b
`
`VSS_a/
`b
`
`VDDCA
`_a/b
`
`CA5_b CA6_b VSS_a/
`b
`
`VDD2_a
`/b
`
`CK_c_b CK_t_b
`
`RFU
`
`VSS_a/
`b
`
`Vref(CA)
`_b
`
`CSB1_b CKE0_b CKE1_b VSS_a/
`b
`
`VDDCA
`_a/b
`
`CA3_b CA4_b CSB0_b VSS_a/
`b
`
`VDD2_a
`/b
`
`CA0_b CA1_b CA2_b VSS_a/
`b
`
`VSS_a/
`b
`
`DM1_b DQ8_b DQ9_b DQ10_b VSS_a/
`b
`
`VDDQ_
`a/b
`
`DQS1_c
`_b
`
`DQS1_t
`_b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`ODT_b DM0_b VSS_a/
`b
`
`VDD2_a
`/b
`
`Vref(DQ
`)_b
`
`RFU DQS0_c
`_b
`
`DQS0_t
`_b
`
`DQ6_b DQ7_b VSS_a/
`b
`
`VDDQ_
`a/b
`
`DQ2_b DQ3_b DQ4_b DQ5_b VDDQ_
`a/b
`
`VSS_a/
`b
`
`DQ23_b DM2_b DQ0_b DQ1_b VDDQ_
`a/b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`RFU
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`DQ21_b DQ22_b DQS2_c
`_b
`
`DQS2_t
`_b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`DQ19_a DQ23_a DQ0_a DQ4_a DM0_a DQS0_c
`_a
`
`ODT_a DQS1_c
`_a
`
`DQ13_a DQ24_a DQ25_a VSS_a/
`b
`
`DQ18_b DQ19_b DQ20_b VSS_a/
`b
`
`VSS_a/
`b
`
`DQ18_a DQ22_a DM2_a DQ3_a DQ7_a DQS0_t
`_a
`
`DM1_a DQS1_t
`_a
`
`DQ12_a DM3_a DQ26_a DQ29_a VSS_a/
`b
`
`DQ16_b DQ17_b VDDQ_
`a/b
`
`VDD1_a
`/b
`
`DQ17_a DQ21_a DQS2_c
`_a
`
`DQ2_a DQ6_a VSS_a/
`b
`
`VSS_a/
`b
`
`DQ9_a DQ11_a DQ15_a DQS3_c
`_a
`
`DQ28_a DQ31_a VDD2_a
`/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDD1_a
`/b
`
`DQ16_a DQ20_a DQS2_t
`_a
`
`DQ1_a DQ5_a VSS_a/
`b
`
`VDD2_a
`/b
`
`DQ8_a DQ10_a DQ14_a DQS3_t
`_a
`
`DQ27_a DQ30_a VSS_a/
`b
`
`VDD1_a
`/b
`
`VSS_a/
`b
`
`NC
`
`NC
`
`VDD2_a
`/b
`
`VDD2_a
`/b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`Vref(DQ
`)_a
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VDDQ
`_a/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`VDDQ_
`a/b
`
`VSS_a/
`b
`
`VSS_a/
`b
`
`NC
`
`NC
`
`AB
`
`AC
`
`AD
`
`AE
`
`AF
`
`AG
`
`AH
`
`NC
`
`NC
`
`NC
`
`AJ
`NC
`NC
`NOTE 1 0.5mm ball pitch, 346 ball count
`NOTE 2 Target package sizes : 12mm x 16mm and 14mm x 18mm
`NOTE 3 Target package, size depends on Flash density.
`NOTE 4 Top view, A1 in top left corner
`NOTE 5 ODT will be connected to rank 0. The ODT input to rank 1 (if 2nd rank is present) will be connected to
`GND in the package.
`NOTE 6 For channel using x32 DRAM
`- ZQ0 is connected to R0 DRAM and R1 DRAM (if present)
`- ZQ1 is NC
`NOTE 7 For channel using x16 DRAM
`- ZQ0 is connected to Byte 0-1 of R0 DRAM and R1 DRAM (if present)
`- ZQ1 is connected to Byte 2-3 of R0 DRAM and R1 DRAM (if present)
`NOTE 8 For flash ball-out, “n” ball assignments are used for NAND flash, and “m” ball assignments for e-MMC.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0010
`
`

`

`JEDEC Standard No. 209-3
`Page 7
`
`2.3
`
`LPDDR3 Pad Sequence
`
`Table 1 — LPDDR3 Pad Sequence
`CA
`Pad
`Seq
`
`DQ Pad
`Sequence
`x32
`x16
`VDD2
`VDD2
`VSS
`VSS
`VSS*1
`VSS*1
`VDD1
`VDD1
`VDDQ
`VSSQ
`DQ31
`DQ30
`VDDQ
`DQ29
`DQ28
`VSSQ
`DQ27
`DQ26
`VDDQ
`DQ25
`DQ24
`VSSQ
`DQS3_t
`DQS3_c
`VDDQ
`DM3
`VSSQ
`DQ15
`DQ14
`VDDQ
`DQ13
`DQ12
`VSSQ
`DQ11
`DQ10
`VDDQ
`DQ9
`DQ8
`VSSQ
`DQS1_t
`DQS1_c
`VDDQ
`DM1
`VSSQ
`VDDQ
`
`VSSQ
`DQ15
`DQ14
`VDDQ
`DQ13
`DQ12
`VSSQ
`DQ11
`DQ10
`VDDQ
`DQ9
`DQ8
`VSSQ
`DQS1_t
`DQS1_c
`VDDQ
`DM1
`VSSQ
`VDDQ
`
`VDD2
`ODT
`VSS
`Vref(DQ)
`
`VDD2
`ODT
`VSS
`Vref(DQ)
`
`VSS
`VDD2
`
`VDDQ
`VSSQ
`DM0
`VDDQ
`DQS0_c
`DQS0_t
`VSSQ
`DQ7
`DQ6
`VDDQ
`DQ5
`DQ4
`VSSQ
`DQ3
`DQ2
`VDDQ
`DQ1
`DQ0
`VSSQ
`DM2
`VDDQ
`DQS2_c
`DQS2_t
`VSSQ
`DQ23
`DQ22
`VDDQ
`DQ21
`DQ20
`VSSQ
`DQ19
`DQ18
`VDDQ
`DQ17
`DQ16
`VSSQ
`VDDQ
`
`VDD1
`VSS*1
`VSS
`VDD2
`
`VSS
`VDD2
`
`VDDQ
`VSSQ
`DM0
`VDDQ
`DQS0_c
`DQS0_t
`VSSQ
`DQ7
`DQ6
`VDDQ
`DQ5
`DQ4
`VSSQ
`DQ3
`DQ2
`VDDQ
`DQ1
`DQ0
`VSSQ
`
`VDD1
`VSS*1
`VSS
`VDD2
`
`VDD2
`VSS
`VSS
`VDD1
`VDD2
`VSS
`
`ZQ
`CA9
`CA8
`VSSCA
`VDDCA
`CA7
`CA6
`CA5
`
`VDD2
`Vref(CA)
`VSS
`VDDCA
`CK_c
`CK_t
`VSSCA
`CKE
`CS_N
`CA4
`CA3
`CA2
`VDDCA
`VSSCA
`CA1
`CA0
`
`VSS
`VDD2
`VDD1
`VSS
`VSS
`VDD2
`
`NOTE 1 Pads with (*1) are optional.
`NOTE 2 Ordering of DQ bits shall be maintained in the system, including within the package and on the PCB.
`DQ byte swapping and DQ bit Swapping are not allowed in the system.
`NOTE 3 CA pads and DQ pads shall be separated on opposite sides of die from top of silicon view.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0011
`
`

`

`JEDEC Standard No. 209-3
`Page 8
`
`2.4
`
`Name
`CK_t, CK_c
`
`Type
`Input
`
`CKE
`
`CS_n
`
`Input
`
`Input
`
`CA0 - CA9
`
`Input
`
`LPDDDR3 Pad Definition and Description
`Table 2 — Pad Definition and Description
`Description
`Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are
`sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE,
`are sampled at the positive Clock edge.
`Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the
`crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint
`of a falling CK_t and a rising CK_c.
`Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore
`device input buffers and output drivers. Power savings modes are entered and exited through CKE
`transitions.
`CKE is considered part of the command code. See Command Truth Table for command code
`descriptions. CKE is sampled at the positive Clock edge.
`Chip Select: CS_n is considered part of the command code. See Command Truth Table for command
`code descriptions.
`CS_n is sampled at the positive Clock edge.
`DDR Command/Address Inputs: Uni-directional command/address bus inputs.
`CA is considered part of the command code. See Command Truth Table for command code
`descriptions.
`Data Inputs/Output: Bi-directional data bus
`
`DQ0 - DQ15 
`(x16)
`DQ0 - DQ31 
`(x32)
`DQS0_t,
`DQS0_c,
`DQS1_t,
`DQS1_c
`(x16)
`DQS0_t -
`DQS3_t,
`DQS0_c -
`DQS3_c
`(x32)
`DM0-DM1
`(x16)
`DM0 - DM3 
`(x32)
`
`ODT
`
`VDD1
`VDD2
`VDDCA
`VDDQ
`VREF(CA)
`
`VREF(DQ)
`VSS
`VSSCA
`VSSQ
`ZQ
`
`I/O
`
`I/O
`
`Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write
`data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS_t
`is edge-aligned to read data and centered with write data.
`
`For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and DQS1_c to the data
`on DQ8 - DQ15.
`For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data
`on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data
`on DQ24 - DQ31.
`
`Input
`
`Input
`
`Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is
`sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of
`DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c).
`For x16 and x32 devices, DM0 is the input data mask signal for the data on DQ0-7. DM1 is the input
`data mask signal for the data on DQ8-15.
`For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data
`mask signal for the data on DQ24-31.
`On-Die Termination: This signal enables and disables termination on the DRAM DQ bus according
`to the specified mode register settings.
`Supply Core Power Supply 1: Core power supply
`Supply Core Power Supply 2: Core power supply
`Supply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c input buffers.
`Supply I/O Power Supply: Power supply for Data input/output buffers.
`Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-
`9, CKE, CS_n, CK_t, and CK_c input buffers.
`Supply Reference Voltage for DQ Input Receiver: Reference voltage for all data input buffers.
`Supply Ground
`Supply Ground for Input Receivers
`Supply I/O Ground
`Reference Pin for Output Drive Strength Calibration
`I/O
`
`NOTE 1 Data includes DQ and DM.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0012
`
`

`

`JEDEC Standard No. 209-3
`Page 9
`
`3
`
`LPDDR3 Functional Description
`
`LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-bank memory.
`These devices contain the following number of bits:
`4 Gb has 4,294,967,296 bits
`8 Gb has 8,589,934,592 bits
`16 Gb has 17,179,869,184 bits
`32 Gb has 34,359,738,368 bits
`LPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of
`input pins in the system. The 10-bit CA bus contains command, address, and bank information. Each command uses
`one clock cycle, during which command information is transferred on both the positive and negative edge of the
`clock.
`These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double
`data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per
`DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR3 SDRAM effectively consists of a
`single 8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-
`half-clock-cycle data transfers at the I/O pins.
`Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and
`continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of
`an Activate command, which is then followed by a Read or Write command. The address and BA bits registered
`coincident with the Activate command are used to select the row and the bank to be accessed. The address bits
`registered coincident with the Read or Write command are used to select the bank and the starting column location for
`the burst access.
`Prior to normal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed infor-
`mation covering device initialization, register definition, command description and device operation.
`
`3.1 LPDDR3 SDRAM Addressing
`
`Table 3 — LPDDR3 SDRAM Addressing
`Items
`4Gb
`8Gb
`16Gb
`Number of Banks
`8
`8
`8
`Bank Addresses
`BA0-BA2 BA0-BA2 BA0-BA2
`3.9
`3.9
`3.9
`tREFI(us)2
`Row Addresses
`R0-R13
`R0-R14
`R0-R14
`C0-C10
`C0-C10
`C0-C11
`Column Addresses1
`Row Addresses
`R0-R13
`R0-R14
`R0-R14
`C0-C9
`C0-C9
`C0-C10
`Column Addresses1
`
`32Gb
`TBD
`TBD
`TBD
`
`TBD
`TBD
`TBD
`TBD
`
`x16
`
`x32
`
`NOTE 1 The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.
`tREFI values for all bank refresh is Tc = -25~85 C, Tc means Operating Case Temperature
`NOTE 2
`NOTE 3 Row and Column Address values on the CA bus that are not used are “don’t care.”
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0013
`
`

`

`JEDEC Standard No. 209-3
`Page 10
`
`3.2 Simplified LPDDR3 State Diagram
`
`LPDDR3-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related
`commands to control them. For a complete definition of the device behavior, the information provided by the state
`diagram should be integrated with the truth tables and timing specification.
`
`The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
`applied restrictions when considering the actual state of all the banks.
`
`For the command definition, see “LPDDR3 Command Definitions and Timing Diagrams” on page 25.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0014
`
`

`

`3.2
`
`Simplified LPDDR3 State Diagram (cont’d)
`
`JEDEC Standard No. 209-3
`Page 11
`
`Power
`Applied
`
`Resetting
`MR
`Reading
`
`Resetting
`Power
`Down
`
`Power
`On
`
`MRR
`
`PD
`PDX
`
`Reset
`
`Idle
`MR
`Reading
`
`DPDX
`
`Deep
`Power
`Down
`
`Automatic Sequence
`Command Sequence
`
`Resetting
`
`DPD
`
`Self
`Refreshing
`
`SREF
`
`SREFX
`
`Reset
`
`MRR
`
`Idle1
`
`REF
`
`Refreshing
`
`MRW
`
`MR
`Writing2
`
`PD
`
`PDX
`
`Idle
`Power
`Down
`
`ACT
`
`Active
`Power
`Down
`
`PDX
`PD
`
`WR3
`
`WR
`
`Active
`
`Writing
`
`WRA3
`
`WRA
`
`Writing
`with
`Autoprecharge
`
`PR, PRA
`
`Precharging
`
`Active
`MR
`Reading
`
`MRR
`
`PR, PRA
`
`RD
`
`RDA
`
`RD3
`
`Reading
`
`RDA3
`
`Reading
`with
`Autoprecharge
`
`ACT = Activate
`PD = Enter Power Down
`PR(A) = Precharge (All)
`PDX = Exit Power Down
`WR(A) = Write (with Autoprecharge)
`SREF = Enter Self Refresh
`RD(A) = Read (with Autoprecharge)
`SREFX = Exit Self Refresh
`MRW = Mode Register Write
`DPD = Enter Deep Power Down
`DPDX = Exit Deep Power Down
`MRR = Mode Register Read
`
`REF = Refresh
`Reset = Reset is achieved through MRW command
`Figure 1 — LPDDR3: Simplified Bus Interface State Diagram
`
`NOTE 1 In the Idle state, all banks are precharged.
`NOTE 2 In the case of MRW to enter CA Training mode or Write Leveling Mode, the state machine will not auto-
`matically return to the Idle state. In these cases an additional MRW command is required to exit either operating
`mode and return to the Idle state. See sections “CA Training” or “Write Leveling”.
`NOTE 3 Terminated bursts are not allowed. For these state transitions, the burst operation must be completed before
`the transition can occur.
`NOTE 4 Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and
`commands to control them, not all details. In particular, situations involving more than one bank are not captured in
`full detail.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2012, 0015
`
`

`

`JEDEC Standard No. 209-3
`Page 12
`
`Power-up, Initialization, and Power-off
`3.3
`3.3.1 Voltage Ramp and Device Initialization
`The following sequence must be used to power up the device. Unless specified otherwise, this procedure is
`mandatory.
`1. Voltage Ramp: While applying power (after Ta), CKE must be held LOW (0.2 × VDDCA) and all other inputs
`must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.
`Following the completion of the voltage ramp (Tb), CKE must be maintained LOW. DQ, DM, DQS_t and DQS_c
`voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA
`input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. Voltage ramp power supply
`requirements are provided in Table 4.
`
`After...
`
`Ta is reached
`
`Table 4 — Voltage Ramp Conditions
`
`Applicable Conditions
`
`VDD1 must be greater than VDD2—200mV
`VDD1 and VDD2 must be greater than VDDCA—200mV
`VDD1 and VDD2 must be greater than VDDQ—200mV
`VRef must always be less than all other supply voltages
`
`NOTE 1 Ta is the point when any power supply first reaches 300mV.
`NOTE 2 Noted conditions apply between Ta and power-off (controlled or uncontrolled).
`NOTE 3 Tb is the point at which all supply and reference voltages are within their defined operating ranges.
`NOTE 4 Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms.
`NOTE 5 The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV.
`Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The clock must
`be stable at least tINIT2 prior to the first CKE LOW-to-HIGH transition (Tc). CKE, CS_n, and CA inputs must
`observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (as well as to subsequent
`falling and rising edges).
`If any MRR commands are issued, the clock period must be within the range defined for tCKb. MRW commands can
`be issued at normal clock frequencies as long as all AC timings are met. Some AC parameters (for example, tDQSCK)
`could have relaxed timings (such as tDQSCKb) before the system is appropriately configured. While keeping CKE
`HIGH, NOP commands must be issued for at least tINIT3 (Td). The O