JEDEC
`STANDARD
`
`DDR2 SDRAM SPECIFICATION
`
`JESD79-2B
`(Revision of JESD79-2A)
`
`January 2005
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0001
`
`

`

`NOTICE
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`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0002
`
`

`

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`2500 W ilson B oulevard
`A rlington, V irginia 22201-3834
`or call (703) 907-7559
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`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0003
`
`

`

`Patent Owner Monterey Research, LLC
`Exhibit 201 1, 0004
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0004
`
`

`

`JEDEC Standard No. 79-2B
`
`Contents
`1 Package pinout & addressing.......................................................................................................... 1
`1.1 DDR2 SDRAM package ballout ...................................................................................................... 1
`1.2
`Input/output functional description .................................................................................................. 6
`1.3 DDR2 SDRAM addressing.............................................................................................................. 7
`2
` Functional description .................................................................................................................... 8
`2.1 Simplified state diagram.................................................................................................................. 8
`2.2 Basic functionality ........................................................................................................................... 9
`2.3 Power-up and initialization .............................................................................................................. 9
`2.3.1
`Power-up and initialization sequence ........................................................................................... 9
`2.4 Programming the mode and extended mode registers................................................................. 10
`2.4.1 DDR2 SDRAM mode register set (MRS).................................................................................... 10
`2.4.2 DDR2 SDRAM extended mode register set (EMRS).................................................................. 11
`2.4.3 Off-chip driver (OCD) impedance adjustment............................................................................. 14
`2.4.4 ODT (on die termination) ............................................................................................................ 16
`2.5 Bank activate command................................................................................................................ 20
`2.6 Read and write access modes...................................................................................................... 21
`Posted CAS ................................................................................................................................ 22
`2.6.1
`2.6.2
`Burst mode operation ................................................................................................................. 22
`2.6.3
`Burst read command .................................................................................................................. 23
`2.6.4
`Burst write operation................................................................................................................... 26
`2.6.5 Write data mask.......................................................................................................................... 29
`2.7 Precharge operation ..................................................................................................................... 30
`2.7.1
`Burst read operation followed by precharge ............................................................................... 31
`2.7.2
`Burst write followed by precharge............................................................................................... 33
`2.8 Auto precharge operation ............................................................................................................. 34
`2.8.1
`Burst read with auto precharge................................................................................................... 35
`2.8.2
`Burst write with auto precharge .................................................................................................. 37
`2.9 Refresh command......................................................................................................................... 38
`2.10 Self refresh operation.................................................................................................................... 39
`2.11 Power-down .................................................................................................................................. 40
`2.12 Asynchronous CKE low event........................................................................................................ 44
`2.13 Input clock frequency change during pecharge power down......................................................... 45
`2.14 No operation command................................................................................................................. 46
`2.15 Deselect command ....................................................................................................................... 46
`3 Truth tables ..................................................................................................................................... 46
`3.1 Command truth table .................................................................................................................... 46
`3.2 Clock enable truth table ................................................................................................................ 47
`3.3 Data mask truth table.................................................................................................................... 48
`4 Absolute maximum DC ratings ..................................................................................................... 48
`5 AC & DC operating conditions ...................................................................................................... 49
`Figures
`1 DDR2 SDRAM x4 ballout using MO-207............................................................................................ 1
`2 DDR2 SDRAM x8 ballout using MO-207............................................................................................ 2
`3 DDR2 SDRAM x16 ballout using MO-207.......................................................................................... 3
`4 Stacked/dual-die DDR2 SDRAM x4 ballout using MO-242................................................................ 4
`5 Stacked/dual-die DDR2 SDRAM x8 ballout using MO-242................................................................ 5
`6 DDR2 SDRAM simplified state diagram............................................................................................. 8
`7
`Initialization sequence after power up .............................................................................................. 10
`8 DDR2 SDRAM mode register set (MRS) ......................................................................................... 11
`
`-i-
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0005
`
`

`

`JEDEC Standard No. 79-2B
`
`Contents
`
`-ii-
`
`32
`
`32
`
`33
`
`Figures
`9 EMRS(1) programming .................................................................................................................... 12
`10 EMRS(2) programming .................................................................................................................... 13
`11 EMRS(3) programming: reserved .................................................................................................... 14
`12 OCD impedance adjustment ............................................................................................................ 14
`13 OCD adjust mode............................................................................................................................. 16
`14 OCD drive mode............................................................................................................................... 16
`15 Functional representation of ODT .................................................................................................... 17
`16 ODT timing for active/standby mode ................................................................................................ 17
`17 ODT timing for power-down mode ................................................................................................... 18
`18 ODT timing mode switch at entering power-down mode.................................................................. 19
`19 ODT timing mode switch at exiting power-down mode .................................................................... 20
`20 Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2............................. 21
`21 Example 1: Read followed by a write to the same bank,
`where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4 ........................... 22
`22 Example 2: Read followed by a write to the same bank,
`where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4 ........................... 22
`23 Data output (read) timing.................................................................................................................. 24
`24 Burst read operation: RL = 5 (AL = 2, CL = 3, BL = 4) ..................................................................... 24
`25 Burst read operation: RL = 3 (AL = 0 and CL = 3, BL = 8) ............................................................... 24
`26 Burst read followed by burst write: RL = 5, WL = (RL-1) = 4, BL = 4 ............................................... 25
`27 Seamless burst read Operation: RL = 5, AL = 2, and CL = 3, BL = 4 .............................................. 25
`28 Read burst interrupt timing example: (CL=3, AL=0, RL=3, BL=8).................................................... 26
`29 Data input (write) timing ................................................................................................................... 27
`30 Burst write operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4 ............................................ 27
`31 Burst write operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4 ............................................ 27
`32 Burst write followed by burst read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4...................... 28
`33 Seamless burst write operation: RL = 5, WL = 4, BL = 4 ................................................................. 28
`34 Write burst interrupt timing example: (CL=3, AL=0, RL=3, WL=2, BL=8) ........................................ 29
`35 Write data mask ............................................................................................................................... 30
`36 Example 1: Burst read operation followed by precharge:
`RL = 1, CL = 3, BL = 4, tRTP <= 2 clocks............................................................................ 31
`37 Example 2: Burst read operation followed by precharge:
`RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
`38 Example 3: Burst read operation followed by precharge:
`RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks
`39 Example 4: Burst read operation followed by precharge:
`RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks
`40 Example 5: Burst read operation followed by precharge:
`33
`RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks
`41 Example 1: Burst write followed by precharge: WL = (RL-1) =3 ...................................................... 34
`42 Example 2: Burst write followed by precharge: WL = (RL-1) = 4 ..................................................... 34
`43 Example 1: Burst read operation with auto precharge:
`RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
`44 Example 2: Burst read operation with auto precharge:
`RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks
`45 Example 3: Burst read with auto precharge
`followed by an activation to the same bank (tRC Limit):
`RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks) ................................ 36
`46 Example 4: Burst read with auto precharge
`followed by an activation to the same bank (tRP Limit):
`RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
`
`35
`
`36
`
`37
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0006
`
`

`

`JEDEC Standard No. 79-2B
`
`Contents
`
`Figures
`47 Burst write with auto-precharge (tRC Limit): WL = 2, tWR =2, BL = 4, tRP=3 ................................. 37
`48 Burst write with auto-precharge (tWR + tRP): WL = 4, tWR =2, BL = 4, tRP=3............................... 38
`49 Refresh command ............................................................................................................................ 39
`50 Self refresh operation ....................................................................................................................... 40
`51 Basic Power down entry and exit timing diagram............................................................................. 41
`52 Example 1 of CKE intensive environment ......................................................................................... 41
`53 Example 2 of CKE intensive environment ......................................................................................... 41
`54 Read to power-down entry ............................................................................................................... 42
`55 Read with autoprecharge to power down-entry................................................................................ 42
`56 Write to power-down entry ............................................................................................................... 43
`57 Write with autoprecharge to power down-entry................................................................................ 43
`58 Refresh command to power down entry........................................................................................... 44
`59 Active command to power down entry ............................................................................................. 44
`60 Precharge/precharge-all command to power-down entry ................................................................ 44
`61 MRS/EMRS command to power-down entry.................................................................................... 44
`62 Asynchronous CKE low event .......................................................................................................... 45
`63 Clock frequency change in precharge power-down mode ............................................................... 45
`64 AC input test signal waveform.......................................................................................................... 51
`65 Differential signal levels.................................................................................................................... 52
`66 AC overshoot and undershoot definition for address and control pins............................................. 53
`67 AC overshoot and undershoot definition for clock, data, strobe, and mask pins.............................. 53
`68 Output slew rate load ....................................................................................................................... 55
`69 DDR2 default pulldown characteristics for full strength driver.......................................................... 57
`70 DDR2 default pullup characteristics for full strength output driver ................................................... 58
`71 DDR2 default pulldown characteristics for reduced strength drive................................................... 59
`72 DDR2 default pullup characteristics for reduced strength driver ...................................................... 60
`73 AC timing reference load.................................................................................................................. 71
`74 Slew rate test load............................................................................................................................ 71
`75 Data input (write) timing ................................................................................................................... 72
`76 Data output (read) timing.................................................................................................................. 72
`77 Illustration of nominal slew rate for tDS (differential DQS, DQS) ...................................................... 75
`78 Illustration of nominal slew rate for tDS (single-ended DQS) ............................................................ 76
`79 Illustration of tangent line for tDS (differential DQS, DQS)................................................................ 77
`80 Illustration of tangent line for tDS (single-ended DQS) ..................................................................... 78
`81 Illustration of nominal slew rate for tDH (differential DQS, DQS) ...................................................... 79
`82 Illustration of nominal slew rate for tDH (single-ended DQS)............................................................ 80
`83 Illustration of tangent line for tDH (differential DQS, DQS)................................................................ 81
`84 Illustration of tangent line for tDH (single-ended DQS) ..................................................................... 82
`85 Illustration of nominal slew rate for tIS .............................................................................................. 85
`86 Illustration of tangent line for tIS........................................................................................................ 86
`87 Illustration of nominal slew rate for tIH .............................................................................................. 87
`88 Illustration of tangent line for tIH........................................................................................................ 88
`89 Method for calculating transitions and endpoints .............................................................................. 90
`90 Differential input waveform timing – tDS and tDH ............................................................................. 90
`91 Differential input waveform timing – tIS and tIH ................................................................................ 91
`Tables
`1 Pin descriptions................................................................................................................................... 6
`2
`256Mb addressing ............................................................................................................................. 7
`3
`512Mb addressing ............................................................................................................................. 7
`4
`1Gb addressing.................................................................................................................................. 7
`
`-iii-
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0007
`
`

`

`JEDEC Standard No. 79-2B
`
`Contents
`
`Tables
`5
`2Gb addressing.................................................................................................................................. 7
`6
`4 Gb addressing................................................................................................................................. 8
`7 OCD drive mode program................................................................................................................ 15
`8 OCD adjust mode program .............................................................................................................. 15
`9 Burst length and sequence .............................................................................................................. 23
`10 Bank selection for precharge by address bits .................................................................................. 30
`11 Precharge & auto precharge clarification.......................................................................................... 38
`12 Command truth table. ...................................................................................................................... 46
`13 Clock enable (CKE) truth table for synchronous transitions ............................................................ 47
`14 DM truth table ................................................................................................................................... 48
`15 Absolute maximum DC ratings ......................................................................................................... 49
`16 Recommended DC operating conditions (SSTL_1.8)...................................................................... 49
`17 Operating temperature condition ...................................................................................................... 49
`18 ODT DC electrical characteristics .................................................................................................... 50
`19 Input DC logic level .......................................................................................................................... 50
`20 Input AC logic level .......................................................................................................................... 51
`21 AC Input test conditions ................................................................................................................... 51
`22 Differential Input AC logic level ........................................................................................................ 51
`23 Differential AC output parameters.................................................................................................... 52
`24 AC overshoot/undershoot specification for address and control pins
`A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT .............................................................. 52
`25 AC overshoot/undershoot specification for clock, data, strobe, and mask pins
`DQ, DQS, DM, CK, CK........................................................................................................... 53
`26 Characteristics for input only pins with clamps ................................................................................ 54
`27 Output AC test conditions ................................................................................................................ 54
`28 Output DC current drive ................................................................................................................... 55
`29 OCD default characteristics ............................................................................................................ 55
`30 Full strength default pulldown driver characteristics ........................................................................ 56
`31 Full strength default pullup driver characteristics............................................................................. 58
`32 Reduced strength default pulldown driver characteristics................................................................ 59
`33 Reduced strength default pullup driver characteristics .................................................................... 60
`34 Full strength calibrated pulldown driver characteristics ................................................................... 61
`35 Full strength calibrated pullup driver characteristics ........................................................................ 61
`36 IDD specification parameters and test conditions............................................................................ 62
`37 IDD testing parameters .................................................................................................................... 64
`38 Input/output capacitance.................................................................................................................. 65
`39 Refresh parameters by device density............................................................................................. 65
`40 DDR2 SDRAM standard speed bins and tRCD, tRP and tRC for corresponding bin ...................... 66
`41 Timing parameters by speed grade (DDR2-400 and DDR2-533).................................................... 66
`42 Timing parameters by speed grade (DDR2-667 and DDR2-800).................................................... 69
`43 DQS,DQS differential slew rate ........................................................................................................ 73
`44 DQS single-ended slew rate ............................................................................................................. 73
`45 Derating values for DDR2-400, DDR2-533....................................................................................... 83
`46 Derating values for DDR2-667, DDR2-800....................................................................................... 84
`Annex A (informative)differences between JESD79-2 and JESD79-2A................................................. 92
`
`-iv-
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0008
`
`

`

`JEDEC Standard No. 79-2.B
`Page 1
`
`Variation DM-z with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`
`R T U V
`
`W
`
`1 Package pinout & addressing
`
`1.1 DDR2 SDRAM package ballout
`
`(Top view: see balls through package)
`
`3
`
`4 5
`
`6
`
`7
`
`8
`
`NC
`
`9
`
`NC
`
`1
`
`NC
`
`2
`
`NC
`
`VSSQ
`DQS
`VDDQ
`DQ2
`VSSDL
`RAS
`CAS
`A2
`A6
`A11
`NC, A15
`
`DQS
`VSSQ
`DQ0
`VSSQ
`CK
`CK
`CS
`A0
`A4
`A8
`NC, A13
`
`VDDQ
`NC
`VDDQ
`NC
`VDD
`ODT
`
`VDD
`
`VSS
`
`VDD
`NC
`VDDQ
`NC
`VDDL
`
`NC, BA2
`
`VSS
`
`VDD
`
`NC
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`DM
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`
`Variation DJ-z without support balls
`
`NC
`
`NC
`
`NC
`
`NC
`
`Variation DM-z (x4/x8)
`with support balls
`1 2 3 4
`8 9
`5 6 7
`
`ABCDEFGHJKLMNPRTU WV
`
`Populated ball
`
`Variation DJ-z (x4 x8)
`
`1 2 3 4
`
`5 6 7
`
`8 9
`
`ABCDEFGHJKL
`
`Figure 1 — DDR2 SDRAM x4 ballout using MO-207
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0009
`
`

`

`Variation DM-z with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`
`R T U V
`
`JEDEC Standard No. 79-2B
`Page 2
`1 Package pinout & addressing (cont’d)
`1.1 DDR2 SDRAM package ballout (cont’d)
`
`(Top view: see balls through package)
`
`3
`
`4 5
`
`6
`
`7
`
`1
`
`NC
`
`2
`
`NC
`
`8
`
`NC
`
`9
`
`NC
`
`DQS
`VSSQ
`VSSQ
`DQS
`DQ0
`VDDQ
`VSSQ
`DQ2
`CK
`VSSDL
`CK
`RAS
`CS
`CAS
`A0
`A2
`A4
`A6
`A8
`A11
`NC, A15 NC, A13
`
`VDDQ
`DQ7
`VDDQ
`DQ5
`VDD
`ODT
`
`VDD
`
`VSS
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`
`VDD
`DQ6
`VDDQ
`DQ4
`VDDL
`
`NC, BA2
`
`VSS
`
`VDD
`
`NU/RDQS
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`DM/RDQS
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`Variation DJ-z without support balls
`
`NC
`NC
`NOTE 1 B1, B9, D1, D9 = NC for x4 organization.
`NOTE 2 Pins B3 and A2 have identical capacitance as pins B7 and A8.
`NOTE 3 For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS
`and input masking function is disabled.
`NOTE 4 The function of DM or RDQS/RDQS is enabled by EMRS command.
`NOTE 5 VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from
`VDD, VDDQ, VSS, and VSSQ
`Variation DM-z (x4/x8)
`with support balls
`1 2 3 4
`5 6 7
`8 9
`
`NC
`
`W
`
`NC
`
`ABCDEFGHJKLMNPRTU WV
`
`Populated ball
`
`Variation DJ-z (x4 x8)
`
`1 2 3 4
`
`5 6 7
`
`8 9
`
`ABCDEFGHJKL
`
`Figure 2 — DDR2 SDRAM x8 ballout using MO-207
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0010
`
`

`

`JEDEC Standard No. 79-2B
`Page 3
`
`Variation DL-z with support balls
`
`A
`
`B C
`
`D
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`R
`T
`U
`
`V W X
`
`AA
`
`1 Package pinout & addressing (cont’d)
`1.1 DDR2 SDRAM package ballout (cont’d)
`
`(Top view: see balls through package)
`
`1
`
`NC
`
`2
`
`NC
`
`3
`
`4 5
`
`6
`
`7
`
`8
`
`NC
`
`9
`
`NC
`
`UDQS
`VSSQ
`VSSQ
`UDQS
`DQ8
`VDDQ
`VSSQ
`DQ10
`LDQS
`VSSQ
`VSSQ
`LDQS
`DQ0
`VDDQ
`VSSQ
`DQ2
`CK
`VSSDL
`CK
`RAS
`CS
`CAS
`A0
`A2
`A4
`A6
`A8
`A11
`NC, A15 NC, A13
`
`VDDQ
`DQ15
`VDDQ
`DQ13
`VDDQ
`DQ7
`VDDQ
`DQ5
`VDD
`ODT
`
`VDD
`
`VSS
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`R
`
`VDD
`DQ14
`VDDQ
`DQ12
`VDD
`DQ6
`VDDQ
`DQ4
`VDDL
`
`NC, BA2
`
`VSS
`
`VDD
`
`NC
`VSSQ
`DQ9
`VSSQ
`NC
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`UDM
`VDDQ
`DQ11
`VSS
`LDM
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`Variation DK-z without support balls
`
`NC
`
`NC
`
`NC
`
`NC
`
`NOTE VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the
`device from VDD, VDDQ, VSS, and VSSQ.
`Variation DL-z (x16)
`with support balls
`1 2 3 4
`5 6 7
`8 9
`
`Variation DK-z (x16)
`
`AV
`ABCDEFGHJKLMNPRTU WXA
`
`Populated ball
`
`1 2 3 4
`
`5 6 7
`
`8 9
`
`ABCDEFGHJKLMNPR
`
`Figure 3 — DDR2 SDRAM x16 ballout using MO-207
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0011
`
`

`

`Variation tbd. with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`
`R T U V
`
`W
`
`JEDEC Standard No. 79-2B
`Page 4
`1 Package pinout & addressing (cont’d)
`1.1 DDR2 SDRAM package ballout (cont’d)
`
`(Top view: see balls through package)
`
`3
`
`4 5
`
`6
`
`7
`
`8
`
`NC
`
`9
`
`NC
`
`1
`
`NC
`
`2
`
`NC
`
`VSSQ
`DQS
`VDDQ
`DQ2
`VSSDL
`RAS
`CAS
`A2
`A6
`A11
`NC, A15
`
`DQS
`VSSQ
`DQ0
`VSSQ
`CK
`CK
`CS0
`A0
`A4
`A8
`NC, A13
`
`VDDQ
`NC
`VDDQ
`NC
`VDD
`ODT0
`CS1
`VDD
`ODT1
`VSS
`
`VDD
`NC
`VDDQ
`NC
`VDDL
`
`NC, BA2
`CKE1
`VSS
`
`VDD
`
`NC
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE0
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`DM
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`
`Variation tbd. without support balls
`
`NC
`
`NC
`
`NC
`
`NC
`
`NOTE This stacked ballot is intended for use only in stacked packages, and does not apply to any non-stacked package. This
`document (JESD79-2) focuses on non-stacked single-die devices, except for the stacked ballout diagrams in Figures 4 and 5.
`
`Variation AD.(x4)
`with support balls
`1 2 3 4
`8 9
`5 6 7
`
`ABCDEFGHJKLMNPRTU WV
`
`Populated ball
`
`Variation AA. (x4)
`
`1 2 3 4
`
`5 6 7
`
`8 9
`
`ABCDEFGHJKL
`
`Figure 4 — Stacked/dual-die DDR2 SDRAM x4 ballout using MO-242.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2011, 0012
`
`

`

`JEDEC Standard No. 79-2B
`Page 5
`
`Variation tbd. with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M