JEDEC
`STANDARD
`
`
`
`
`
`
`Double Data Rate (DDR) SDRAM
`
`
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`
`
`JESD79F
`
`Des m arais LLP
`
`(Revision of JESD79E, May 2005)
`
`
`
`
`
`FEBRUARY 2008
`
`
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`
`
`
`
`
`
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0001
`
`

`

`NOTICE
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`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum
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`the JEDEC standards or publications.
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`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
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`
`No claims to be in conformance with this standard may be made unless all requirements stated in
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`Published by
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`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0002
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`Des m arais LLP
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`Des m arais LLP
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`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
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`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0004
`
`

`

`JESD79F
`Page 1
`
`DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
`16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks)
`32 M X4 (8 M X4 X4 banks), 16 M X8 (4 M X8 X4 banks), 8 M X16 (2 M X16 X4 banks)
`64 M X4 (16 M X4 X4 banks), 32 M X8 (8 M X8 X4 banks), 16 M X16 (4 M X16 X4 banks)
`128 M X4 (32 M X4 X4 banks), 64 M X8 (16 M X8 X4 banks), 32 M X16 (8 M X16 X4 banks)
`256 M X4 (64 M X4 X4 banks), 128 M X8 (32 M X8 X4 banks), 64 M X16 (16 M X16 X4 banks)
`FEATURES
`SDRAM during READs and by the memory controller
`during WRITEs. DQS is edge--aligned with data for
`• Double--data--rate architecture; two data transfers
`READs and center--aligned with data for WRITEs.
`per clock cycle
`The DDR SDRAM operates from a differential clock
`• Bidirectional, data strobe (DQS) is transmitted/re-
`(CK and CK; the crossing of CK going HIGH and CK
`ceived with data, to be used in capturing data at
`going LOW will be referred to as the positive edge of
`CK). Commands (address and control signals) are reg-
`the receiver
`istered at every positive edge of CK. Input data is regis-
`• DQS is edge--aligned with data for READs; cen-
`tered on both edges of DQS, and output data is refer-
`ter--aligned with data for WRITEs
`enced to both edges of DQS, as well as to both edges
`• Differential clock inputs (CK and CK)
`of CK.
`• DLL aligns DQ and DQS transitions with CK transi-
`Read and write accesses to the DDR SDRAM are
`burst oriented; accesses start at a selected location
`tions
`and continue for a programmed number of locations in
`• Commands entered on each positive CK edge;
`a programmed sequence. Accesses begin with the
`data and data mask referenced to both edges of
`registration of an ACTIVE command, which is then fol-
`DQS
`lowed by a READ or WRITE command. The address
`• Four internal banks for concurrent operation
`bits registered coincident with the ACTIVE command
`are used to select the bank and row to be accessed.
`• Data mask (DM) for write data
`The address bits registered coincident with the READ
`• Burst lengths: 2, 4, or 8
`or WRITE command are used to select the bank and
`• CAS Latency: 2 or 2.5, DDR400 also includes
`the starting column location for the burst access.
`CL = 3
`The DDR SDRAM provides for programmable read
`or write burst lengths of 2, 4 or 8 locations. An AUTO
`• AUTO PRECHARGE option for each burst access
`PRECHARGE function may be enabled to provide a
`• Auto Refresh and Self Refresh Modes
`self--timed row precharge that is initiated at the end of
`• 2.5 V (SSTL_2 compatible) I/O
`the burst access.
`• VDDQ: +2.5 V ±0.2 V for DDR 200, 266, or 333
`As with standard SDRAMs, the pipelined, multibank
`+2.6 ±0.1 V for DDR 400
`architecture of DDR SDRAMs allows for concurrent
`operation, thereby providing high effective bandwidth
`by hiding row precharge and activation time.
`An auto refresh mode is provided, along with a pow-
`er--saving, power--down mode. All inputs are compat-
`ible with the JEDEC Standard for SSTL_2. All outputs
`are SSTL_2, Class II compatible.
`Initial devices may have a VDD supply of 3.3 V (nomi-
`nal). Eventually, all devices will migrate to a VDD sup-
`ply of 2.5 V (nominal). During this initial period of prod-
`uct availability, this split will be vendor and device
`specific.
`This data sheet includes all features and functional-
`ity required for JEDEC DDR devices; options not re-
`quired, but listed, are noted as such. Certain vendors
`may elect to offer a superset of this specification by of-
`fering improved timing and/or including optional fea-
`tures. Users benefit from knowing that any system de-
`sign based on the required aspects of
`this
`specification are supported by all DDR SDRAM ven-
`dors; conversely, users seeking to use any superset
`specifications bear the responsibility to verify support
`with individual vendors.
`Note: The functionality described in, and the tim-
`ing specifications included in this data sheet are
`for the DLL Enabled mode of operation.
`
`• VDD:
`+3.3 V ±0.3 V or +2.5 V ±0.2 V for DDR 200, 266,
`or 333
`+2.6 ±0.1 V for DDR 400
`GENERAL DESCRIPTION
`The DDR SDRAM is a high--speed CMOS, dynamic
`random--access memory internally configured as a
`quad--bank DRAM. These devices contain the follow-
`ing number of bits:
`64 Mb has 67,108,864 bits
`128 Mb has 134,217,728 bits
`256 Mb has 268,435,456 bits
`512 Mb has 536,870,912 bits
`1 Gb has 1,073,741,824 bits
`The DDR SDRAM uses a double--data--rate architec-
`ture to achieve high--speed operation. The double
`data rate architecture is essentially a 2n prefetch archi-
`tecture with an interface designed to transfer two data
`words per clock cycle at the I/O pins. A single read or
`write access for the DDR SDRAM effectively consists
`of a single 2n--bit wide, one clock cycle data transfer at
`the internal DRAM core and two corresponding n--bit
`wide, one--half--clock--cycle data transfers at the I/O
`pins.
`A bidirectional data strobe (DQS) is transmitted ex-
`ternally, along with data, for use in data capture at the
`receiver. DQS is a strobe transmitted by the DDR
`Note: This specification defines the minimum set of requirements for JEDEC X4/X8/X16 DDR SDRAMs.
`Vendors will provide individual data sheets in their specific format. Vendor data sheets should be con-
`sulted for optional features or superset specifications.
`
`Des m arais LLP
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0005
`
`

`

`Fig. 27, Write To Read -- Max tDQSS,
`. . . . . . . . . . . . .
`Odd Number of Data, Interrupting
`Fig. 28, Write To Precharge -- Max tDQSS,
`Non--Interrupting
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 29, Write To Precharge -- Max tDQSS,
`Interrupting
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 30, Write To Precharge -- Max tDQSS,
`Odd Number of Data, Interrupting
`. . . . . . . . . . . . .
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Precharge
`Fig. 31, Precharge Command
`. . . . . . . . . . . . . . . . . . . . . . .
`Powerdown
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 32, Power--Down
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 33, Clock Frequency Change in Precharge
`Power--Down Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`44
`Absolute Maximum Ratings
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`45
`Table 5 -- Capacitance
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`45
`Tab. 6 -- DC Electrical Characteristics and Operating Conditions
`.
`45
`Table 7 -- AC Operating Conditions
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`46
`Table 8 -- Low Power DDR SDRAM Electrical Characteristics
`. . . .
`46
`Table 9 Idd Specifications and Conditions,
`. . . . . . . . . . . . . . . .
`47 & 48
`Fig. 34, IDD7 Measurement Timing Waveforms
`48
`. . . .
`Table 10 Low Power DDR Idd Specifications and Conditions,
`49
`Table 11 -- AC Electrical Characteristics (Timing Table),
`. . . . .
`50 & 51
`AC Timing Variations, DDR200, DDR266, DDR333, Table 12
`52
`Fig. 35, Test Reference Load
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`52
`Fig. 36, Method for Calculating Transitions and Endpoints
`53
`Component Specification Notes
`. . . . . . . . . . . . . . . . . . . . . . . . .
`52 & 53
`System Characteristics, DDR200, DDR266, & DDR333
`. . . . . . . . .
`54
`Tables 13--19Signal Derating Specifications
`. . . . . . . . . . . . . . . . . . .
`54
`Figs. 37 & 38, AC Overshoot/Undershoot Specification,
`Tables 20 & 21,
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`55
`Table 22, Clamp V--I Characteristics
`. . . . . . . . . . . . . . . . . . . . . . . . .
`56
`Fig. 39, Pullup Slew Rate Test Load
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`57
`Fig. 40, Pulldown Slew Rate Test Load
`. . . . . . . . . . . . . . . . . . . . . . .
`57
`System Characteristics Notes
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`57 & 58
`Fig. 41, Full Strength Output V--I Characteristics
`59 & 60
`. . . . . . . . . .
`Fig. 42 Weak Output V--I Characteristics
`. . . . . . . . . . . . . . . .
`61 & 62
`DDR SDRAM Output Driver V--I Characteristics
`. . . . . . . . . . . . . . . .
`63
`Timing Waveforms
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 43, Data Input Timing
`Fig. 44, Data Output Timing
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 45, Initialize and Mode Register Set
`. . . . . . . . . . . . . .
`Fig. 46, Power--Down Mode
`. . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 47, Auto Refresh Mode
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 48, Self Refresh Mode
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Reads
`. . . . . . . . . . . . . .
`69
`Fig. 49, Read -- Without Auto Precharge
`Fig. 50, Read -- Without Auto Precharge (CL=1.5, BL=4) 70
`Fig. 51, Read -- With Auto Precharge
`. . . . . . . . . . . . . . . . .
`71
`Fig. 52, Bank Read Access
`. . . . . . . . . . . . . . . . . . . . . . . . .
`72
`Writes
`. . . . . . . . . . . . . .
`Fig. 53, Write -- Without Auto Precharge
`Fig. 54, Write -- With Auto Precharge
`. . . . . . . . . . . . . . . . .
`Fig. 55, Bank Write Accesses
`. . . . . . . . . . . . . . . . . . . . . . .
`Fig. 56, Write -- DM Operation
`. . . . . . . . . . . . . . . . . . . . . . .
`
`39
`
`40
`
`41
`
`42
`43
`43
`43
`44
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`64
`64
`65
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`67
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`73
`74
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`JESD79F
`Page 2
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`
`CONTENTS
`Features
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`General Description
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Pin Assignment Diagram, TSOP2 Package
`. . . . . . . . . . . . . . . . . . . .
`Address Assignment Table 1a TSOP2 Package
`. . . . . . . . . . . . . . . . .
`Pin Assignment Diagram, BGA Package
`. . . . . . . . . . . . . . . . . . . . . . .
`Address Assignment Table 1b BGA Package
`. . . . . . . . . . . . . . . . . . .
`Functional Block Diagram -- X4/X8/X16
`. . . . . . . . . . . . . . . . . . . . . . . .
`Pin Descriptions, Table 2
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Functional Description
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Initialization
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Register Definition
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Mode Register
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Burst Length
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Table 3, Burst Definition
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 4, Mode Register Definition
`. . . . . . . . . . . . . . . . . .
`Burst Type
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Read Latency
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Operating Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Terminology Definitions
`DDR200
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`DDR266
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`DDR333
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`DDR400
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`Fig. 5, Required CAS Latencies
`. . . . . . . . . . . . . . . . .
`10
`Extended Mode Register
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`11
`DLL Enable/Disable
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`11
`Output Drive Strength
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`11
`Fig.6, Extended Mode Register Definitions
`. . . . . . . . .
`11
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Commands
`12
`Truth Table 1a (Commands)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`12
`Truth Table 1b (DM Operation)
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`12
`Truth Table 2 (CKE)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`13
`Truth Table 3 (Current State, Same Bank)
`. . . . . . . . . . . . .
`14 & 15
`Truth Table 4 (Current State, Different Bank)
`16 & 17
`. . . . . . . . . .
`Fig. 7, Simplified State Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . .
`18
`Command definitions
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`19 & 20
`DESELECT
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`19
`NO OPERATION (NOP)
`19
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`MODE REGISTER SET
`19
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`ACTIVE
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`19
`READ
`19
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`WRITE
`19
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`BURST TERMINATE
`19
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`PRECHARGE
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`20
`AUTO PRECHARGE
`20
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`REFRESH REQUIREMENTS
`20
`. . . . . . . . . . . . . . . . . . . . . . .
`AUTO REFRESH
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`20
`SELF REFRESH
`20
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Table 4, Row--Column Organization by Density
`19
`. . . . . . . . . . . .
`Operations
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`21
`Bank/Row Activation
`21
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 8, Activating a Specific Row
`21
`. . . . . . . . . . . . . . . . . . . . .
`Fig. 9, tRCD & tRRD Definition
`. . . . . . . . . . . . . . . . . . . . . .
`21
`Reads
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`22 & 23
`Fig. 10, Read Command
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`22
`Fig. 11, Read Burst
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`24
`Fig. 12, Consecutive Read Bursts
`25
`. . . . . . . . . . . . . . . . . . .
`Fig. 13, Nonconsecutive Read Bursts
`26
`. . . . . . . . . . . . . . . .
`Fig. 14, Random Read Accesses
`. . . . . . . . . . . . . . . . . . . .
`27
`Fig. 15, Terminating a Read Burst
`28
`. . . . . . . . . . . . . . . . . . .
`Fig. 16, Read to Write
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`29
`Fig. 17, Read to Precharge
`30
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Writes
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`31
`Fig. 18, Write Command
`31
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 19, Write to Write--Max tDQSS
`32
`. . . . . . . . . . . . . . . . . .
`Fig. 20, Write to Write--Min tDQSS
`32
`. . . . . . . . . . . . . . . . . . .
`Fig. 21, Write Burst -- Nom., Min., and Max tDQSS
`33
`Fig. 22, Write To Write -- Max tDQSS
`. . . . . . . . . . . . . . . . .
`34
`Fig. 23, Write To Write -- Max tDQSS, Non Consecutive
`35
`.
`Fig. 24, Random Write Cycles -- Max tDQSS
`. . . . . . . . . .
`36
`Fig. 25, Write To Read -- Max tDQSS, Non--Interrupting
`37
`.
`Fig. 26, Write To Read -- Max tDQSS, Interrupting
`. . . . . .
`38
`
`Des m arais LLP
`
`Annex A (Informational) Differences Between 79D and 79C
`
`. . . . . .
`
`77
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0006
`
`

`

`JESD79F
`Page 3
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`Bank Addr
`
`BA0, BA1
`BA0, BA1
`BA0, BA1
`
`BA0, BA1
`BA0, BA1
`BA0, BA1
`
`X16 DDR SDRAM
`X8 DDR SDRAM
`
`X4 DDR SDRAM
`
`66
`
`65
`
`64
`
`63
`
`62
`
`61
`
`60
`
`59
`
`58
`
`57
`
`56
`
`55
`
`54
`
`53
`
`VSS
`
`NC
`
`DQ7 DQ15
`
`VSSQ
`
`NC
`
`NC DQ14
`
`DQ3
`
`DQ6 DQ13
`
`VDDQ
`
`NC
`
`NC
`
`NC DQ12
`
`DQ5 DQ11
`
`VSSQ
`
`NC
`
`NC DQ10
`
`DQ2
`
`DQ4 DQ9
`
`VDDQ
`
`NC
`
`NC
`
`NC DQ8
`
`Density Org.
`
`64 Mb 16M X 4
`8M X 8
`4M X 16
`
`128 Mb 32M X 4
`16M X 8
`8M X 16
`
`256 Mb 64M X 4
`32M X 8
`16M X 16
`
`4
`4
`4
`
`4
`4
`4
`
`4
`4
`4
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`
`11
`
`12
`
`13
`
`14
`
`VDD
`
`DQ0
`
`NC
`
`VDDQ
`
`DQ1
`
`NC
`
`NC
`
`DQ2
`
`DQ1
`
`DQ0
`
`VSSQ
`
`DQ3
`
`NC
`
`DQ4
`
`DQ2
`
`NC
`
`NC
`
`VDDQ
`
`DQ5
`
`NC
`
`NC
`
`DQ6
`
`DQ3
`
`DQ1
`
`DQ7
`
`NC
`
`VSSQ
`
`NC
`
`NC
`
`ADDRESS ASSIGNMENT TABLE
`Bank Row Addr.
`Col Addr
`A0⇒A11
`A0⇒A9
`A0⇒A11
`A0⇒A8
`A0⇒A11
`A0⇒A7
`A0⇒A11
`A0⇒A9, A11
`A0⇒A11
`A0⇒A9
`A0⇒A11
`A0⇒A8
`BA0, BA1
`A0⇒A12
`A0⇒A9, A11
`BA0, BA1
`A0⇒A12
`A0⇒A9
`BA0, BA1
`A0⇒A12
`A0⇒A8
`A0⇒A12 A0⇒A9,A11,A12 BA0, BA1
`BA0, BA1
`A0⇒A12
`A0⇒A9, A11
`A0⇒A12
`A0⇒A9
`BA0, BA1
`256M X 4
`4
`A0⇒A13 A0⇒A9,A11,A12 BA0, BA1
`128M X 8
`4
`BA0, BA1
`A0⇒A13
`A0⇒A9,A11
`64M X 16
`4
`A0⇒A13
`A0⇒A9
`BA0, BA1
`TABLE 1a: TSOP2 Device Address
`Assignment Table
`
`512 Mb 128M X 4
`64M X 8
`32M X 16
`
`4
`4
`4
`
`Des m arais LLP
`
`66 PIN
`TSOP2
`MS--024FC
`&
`LSOJ
`MO--199
`&
`MO--200
`
`10.16 mm
`PIN PITCH
`0.65 mm
`
`52
`
`51
`
`50
`
`49
`
`48
`
`47
`
`46
`
`45
`
`TOP VIEW
`
`44
`
`43
`
`42
`
`41
`
`40
`
`39
`
`38
`
`37
`
`36
`
`35
`
`34
`
`LDQS
`
`LDM
`
`VDDQ
`
`NC
`NC,
`A13
`VDD
`
`NU
`
`NC
`
`WE
`
`CAS
`
`RAS
`
`CS0,
`NC
`CS1,
`NC
`BA0
`
`BA1
`A10
`/AP
`A0
`
`A1
`
`A2
`
`A3
`
`VDD
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`UDQS
`
`UDM
`
`VSSQ
`
`DQS
`
`NC
`
`VREF
`
`VSS
`
`DM
`
`CK
`
`CK
`CKE0,
`NC
`CKE1,
`NC
`NC,
`A12
`A11
`
`A9
`
`A8
`
`A7
`
`A6
`
`A5
`
`A4
`
`VSS
`
`1 Gb
`
`The following pin assignments apply
`for CS and CKE pins for Stacked
`and Non--stacked devices.
`Pin
`Non--
`Stacked
`Stacked
`CS
`NC
`NC
`CKE
`
`CS0
`CS1
`CKE1
`CKE0
`
`24
`25
`43
`44
`
`Figure 1
`64 Mb Through 1Gb DDR SDRAM (X4, X8, & X16) IN TSOP2 & LSOJ
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0007
`
`

`

`JESD79F
`Page 4
`
`(x4)
`
`1
`
`2
`
`3
`
`7
`
`8
`
`9
`
`(x8)
`
`1
`
`2
`
`3
`
`7
`
`8
`
`9
`
`VSSQ
`
`NC
`
`VSS
`
`VDD
`
`NC
`
`VDDQ
`
`VSSQ DQ7
`
`VSS
`
`VDD
`
`DQ0
`
`VDDQ
`
`NC
`
`NC
`
`VDDQ DQ3
`
`DQ0
`
`VSSQ
`
`VSSQ
`
`NC
`
`NC
`
`VDDQ
`
`DQ1 VSSQ
`
`NC
`
`NC
`
`NC
`
`NC
`
`NC
`
`VDDQ DQ6
`
`DQ1
`
`VSSQ
`
`VSSQ
`
`DQ5
`
`DQ2
`
`VDDQ
`
`DQ3 VSSQ
`
`NC
`
`NC
`
`NC
`
`VDDQ
`
`NC
`
`NC
`
`NC
`
`VDDQ
`
`DQ4
`
`VSSQ DQS
`
`VDD
`
`A13,NC
`
`VREF
`
`NC
`
`NC
`
`VREF
`
`VDDQ
`
`DQ2
`
`VSSQ DQS
`
`VSS
`
`CK
`
`DM
`
`CK
`
`A12,NC
`
`CKE
`
`A11
`
`A9
`
`NC
`
`NC
`
`WE
`
`CAS
`
`RAS
`
`CS
`
`BA0
`
`VSS
`
`CK
`
`DM
`
`CK
`
`A12,NC
`
`CKE
`
`NC
`
`NC
`
`VDDQ
`
`NC
`
`VDD
`
`A13,NC
`
`WE
`
`CAS
`
`RAS
`
`CS
`
`A11
`
`A9
`
`BA1
`
`BA0
`
`A0
`
`A2
`
`VDD
`
`A10/AP
`
`A1
`
`A3
`
`A B C D E F G H J K L M
`
`BA1
`
`A0
`
`A2
`
`VDD
`
`A10/AP
`
`A1
`
`A3
`
`A8
`
`A6
`
`A4
`
`A7
`
`A5
`
`VSS
`
`A B C D E F G H J K L M
`
`A8
`
`A6
`
`A4
`
`A7
`
`A5
`
`VSS
`
`X4 Device Ball Pattern
`
`X8 Device Ball Pattern
`
`(x16)
`
`1
`
`2
`
`3
`
`7
`
`8
`
`9
`
`: Ball Existing
`: Depopulated Ball
`
`[For Reference Only]
`
`VSSQ DQ15
`
`VSS
`
`VDD
`
`DQ0
`
`VDDQ
`
`Top View(See the balls through the Package)
`
`DQ14 VDDQ DQ13
`
`DQ2
`
`VSSQ
`
`DQ1
`
`1 2 3 4 5 67 8 9
`
`VSSQ
`
`DQ11
`
`DQ4
`
`Des m arais LLP
`
`1.0 mm
`
`max. 18 mm
`max. 17 mm
`for Micro DIMM
`
`A B C D E F G H J K L M
`
`VDDQ
`
`DQ3
`
`DQ6 VSSQ DQ5
`
`LDQS
`
`VDDQ
`
`DQ7
`
`LDM VDD
`
`A13,NC
`
`WE
`
`CAS
`
`RAS
`
`CS
`
`BA1
`
`BA0
`
`A0
`
`A2
`
`VDD
`
`A10/AP
`
`A1
`
`A3
`
`A B C D E F G H J K L M
`
`DQ12
`
`DQ10
`
`VDDQ
`
`DQ9
`
`DQ8
`
`VSSQ UDQS
`
`VREF
`
`VSS
`
`UDM
`
`CK
`
`CK
`
`A12,NC
`
`CKE
`
`A11
`
`A8
`
`A6
`
`A4
`
`A9
`
`A7
`
`A5
`
`VSS
`
`X16 Device Ball Pattern
`
`0.8 mm
`
`max. 10 mm
`max. 8.5 mm
`for Micro DIMM
`BGA Package Ball Pattern,
`Top View
`
`Figure 2
`128 Mb Through 1Gb DDR SDRAM (X4, X8, & X16) IN BGA
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0008
`
`

`

`JESD79F
`Page 5
`
`Note
`
`128Mb
`4
`BA0, BA1
`A10/AP
`A0-A11
`A0-A9,A11
`A0-A9
`A0-A8
`NC
`NC
`MO-233A
`AA
`DSBGA
`
`256Mb
`4
`BA0, BA1
`A10/AP
`A0-A12
`A0-A9,A11
`A0-A9
`A0-A8
`A12
`NC
`MO-233A
`AA
`DSBGA
`
`512Mb
`4
`BA0, BA1
`A10/AP
`A0-A12
`A0-A9,A11,A12
`A0-A9,A11
`A0-A9
`A12
`NC
`MO-233A
`AA
`DSBGA
`
`1Gb
`4
`BA0, BA1
`A10/AP
`A0-A13
`A0-A9,A11,A12
`A0-A9,A11
`A0-A9
`A12
`A13
`MO-233A
`AA
`DSBGA
`
`Item
`Number of banks
`Bank Address Pins
`Autoprecharge Pins
`Row Addresses
`Column Addresses x4
`x8
`x16
`H2 pin function
`F13 pin function
`JC11 MO #
`JC11 Variation #
`JC11 Package
`Name
`Pin Pitch
`
`0.8 mm x 1.0
`0.8 mm x 1.0
`0.8 mm x 1.0
`0.8 mm x 1.0
`mm
`mm
`mm
`mm
`TABLE 1b: BGA Device Address Assignment and Package Table
`
`BANK3
`
`BANK2
`
`BANK1
`
`X4
`8
`4
`
`X8
`16
`8
`
`X16
`32
`16
`
`X
`Y
`
`Des m arais LLP
`
`14
`
`BANK0
`ROW--
`ADDRESS
`LATCH
`&
`DECODER
`
`16384
`
`BANK0
`MEMORY
`ARRAY
`
`SENSE AMPLIFIERS
`
`I/O GATING
`DM MASK LOGIC
`
`X
`
`BANK
`CONTROL
`LOGIC
`
`X
`
`READ
`LATCH
`
`Y
`
`Y
`
`X
`
`WRITE
`FIFO
`&
`DRIVERS
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`CKEn
`
`CK
`CK
`
`CSn
`
`WE
`
`CAS
`RAS
`
`MODE REGISTERS
`
`REFRESH
`COUNTER
`
`14
`
`16
`
`14
`
`ROW--
`ADDRESS
`MUX
`
`2
`
`A0--A13,
`BA0, BA1
`
`16
`
`ADDRESS
`REGISTER
`
`2
`
`12
`
`DQ0 --
`DQn, DM
`
`DQS
`
`CLK
`
`DATA
`
`DLL
`
`Y
`
`DQS
`GENERATOR
`
`1
`
`INPUT
`REGISTERS
`
`DRVRS
`
`DQS
`
`RCVRS
`
`1
`
`Y
`
`1 1
`
`Y Y
`
`1 1
`
`Y Y
`
`MUX
`
`COL0
`
`MASK
`
`2
`
`X
`
`COLUMN
`DECODER
`
`CK
`out
`
`CK
`in
`
`DATA
`
`COLUMN--
`ADDRESS
`COUNTER/
`LATCH
`
`11
`
`1
`
`COL0
`
`CK
`
`COL0
`
`1
`
`Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
`not represent an actual circuit implementation.
`Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and DQS signals.
`Note 3: Not all address inputs are used on all densities.
`
`FIGURE 3: FUNCTIONAL BLOCK DIAGRAM OF DDR SDRAM
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0009
`
`

`

`JESD79F
`Page 6
`
`Input
`
`CKE
`
`(CKE0)
`(CKE1)
`
`TABLE 2: PIN DESCRIPTIONS
`SYMBOL
`TYPE
`DESCRIPTION
`CK, CK
`Input
`Clock: CK and CK are differential clock inputs. All address and control input signals
`are sampled on the crossing of the positive edge of CK and negative edge of CK.
`Output (read) data is referenced to the crossings of CK and CK (both directions of
`crossing).
`Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-
`nals, and device input buffers and output drivers. Taking CKE LOW provides PRE-
`CHARGE POWER--DOWN and SELF REFRESH operation (all banks idle), or AC-
`TIVE POWER--DOWN (row ACTIVE in any bank). CKE is synchronous for POW-
`ER--DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for
`SELF REFRESH exit, and for output disable. CKE must be maintained high
`throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE
`are disabled during POWER--DOWN. Input buffers, excluding CKE are disabled
`during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
`level after Vdd is applied upon 1st power up. After VREF has become stable during
`the power on and initialization sequence, it must be maintained for proper operation
`of the CKE receiver. For proper self--refresh entry and exit, VREF must be main-
`tained to this input The standard pinout includes one CKE pin. Optional pinouts in-
`clude CKE0 and CKE1 on different pins, to facilitate device stacking.
`Chip Select: All commands are masked when CS is registered high. CS provides
`for external bank selection on systems with multiple banks. CS is considered part of
`the command code. The standard pinout includes one CS pin. Optional pinouts
`include CS0 and CS1 on different pins, to facilitate device stacking.
`Command Inputs: RAS, CAS and WE (along with CS) define the command being
`entered.
`Input Data Mask: DM is an input mask signal for write data. Input data is masked
`when DM is sampled HIGH along with that input data during a WRITE access. DM
`is sampled on both edges of DQS. Although DM pins are input only, the DM loading
`matches the DQ and DQS loading. For the X16, LDM corresponds to the data on
`DQ0--DQ7; UDM corresponds to the data on DQ8--DQ15. DM may be driven high,
`low, or floating during READs.
`Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
`WRITE or PRECHARGE command is being applied.
`Address Inputs: Provide the row address for ACTIVE commands, and the column
`address and AUTO PRECHARGE bit for READ/WRITE commands, to select one
`location out of the memory array in the respective bank. A10 is sampled during a
`precharge command to determine whether the PRECHARGE applies to one bank
`(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank
`is selected by BA0, BA1. The address inputs also provide the op--code during a
`MODE REGISTER SET command. BA0 and BA1 define which mode register is
`loaded during the MODE REGISTER SET command (MRS or EMRS). A12 is used
`on device densities of 256Mb and above; A13 is used on device densities of 1Gb.
`Data Bus: Input/Output.
`Data Strobe: Output with read data, input with write data. Edge--aligned with read
`data, centered in write data. Used to capture write data. For the X16, LDQS corre-
`sponds to the data on DQ0--DQ7; UDQS corresponds to the data on DQ8--DQ15.
`No Connect: No internal electrical connection is present.
`DQ Power Supply: +2.5 V ±0.2 V. for DDR 200, 266, or 333
`. . . . . . . . . . . . . . . .
`+2.6 ±0.1 V for DDR 400
`DQ Ground.
`Power Supply: One of +3.3 V ±0.3 V or +2.5 V ±0.2 V for DDR 200, 266, or 333
`. . . . . . . . . . . .
`+2.6 ±0.1 V for DDR 400
`Supply Ground.
`Input
`SSTL_2 reference voltage.
`
`Des m arais LLP
`
`CS
`(CS0)
`(CS1)
`
`RAS, CAS,
`WE
`DM
`(LDM)
`(UDM)
`
`Input
`
`Input
`
`Input
`
`BA0, BA1
`
`Input
`
`A0--A13
`
`Input
`
`I/O
`I/O
`
`—
`Supply
`
`Supply
`Supply
`
`DQ
`DQS
`(LDQS)
`(UDQS)
`NC
`VDDQ
`
`VSSQ
`VDD
`
`VSS
`VREF
`
`Downloaded by Jamell Watson (JWatson@desmaraisllp.com) on Feb 9, 2021, 1:52 pm PST
`
`Patent Owner Monterey Research, LLC
`Exhibit 2010, 0010
`
`

`

`FUNCTIONAL DESCRIPTION
`The DDR SDRAM is a high--speed CMOS, dy-
`namic random--access memory internally config-
`ured as a quad--bank DRAM. These devices con-
`tain the following number of bits:
`64Mb has 67,108,864 bits
`128Mb has 134,217,728 bits
`256Mb has 268,435,456 bits
`512Mb has 536,870,912 bits
`1Gb has 1,073,741,824 bits
`The DDR SDRAM uses a double--data--rate archi-
`tecture to achieve high--speed operation. The
`double--data--rate architecture is essentially a 2n
`prefetch architecture, with an interface designed to
`transfer two data words per clock cycle at the I/O
`pins. A single read or write access for the DDR
`SDRAM consists of a single 2n--bit wide, one clock
`cycle data transfer at the internal DRAM core and
`two corresponding n--bit wide, one--half clock cycle
`data transfers at the I/O pins. DQ, DQS, & DM may
`be floated when no data is being transferred
`Read and write accesses to the DDR SDRAM are
`burst oriented; accesses start at a selected location
`and continue for a programmed number of locations
`in a programmed sequence. Accesses begin with
`the registration of an ACTIVE command, which is
`then followed by a READ or WRITE command. The
`address bits registered coincident with the ACTIVE
`command are used to select the bank and row to be
`accessed (BA0, BA1 select the bank; A0--A13 se-
`lect the row). The address bits registered coincident
`with the READ or WRITE command are used to se-
`lect the starting column location for the burst ac-
`cess.
`Prior to normal operation, the DDR SDRAM must
`be initialized. The following sections provide de-
`tailed information covering device initialization, reg-
`ister definition, command descriptions and device
`operation.
`INITIALIZATION
`DDR SDRAMs must be powered up and initialized
`in a predefined manner. Operational procedures
`other than those specified may result in undefined
`operation. No power sequencing is specified during
`power up and power down given the following crite-
`ria:
`D VDD and VDDQ are driven from a single power
`converter output, AND
`D VTT is limited to 1.35 V, AND
`D VREF tracks VDDQ/2
`
`Des m arais LLP
`
`JESD79F
`Page 7
`
`At least one of these two conditions must be met.
`
`Except for CKE, inputs are not recognized as valid
`until after VREF is applied. CKE is an SSTL_2 input,
`but will detect an LVCMOS LOW level after VDD is
`applied. Maintaining an LVCMOS LOW level on
`CKE during power--up is required to guarantee that
`the DQ and DQS outputs will be in the High--Z state,
`where they will remain until driven in normal opera-
`tion (by a read access). After all power supply and
`reference voltages are stable, and the clock is
`stable, the DDR SDRAM requires a 200 μs delay
`prior to applying an executable command.
`Once the 200 μs delay has been satisfied, a DE-
`SELECT or NOP command should be applied, and
`CKE should be brought HIGH. Following the NOP
`command, a PRECHARGE ALL command should
`be applied. Next a MODE REGISTER SET com-
`mand should be issued for the Extended Mode Reg-
`ister, to enable the DLL, then a MODE REGISTER
`SET command should be issued for the Mode Reg-
`ister, to reset the DLL, and to program the operating
`parameters. 200 clock cycles are required between
`the DLL reset and any executable command. A
`PRECHARGE ALL command should be applied,
`placing the device in the ”all banks idle” state.
`Once in the idle state, two AUTO refresh cycles
`must be performed. Additionally, a MODE REG-
`ISTER SET command for the Mode Register, with
`the reset DLL bit deactivated (i.e., to program oper-
`ating parameters without resetting the DLL) must
`be performed. Following these cycles, the DDR
`SDRAM is ready for normal operation.
`REGISTER DEFINITION
`MODE REGISTER
`The Mode Register is used to define the specific
`mode of operation of the DDR SDRAM. This defini-
`tion includes the selection of a burst length, a burst
`type, a CAS latency, and an operating mode, as
`shown in Figure NO TAG. The Mode Register is
`programmed via the MODE REGISTER SET com-
`mand (with BA0 = 0 and BA1 = 0) and will retain the
`stored information until it is programmed again or
`the device loses power (except for bit A8, which
`may be self--clearing).
`Mode Register bits A0--A2 specify the burst
`length, A3 specifies the type of burst (sequential or
`interleaved), A4--A6 specify the CAS latency, and
`A7--A13 or (A12 on 256Mb/512Mb