DRAM
`
`CIRCUIT DESIGN
`
`Fundamental and High-Speed Topics
`
` eSAN
`
`SNe
`
`Brent Keeth - R. Jacob Baker
`Brian Johnson - Feng Lin
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0001
`
`

`

`DRAM Circuit Design
`DRAM Circuit Design
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0002
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0002
`
`

`

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`

`

`DRAM Circuit Design
`Fundamental and High-Speed Topics
`
`Brent Keeth
`R. Jacob Baker
`Brian Johnson
`Feng Lin
`
`IEEE Press Series on Microelectronic Systems
`Stuart K. Tewksbury and Joe E. Brewer, Series Editors
`
`IEEE Solid-State Circuits Society, Sponsor
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`+IEEE
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`IEEE PRESS
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`BICENTENNIAL
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`c
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`i1807~
`z
`z
`~ Gi)WILEY:
`z
`z
`~2007~
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`~
`•
`r
`BICENTENNIAL
`
`WILEY-INTERSCIENCE
`A John Wiley & Sons, Inc., Publication
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`Patent Owner Monterey Research, LLC
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`Copyright © 2008 by the Institute of Electrical and Electronic Engineers, Inc. All rights reserved.
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`Patent Owner Monterey Research, LLC
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`

`

`To Susi, John, Katie, Gracie, Dory, and Faith (B.K.)
`To Julie, Kyri, and Josh (J.B.)
`To Cassandra, Parker, Spencer, and Dolpha (B.J.)
`To Hui, Luan, and Conrad (F.L.)
`To Leah and Nicholas (MM.)
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0006
`
`

`

`Contents
`
`Preface .................................................. x1
`
`Chapter 1 An Introduction to DRAM
`1.1 DRAM Types and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`1.1.1 The lk DRAM (First Generation) .................... 1
`1.1.2 The 4k-64 Meg DRAM (Second Generation) ........... 7
`1.1.3 Synchronous DRAM (Third Generation) .............. 15
`1.2 DRAM Basics ....................................... 22
`1.2. I Access and Sense Operations ....................... 24
`1.2.2 Write Operation ................................. 28
`1.2.3 Opening a Row (Summary) ........................ 29
`1.2.4 Open/Folded DRAM Array Architectures ............. 31
`
`Chapter 2 The DRAM Array
`2.1 The Mbit Cell ........................................ 33
`2.2 The Sense Amp ...................................... 44
`2.2.1 Equilibration and Bias Circuits ..................... 44
`2.2.2 Isolation Devices ................................ 46
`2.2.3 Input/Output Transistors .......................... 46
`2.2.4 Nsense and Psense Amplifiers ...................... 4 7
`2.2.5 Rate of Activation ............................... 49
`2.2.6 Configurations .................................. 49
`2.2. 7 Operation ...................................... 52
`2.3 Row Decoder Elements ................................ 54
`2.3.1 Bootstrap Wordline Driver. ........................ 55
`2.3.2 NOR Driver .................................... 57
`2.3.3 CMOS Driver ................................... 58
`
`vii
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`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0007
`
`

`

`viii
`
`Contents
`
`2.3.4 Address Decode Tree ............................ 58
`2.3.5 Static Tree ..................................... 59
`2.3.6 P&E Tree ...................................... 59
`2.3.7 Predecoding .................................... 60
`2.3.8 Pass Transistor Tree ............................. 61
`2.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`
`Chapter 3 Array Architectures
`3.1 Array Architectures ................................... 65
`3.1.1 Open Digitline Array Architecture .................. 65
`3.1.2 Folded Array Architecture ......................... 75
`3.2 Design Examples: Advanced Bilevel DRAM Architecture .... 83
`3.2.1 Array Architecture Objectives ...................... 84
`3.2.2 Bilevel Digitline Construction ...................... 85
`3.2.3 Bilevel Digitline Array Architecture ................. 88
`3.2.4 Architectural Comparison ......................... 93
`
`Chapter 4 The Peripheral Circuitry
`4.1 Column Decoder Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
`4.2 Column and Row Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . I 02
`4.2.1 Row Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 04
`4.2.2 Column Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 07
`
`Chapter 5 Global Circuitry and Considerations
`5.1 Data Path Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
`5.1.1 Data Input Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
`5.1.2 Data Write Muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
`5.1.3 Write Driver Circuit ............................ 116
`5.1.4 Data Read Path ................................ 118
`5.1.5 DC Sense Amplifier (DCSA) . . . . . . . . . . . . . . . . . . . . . 119
`5.1.6 Helper Flip-Flop (HFF). . .. . . . . . . . . . . . . .. . . . . . . . . 121
`5.1. 7 Data Read Muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J 22
`5.1.8 Output Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
`5.1.9 Test Modes ................................... 125
`5.2 Address Path Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
`5.2.1 Row Address Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
`5.2.2 Row Address Buffer ............................ 127
`5.2.3 CBR Counter .................................. 127
`5.2.4 Predecode Logic ............................... 128
`5.2.5 Refresh Rate .................................. 128
`5.2.6 Array Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
`5.2. 7 Phase Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J 31
`
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`Exhibit 2007, 0008
`
`

`

`Contents
`
`ix
`
`5.2.8 Column Address Path ............................ 131
`5.2.9 Address Transition Detection ...................... 132
`5.3 Synchronization in DRAMs ........................... 135
`5.3.1 The Phase Detector ............................. 137
`5.3.2 The Basic Delay Element ......................... 137
`5.3.3 Control of the Shift Register ...................... 138
`5.3.4 Phase Detector Operation ......................... 139
`5.3.5 Experimental Results ............................ 140
`5.3.6 Discussion .................................... 142
`
`Chapter 6 Voltage Converters
`6.1 Internal Voltage Regulators ............................ 147
`6.1.1 Voltage Converters .............................. 14 7
`6.1.2 Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
`6.1.3 Bandgap Reference ............................. 153
`6.1.4 The Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
`6.2 Pumps and Generators ................................ 158
`6.2.1 Pumps ........................................ 158
`6.2.2 DVC2 Generator ............................... 165
`6.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
`
`Chapter 7 An Introduction to High-Speed DRAM
`7.1 The Performance Paradigm ............................ 167
`7.2 Performance for DRAM Memory Devices ................ 169
`7.3 Underlying Technology Improvements ................... 171
`
`Chapter 8 High-Speed Die Architectures
`8.1 Introduction: Optimizing DRAM Architecture for High Perfor-
`mance ............................................ 173
`8.2 Architectural Features: Bandwidth, Latency, and Cycle Time. 175
`8.2.1 Architectural Limiters: The Array Data Path .......... 176
`8.2.2 Architectural Limiters: The Read Data Path .......... 183
`8.2.3 Architectural Limiters: Latency .................... 186
`8.3 Conclusion: Designing for High Performance ............. 190
`
`Chapter 9 Input Circuit Paths
`9.1 Introduction ........................................ 193
`9.2 Input Receivers ..................................... 196
`9.3 Matched Routing .................................... 200
`9.4 Capture Latches ..................................... 203
`9.5 Input Timing Adjustments ............................. 206
`9.6 Current Mode Logic (CML) ........................... 212
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0009
`
`

`

`x
`
`Contents
`
`Chapter 10 Output Circuit Paths
`I 0.1 Transmission Line, Impedance, and Tennination .......... 220
`I 0.2 Impedance Control ................................. 224
`I 0.3 Simultaneous Switching Noise (SSN) .................. 230
`10.4 Signal Return Path Shift (SRPS) ....................... 238
`I 0.5 Electrostatic Discharge (ESD) ........................ 242
`I 0.6 Parallel-to-Serial Conversion ......................... 244
`I 0. 7 Emerging Memory J/0 Features ....................... 248
`
`Chapter 11 Timing Circuits
`11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
`11.2 All-Digital Clock Synchronization Design ............... 254
`11.2.1 Timing Analysis .............................. 255
`11.2.2 Digital Delay Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
`11.2.3 Phase Detector (PD) ........................... 267
`11.2.4 Test and Debug ............................... 273
`11.2.5 Dual-Loop Architecture ........................ 274
`11.3 Mixed-Mode Clock Synchronization Design ............. 275
`11.3.1 Analog Delay Line ............................ 276
`11.3.2 Charge-Pump Phase Detector (CPPD) ............. 283
`11.3.3 Dual-Loop Analog DLL ........................ 286
`11.3.4 Mixed-Mode DLL and Its Applications ............ 289
`11.4 What's Next for Timing ............................. 291
`
`Chapter 12 Control Logic Design
`12. l Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
`12.2 DRAM Logic Styles ................................ 298
`12.2. l Process Limitations ............................ 298
`12.2.2 Array Operation ............................... 301
`12.2.3 Perfonnance Requirements ...................... 304
`12.2.4 Delay-Chain Logic Sty le. . . . . . . . . . . . . . . . . . . . . . . . 306
`12.2.5 Domino Logic ................................ 309
`12.2.6 Testability ................................... 314
`12.3 Command and Address Control . . . . . . . . . . . . . . . . . . . . . . . 317
`12.3.l Command Decoder ............................ 318
`12.3.2 Read and Write Data Address Registers ............ 324
`12.3.3 Column Access Control. ........................ 328
`12.4 Write Data Latency Timing and Data Demultiplexing ...... 330
`12.4.1 Write Latency Timing .......................... 332
`12.4.2 Write Data Demultiplexing ...................... 338
`12.5 Read Data Latency Timing and Data Multiplexing ........ 346
`12.5.1 Read Data FIFO ............................... 350
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0010
`
`

`

`Contents
`
`xi
`
`12.5.2 Read Latency (CL) Tracking ..................... 359
`12.6 Comments on Future Direction for DRAM Logic Design ... 367
`
`Chapter 13 Power Delivery
`13.1 Power Delivery Network Design ....................... 373
`13.2 Device/Package Co-design ........................... 376
`13.3 Full-Chip Simulations ............................... 380
`
`Chapter 14 Future Work in High-Performance Memory .... 385
`
`Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
`
`Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
`
`Index .............................................. 413
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0011
`
`

`

`Preface
`
`From the core memory that rocketed into space during the Apollo moon
`missions to the solid-state memories used in today's commonplace com(cid:173)
`puter, memory technology has played an important, albeit quiet, role during
`the prior and current centuries. It has been quiet in the sense that memory,
`although necessary, is not glamorous and sexy, and is instead being rele(cid:173)
`gated to the role of a commodity. Yet, it is important because memory tech(cid:173)
`nology, specifically, CMOS DRAM technology, has been one of the
`greatest driving forces in the advancement of solid-state technology. It
`remains a driving force today, despite the segmentation in its market space.
`The very nature of the commodity memory market, with high product
`volumes and low pricing, is what ultimately drives the technology. To sur(cid:173)
`vive, let alone remain viable over the long term, memory manufacturers
`work aggressively to drive down their manufacturing costs while maintain(cid:173)
`ing, if not increasing, their share of the market. One of the best tools to
`achieve this goal remains the ability of manufacturers to shrink their tech(cid:173)
`nology, essentially in getting more memory chips per wafer through process
`scaling. Unfortunately, with all memory manufacturers pursuing the same
`goals, it is literally a race to see who can get there first. As a result, there is
`tremendous pressure to advance the state of the art-more so than in other
`related technologies due to the commodity status of memory.
`While the memory industry continues to drive forward, most people can
`relax and enjoy the benefits-except for those of you who need to join in
`the fray. For you, the only way out is straight ahead, and it is for you that we
`have written the second edition of this book.
`The goal of DRAM Circuit Design: Fundamental and High-Speed Topics
`is to bridge the gap between the introduction to memory design available in
`most CMOS circuit texts and the advanced articles on DRAM design that
`
`XIII
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0012
`
`

`

`XIV
`
`Preface
`
`are available in technical journals and symposium digests. The book intro(cid:173)
`duces the reader to DRAM theory, history, and circuits in a systematic, tuto(cid:173)
`rial fashion. The level of detail varies, depending on the topic. In most
`cases, however, our aim is merely to introduce the reader to a functional ele(cid:173)
`ment and illustrate it with one or more circuits. After gaining familiarity
`with the purpose and basic operation of a given circuit, the reader should be
`able to tackle more detailed papers on the subject.
`The second half of the book is completely devoted to advanced con(cid:173)
`cepts pertaining to state-of-the-art high-speed and high-performance
`DRAM memory. The two halves of the book are worlds apart in content.
`This is intentional and serves to rapidly advance the reader from novice to
`expert through the turning of a page.
`The book begins in Chapter I with a brief history of DRAM device evo(cid:173)
`lution from the first 1 Kbit device to the 64Mbit synchronous devices. This
`chapter introduces the reader to basic DRAM operation in order to lay a
`foundation for more detailed discussion later. Chapter 2 investigates the
`DRAM memory array in detail, including fundamental array circuits needed
`to access the array. The discussion moves into array architecture issues in
`Chapter 3, including a design example comparing known architecture types
`to a novel, stacked digitline architecture. This design example should prove
`useful, for it delves into important architectural trade-offs and exposes
`underlying issues in memory design. Chapter 4 then explores peripheral cir(cid:173)
`cuits that support the memory array, including column decoders and redun(cid:173)
`dancy. The reader should find Chapter 5 very interesting due to the breadth
`of circuit types discussed. This includes data path elements, address path
`elements, and synchronization circuits. Chapter 6 follows with a discussion
`of voltage converters commonly found on DRAM designs. The list of con(cid:173)
`verters includes voltage regulators, voltage references, V mJ2 generators,
`and voltage pumps.
`Chapter 7 introduces the concept of high-performance memory and
`underlying market forces. Chapter 8 examines high-speed DRAM memory
`architectures including a discussion of performance-cost trade-offs. Chapter
`9 takes a look at the input circuit path of high-performance DRAM while
`Chapter 10 takes a complementary look at the output circuit path. Chapter 11
`dives into the complicated world of high-performance timing circuits
`including delay-lock-loops and phase-lock-loops. Chapter 12 ties it all
`together by tackling the difficult subject of control logic design. This is an
`especially important topic in high-performance memory chips. Chapter 13
`looks at power delivery and examines methods to improve performance
`through careful analysis and design of the power delivery network. Finally,
`Chapter 14 discusses future work in high-performance memory. We wrap
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0013
`
`

`

`Preface
`
`xv
`
`up the book with the Appendix, which directs the reader to a detailed list of
`papers from major conferences and journals.
`
`Brent Keeth
`R. Jacob Baker
`Brian Johnson
`Feng Lin
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0014
`
`

`

`Chapter
`1
`
`An Introduction to DRAM
`
`Dynamic random access memory (DRAM) integrated circuits (ICs) have
`existed for more than thirty years. DRAMs evolved from the earliest kilobit
`(Kb) generation to the gigabit (Gb) generation through advances in both
`semiconductor process and circuit design
`technology. Tremendous
`advances in process technology have dramatically reduced feature size, per(cid:173)
`mitting ever higher levels of integration. These increases in integration have
`been accompanied by major improvements in component yield to ensure
`that overall process solutions remain cost-effective and competitive. Tech(cid:173)
`nology improvements, however, are not limited to semiconductor process(cid:173)
`ing. Many of the advances in process technology have been accompanied or
`enabled by advances in circuit design technology. In most cases, advances
`in one have enabled advances in the other. In this chapter, we introduce
`some fundamentals of the DRAM IC, assuming that the reader has a basic
`background in complementary metal-oxide semiconductor (CMOS) circuit
`design, layout, and simulation [l].
`
`1.1 DRAM TYPES AND OPERATION
`
`To gain insight into how modem DRAM chips are designed, it is useful to
`look into the evolution of DRAM. In this section, we offer an overview of
`DRAM types and modes of operation.
`
`1.1.1 The 1 k DRAM (First Generation)
`
`We begin our discussion by looking at the I ,024-bit DRAM (1,024 x
`I bit). Functional diagrams and pin connections appear in Figure I. I and
`Figure 1.2, respectively. Note that there are IO address inputs with pin
`labels R 1-R 5 and C 1-C 5 • Each address input is connected to an on-chip
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0015
`
`

`

`2
`
`Chap. | An Introduction to DRAM
`
`address input buffer. The input buffers that drive the row (R) and column
`(C) decoders in the block diagram have two purposes: to provide a known
`input capacitance (Cjy) on the address input pins and to detect the input
`address signal at a known level so as to reduce timing errors. The level
`Vrpjp, an idealized trip point around which the input buffers slice the input
`signals,
`is important due to the finite transition times on the chip inputs
`(Figure 1.3). Ideally, to avoid distorting the duration of the logic zeros and
`ones, Vrp;p should be positioned at a knownlevelrelative to the maximum
`and minimum input signal amplitudes. In other words, the reference level
`should change with changes in temperature, process conditions, input maxi-
`mum amplitude (Vj), and input minimum amplitude (Vj). Having said
`this, we note that the input buffers used in first-generation DRAMs were
`simply inverters.
`Continuing our discussion of the block diagram shown in Figure 1.1,
`we see that five address inputs are connected through a decoder to the
`1,024-bit memory array in both the row and columndirections. The total
`number of addresses in each direction, resulting from decoding the 5-bit
`word, is 32. The single memory array is made up of 1,024 memory ele-
`mentslaid out in a square of 32 rows and 32 columns. Figure 1.4 illustrates
`the conceptual layout of this memory array. A memory elementis locatedat
`the intersection of a row and a column.
`
`C1C2C3.C4 C5
`Voo
`
`O00 QO QO
`
`Addressinput
`buffers
`
`Cell matrix
`1,024 bits
`
`
`
`~5a£o®239<
`
`Figure 1.1 1,024-bit DRAM functional diagram.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0016
`
`

`

`Sec. 1.1 DRAM Types and Operation
`
`3
`
`
`
`Input buffer—Output to
`
`decoders
`
`
`_| |Outputsignal
`
`Figure 1.3 Ideal address input buffer.
`
`By applying an address of all zeros to the 10 address input pins, the
`memory data located at the intersection of row0, RAO, and column 0, CA0,
`is accessed.(It is either written to or read out, depending onthe state of the
`R/W* input and assuming that the CE* pin is LOW so that the chip is
`enabled.)
`It is important to realize that a single bit of memory is accessed by using
`both a row and a column address. Modern DRAMchipsreduce the number
`of external pins required for the memory address by using the same pins
`for both the row and column address inputs (address multiplexing). A clock
`signal row address strobe (RAS*) strobes in a row address and then, on the
`same set of address pins, a clock signal column address strobe (CAS*)
`strobes in a column addressat a differenttime.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0017
`
`

`

`4
`
`Chap.
`
`1
`
`An Introduction to DRAM
`
`Theintersection
`of a row and
`columnis the
`location of a
`memory bit.
`
`Column address decoder outputs
`CAO CA1 CA2
`CA30 CA31
`
`outputs
`
`Rowaddressdecoder
`
`Figure 1.4 Layout of a 1,024-bit memory array.
`
`Also note howa first-generation memory array is organized asalogical
`square of memory elements. (At this point, we don’t know whator how the
`memory elements are made. Wejust know thatthereis a circuit at the inter-
`section of a row and columnthat stores a single bit of data.) In a modern
`DRAMchip, many smaller memory arrays are organized to achieve a larger
`memory size. For example, 1,024 smaller memory arrays, each composed
`of 256 kbits, may constitute a 256-Meg (256 million bits) DRAM.
`
`1.1.1.1 Reading Data Out ofthe Ik DRAM. Data can be read out of
`the DRAMbyfirst putting the chip in the Read mode by pulling the R/W*
`pin HIGH andthen placing the chip enable pin CE* in the LOWstate. Fig-
`ure 1.5 illustrates the timing relationships between changes in the address
`inputs and data appearing on the Doy7 pin. Important timing specifications
`present in this figure are Read cycle time (tpc) and Access time (t4c). The
`term fgc specifies how fast the memory can beread.If tec is 500 ns, then
`the DRAM can supply 1|-bit words at a rate of 2 MHz. The term t4c spec-
`ifies the maximum length oftime after the input address is changed before
`the output data (Doy7) is valid.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0018
`
`

`

`Sec. 1.1 DRAM Types and Operation
`
`5
`
`tRC
`I Address changing11
`
`I
`1
`1
`
`!
`bc
`GQ}
`
`1
`I
`'
`
`Address
`R1i-R5 and
`C1i-C5
`
`Dataout,
`
`OUT
`
`1
`RMW* =1 CE*=0
`
`Figure 1.5 1k DRAM Readcycle.
`
`1.1.1.2 Writing to the 1k DRAM. Writing data to the DRAM is
`accomplished by bringing the R/W* input LOW with valid data present on
`the D,y pin. Figure 1.6 shows the timing diagram for a Write cycle. The
`term Write cycle time (twc) is related to the maximum frequency at which
`we can write data into the DRAM. The term Address to Write delay time
`(taw) specifies the time between the address changing and the R/W* input
`going LOW.Finally, Write pulse width (typ) specifies how long the input
`data must be present before the R/W* input can go back HIGHin prepara-
`tion for another Read or Write to the DRAM. Whenwriting to the DRAM,
`wecan think of the R/W* inputas a clocksignal.
`
`1.1.1.3 Refreshing the 1k DRAM. The dynamic nature of DRAM
`requires that the memory be refreshed periodically so as not to lose the con-
`tents of the memory cells. Later we will discuss the mechanismsthat lead to
`the dynamic operation of the memory cell. At this point, we discuss how
`memory Refresh is accomplished for the 1k DRAM.
`
`| = 20ns
`
`Address
`
`! |
`
`'
`
`|
`I
`!
`twp
`bw '
`'
`!
`'
`<———+,
`A
`\
`/
`'
`lop >
`' —11~20ns
`
`RM"
`
`waewenee I
`
`Data
`input
`
`Figure 1.6 1k DRAM Write cycle.
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0019
`
`

`

`6
`
`Chap. I An Introduction to DRAM
`
`Refreshing a DRAM is accomplished internally: external data to the
`DRAM need not be applied. To refresh the DRAM, we periodically access
`the memory with every possible row address combination. A timing dia(cid:173)
`gram for a Refresh cycle is shown in Figure 1.7. With the CE* input pulled
`HIGH, the address is changed, while the RIW* input is used as a strobe or
`clock signal. Internally, the data is read out and then written back into the
`same location at full voltage; thus, logic levels are restored ( or refreshed).
`
`fWC
`
`I
`
`I
`Row
`I
`a d d r e s - ; : - y - - - v (cid:173)
`inpu t s~
`
`Mr ~;r-
`CE*= LJ
`
`~ \__J
`~
`
`I
`
`Figure 1.7 lk DRAM Refresh cycle.
`
`1.1.1.4 A Note on the Power Supplies. The voltage levels used in the
`lk DRAM are unusual by modern-day standards. In reviewing Figure 1.2,
`we see that the lk DRAM chip uses two power supplies: V00 and Vss· To
`begin, Vss is a greater voltage than V00 : Vss is nominally 5 V, while V00 is
`-12 V. The value of Vss was set by the need to interface to logic circuits that
`were implemented using transistor-transistor logic (TTL) logic. The 17 V
`difference between V00 and Vss was necessary to maintain a large signal(cid:173)
`to-noise ratio in the DRAM array. We discuss these topics in greater detail
`later in the book. The Vss power supply used in modern DRAM designs, at
`the time of this writing, is generally zero; the V00 is in the neighborhood of
`1.5 V.
`
`1.1.1.5 The 3-Transistor DRAM Cell One of the interesting circuits
`used in the lk DRAM (and a few of the 4k and 16k DRAMs) is the 3-tran(cid:173)
`sistor DRAM memory cell shown in Figure 1.8. The column- and rowlines
`shown in the block diagram of Figure 1.1 are split into Write and Read line
`pairs. When the Write rowline is HIGH, Ml turns ON. At this point, the
`data present on the Write columnline is passed to the gate of M2, and the
`information voltage charges or discharges the input capacitance of M2. The
`next, and final, step in writing to the mbit cell is to turn OFF the Write row(cid:173)
`line by driving it LOW. At this point, we should be able to see why the
`memory is called dynamic. The charge stored on the input capacitance of
`M2 will leak off over time.
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0020
`
`

`

`Sec. 1.1 DRAM Typesand Operation
`
`7
`
`Write columniine
`
`Read columnline
`
` Read rowline
`Write rowline
`
`M1
`
`
`
`
`
`‘
`
`
`capacitanceYStorage node
`of M2
`
`Input
`
`¥
`
`
`
`Figure 1.8 3-transistor DRAM cell.
`
`If we want to read out the contents of the cell, we begin by first pre-
`charging the Read columnline to a knownvoltage and then driving the Read
`rowline HIGH. Driving the Read rowline HIGH turns M3 ONand allows
`M2either to pull the Read columnline LOW or to not change the pre-
`charged voltage of the Read columnline. (If M2’s gate is a logic LOW,then
`M2will be OFF, having no effect on the state of the Read columnline.) The
`main drawbackofusing the 3-transistor DRAM cell, and the reasonit is no
`longerused,is that it requires two pairs of column and rowlines and a large
`layout area. Modern 1-transistor, 1-capacitor DRAM cells use a single row-
`line, a single columnline, and considerablylessarea.
`
`1.1.2 The 4k-64 Meg DRAM (Second Generation)
`
`We distinguish second-generation DRAMs from_first-generation
`
`DRAMsbythe introduction of multiplexed address inputs, multiple mem-
`ory arrays, and the |-transistor/1-capacitor memory cell. Furthermore, sec-
`ond-generation DRAMs offer more modes of operation for greater
`flexibility or higher speed operation. Examples are page mode, nibble
`mode, static column mode, fast page mode (FPM), and extended data out
`(EDO). Second-generation DRAMsrange in size from 4k (4,096 x 1 bit,
`i.e., 4,096 address locations with 1-bit input/output word size) up to 64 Meg
`(67,108,864 bits) in memory sizes of 16 Meg x 4 organized as 16,777,216
`address locations with 4-bit input/output word size, 8 Meg x 8, or 4 Meg
`x 16.
`Two other major changes occurred in second-generation DRAMs:
`(1) the power supply transitioned to a single 5 V and (2) the technology
`advanced from NMOS to CMOS. The change to a single 5 V supply
`occurred at the 64kbit density. It simplified system design to a single power
`supply for the memory, processor, and any TTL (transistor-transistor logic)
`used in the system. As a result, rowlines had to be driven to a voltage
`
`Patent Owner Monterey Research, LLC
`Exhibit 2007, 0021
`
`

`

`8
`
`Chap. 1 An Introduction to DRAM
`
`greater than 5 V to turn the NMOSaccess devices fully ON (more onthis
`later), and the substrate held at a potential less than zero. For voltages out-
`side the supply range, charge pumps are used (see Chapter 6). The move
`from NMOSto CMOS, at the 1Mb density level, occurred because of con-
`cerns over speed, power, and layout size. At the cost of process complexity,
`complementary devices improved the design.
`
`Figure 1.9 shows a 4k DRAM block
`1.1.2.1 Multiplexed Addressing.
`diagram, while Figure 1.10 shows the pin connections for a 4k chip. Note
`that comparedto the block diagram of the 1k DRAM shownin Figure 1.1,
`the numberof address input pins has decreased from 10 to 6, even though
`the memory size has quadrupled. This is the result of using multiplexed
`addressing in which the same address input pins are used for both the row
`and column addresses. The row address strobe (RAS*) input clocks the
`address present on the DRAM address pins Ag to As into the row address
`latches on the falling edge