PC1 Local Bus
`Specification
`
`Revision 2.2
`December 18,1998
`
`1
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`Comcast, Ex. 1108
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`

`

`esz!
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`Revision 2.2
`
`REVISION HISTORY
`
`I
`
`I
`
`( REVISION I
`I
`1 Original issue
`I .O
`I
`I Incorporated connector and expansion board specification
`2.0
`Incorporated clarifications and added 66 MHz chapter
`Incorporated ECNs and improved readability
`
`2.1
`
`2.2
`
`(
`
`I DATE
`1 6/22/92
`
`I
`
`I
`
`4130193
`
`611 195
`
`1211 8/98
`
`The PC1 Special Interest Group disclaims all warranties and liability for the use of this document
`and the information contained herein and assumes no responsibility for any errors that may appear
`in this document, nor does the PC1 Special Interest Group make a commitment to update the
`information contained herein.
`
`Contact the PC1 Special Interest Group office to obtain the latest revision of the specification.
`
`Questions regarding the PC1 specification or membership in the PC1 Special Interest Group may be
`forwarded to:
`
`PC1 Special Interest Group
`2575 N.E. Kathryn #17
`Hillsboro, Oregon 9 7 124
`Phone: 800-433-5 177 (Inside the U.S.)
`503-693-6360 (Outside the U.S.)
`Fax:
`503-693-8344
`e-mail pcisig@pcisig.com
`http://www.pcisig.com
`
`DISCLAIMER
`This PC1 Local Bus Specification is provided "as is" with no warranties whatsoever,
`including any warranty of merchantability, noninfi-ingement, fitness for any particular
`purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
`The PC1 SIG disclaims all liability for infringement of proprietary rights, relating to use
`of information in this specification. No license, express or implied, by estoppel or
`otherwise, to any intellectual property rights is granted herein.
`
`ALPHA is a registered trademark of Digital Equipment Corporation.
`FireWire is a trademark of Apple Computer, Inc.
`
`Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are registered
`trademarks of Il3M Corporation.
`
`Windows, MS-DOS, and Microsoft are registered trademarks of Microsoft Corporation.
`
`Tristate is a registered trademark of National Semiconductor.
`NuBus is a trademark of Texas Instruments.
`Ethernet is a registered trademark of Xerox Corporation.
`
`All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
`
`Copyright O 1992, 1993, 1995, 1998 PC1 Special Interest Group
`
`2
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`Revision 2.2
`
`~~
`
`Contents
`
`Chapter 1 Introduction
`
`1 . 1. Specification Contents ............................................................................................................ 1
`
`1.2. Motivation ............................................................................................................................. 1
`
`1.3. PC1 Local Bus Applications ................................................................................................... 2
`
`1.4. PC1 Local Bus Overview ....................................................................................................... 3
`
`1.5. PC1 Local Bus Features and Benefits ..................................................................................... 4
`
`1.6. Administration ........................................................................................................................ 6
`
`Chapter 2 Signal Definition
`
`2.1. Signal Type Definition ...........................................................................................................
`8
`
`2.2. Pin Functional Groups ............................................................................................................ 8
`
`2.2.1. System Pins ..................................................................................................................... 8
`
`2.2.2. Address and Data Pins ..................................................................................................... 9
`
`2.2.3. Interface Control Pins .................................................................................................... 10
`
`2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11
`
`2.2.5. Error Reporting Pins ...................................................................................................... 12
`
`2.2.6. Interrupt Pins (Optional) ............................................................................................... 13
`
`2.2.7. Additional Signals ....................................................................................................... 15
`
`2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17
`
`2.2.9. JTAG/B oundary Scan Pins (Optional) .......................................................................... 18
`
`2.3. Sideband Signals ................................................................................................................. 19
`
`..................................................................................................
`2.4. Central Resource Functions
`19
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`Revision 2.2
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`Chapter 3 Bus Operation
`
`.....................................................................................................................
`3.1. Bus Commands
`21
`
`.....................................................................................................
`3.1.1. Command Definition
`21
`
`3.1.2. Command Usage Rules
`
`.................................................................................................
`23
`
`..................................................................................................
`3.2. PC1 Protocol Fundamentals
`26
`
`..................................................................................................
`3.2.1. Basic Transfer Control
`26
`
`.....................................................................................................................
`3.2.2. Addressing
`27
`................................................................................................
`.
`3.2.2.1 110 Space Decoding
`28
`.......................................................................................
`3.2.2.2. Memory Space Decoding
`28
`...............................................................................
`3.2.2.3. Configuration Space Decoding
`30
`3.2.3. Byte Lane and Byte Enable Usage ................................... .... ......................................... 38
`3.2.4. Bus Driving and Turnaround ......................................................................................... 39
`
`3.2.5. Transaction Ordering and Posting ................................................................................. 40
`3.2.5.1. Transaction Ordering and Posting for Simple Devices ........................................ 41
`3.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42
`
`3.2.6. Combining. Merging. and Collapsing ........................................................................... 44
`
`3.3. Bus Transactions .................................................................................................................. 46
`
`3.3.1. Read Transaction ........................................................................................................... 47
`
`..........................................................................................................
`3.3.2. Write Transaction
`48
`
`3.3.3. Transaction Termination ............................................................................................... 49
`3.3.3.1. Master Initiated Termination .................................................................................. 49
`..................................................................................
`3.3.3.2. Target Initiated Termination
`52
`3.3.3.3. Delayed Transactions ........................................................................................... 61
`
`3.4. Arbitration ............................................................................................................................
`68
`
`3.4.1. Arbitration Signaling Protocol ; ..................................................................................... 70
`
`3.4.2. Fast Back-to-Back Transactions ................................................................................... 72
`
`3.4.3. Arbitration Parking ........................................................................................................ 74
`
`3.5. Latency
`
`...............................................................
`.................................................................
`75
`
`...............................................................................................................
`3.5.1. Target Latency
`75
`3.5.1.1. Target Initial Latency ............................................................................................. 75
`3.5.1.2. Target Subsequent Latency .................................................................................... 77
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`3.5.2. Master Data Latency ...................................................................................................... 78
`
`3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78
`
`3.5.4. Arbitration Latency ....................................................................................................... 79
`3.5.4.1. Bandwidth and Latency Considerations ................................................................. 80
`3.5.4.2. Determining Arbitration Latency ........................................................................... 82
`3.5.4.3. Determining Buffer Requirements ......................................................................... 87
`
`3.6. Other Bus Operations ........................................................................................................... 88
`
`3.6.1. Device Selection .......................................................................................................... 88
`
`3.6.2. Special Cycle ................................................................................................................. 90
`
`3.6.3. AddressIData Stepping .................................................................................................. 91
`3.6.4. Interrupt Acknowledge .................................................................................................. 93
`
`3.7. Error Functions .....................................................................................................................
`93
`
`3.7.1. Parity Generation ........................................................................................................... 94
`
`3.7.2. Parity Checking ............................................................................................................. 95
`
`3.7.3. Address Parity Errors ................................. ............................. ..................................... 95
`
`3.7.4. Error Reporting .............................................................................................................. 95
`3.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 96
`3.7.4.2. Other Error Signaling on SERR# ........................................................................... 97
`3.7.4.3. Master Data Parity Error Status Bit ........................................................................ 98
`3.7.4.4. Detected Parity Error Status Bit ............................................................................. 98
`
`3.7.5. Delayed Transactions and Data Parity Errors
`
`...............................................................
`98
`
`3.7.6. Error Recovery .............................................................................................................. 99
`
`..........................................................................................................
`3.8. 64-Bit Bus Extension
`100
`
`3.8.1. Determining Bus Width During System Initialization ................................................ 104
`
`3.9. 64-bit Addressing ............................................................................................................... 105
`
`.........................................................................................
`3.10. Special Design Considerations
`108
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`Revision 2.2
`
`Chapter 4 Electrical Specification
`
`................................................................................
`113
`4.1.1. 5V to 3.3V Transition Road Map
`
`4.1.2. Dynamic vs . Static Drive Specification ...................................................................... 115
`
`4.2. Component Specification ................................................................................................... 115
`..........................................................................................
`4.2.1. 5V Signaling Environment
`117
`.................................................................................................
`117
`4.2.1.1. DC Specifications
`.................................................................................................
`4.2.1.2. AC Specifications
`118
`.....................................................
`4.2.1.3. Maximum AC Ratings and Device Protection
`120
`
`.......................................................................................
`4.2.2. 3.3V Signaling Environment
`122
`.................................................................................................
`122
`4.2.2.1. DC Specifications
`.................................................................................................
`4.2.2.2. AC Specifications
`123
`4.2.2.3. Maximum AC Ratings and Device Protection ..................................................... 125
`
`...................................................................................................
`4.2.3. Timing Specification
`126
`..............................................................................................
`4.2.3.1. Clock Specification
`126
`................................................................................................
`4.2.3.2. Timing Parameters
`128
`.......................................................................
`4.2.3.3. Measurement and Test Conditions
`129
`
`4.2.4. Indeterminate Inputs and Metastability ....................................................................... 130
`
`....................................................................................
`4.2.5. Vendor Provided Specification
`131
`
`4.2.6. Pinout Recommendation
`
`.............................................................................................
`131
`
`............. ....................................................................
`4.3. System (Motherboard) Specification
`132
`
`;
`
`..................................................................................................................
`4.3.1. Clock Skew
`132
`
`4.3.2. Reset ............................................................................................................................
`133
`
`4.3.3. Pull-ups ........................................................................................................................ 136
`
`4.3.4. Power ...........................................................................................................................
`137
`.
`.............................................................................................
`4.3.4.1 Power Requirements
`137
`4.3.4.2. Sequencing ............................................................................................................
`137
`4.3.4.3. Decoupling ............................................................................................................ 138
`
`................................................................................................
`4.3.5. System Timing Budget
`
`138
`
`................................................................................................
`141
`4.3.6. Physical Requirements
`4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards ............... 141
`.......................................................................................
`4.3.6.2. Motherboard Impedance
`141
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`Ps
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`4.3.7. Connector Pin Assignments
`
`........................................................................................
`142
`
`..........................................................................................
`4.4. Expansion Board Specification
`146
`
`.................................................................................................
`4.4.1. Board Pin Assignment
`146
`
`....................................................................................................
`4.4.2. Power Requirements
`150
`4.4.2.1. Decoupling ............................................................................................................ 150
`.............................................................................................
`4.4.2.2. Power Consumption
`150
`................................................................................................
`4.4.3. Physical Requirements
`151
`...................................
`.......................................
`..................
`4.4.3.1. Trace Length Limits
`151
`...........................
`152
`4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards
`4.4.3.3. Impedance ........................................................................................................
`152
`......................................................................................................
`4.4.3.4. Signal Loading
`152
`
`Chapter 5 Mechanical Specification
`
`5.1. Overview ............................................................................................................................ 153
`
`......................................................
`154
`5.2. Expansion Card Physical Dimensions and Tolerances
`
`..................................................................................
`5.2.1. Connector Physical Description
`168
`........................................................................
`5.2.1.1. Connector Physical Requirements
`176
`..................................................................
`5.2.1.2. Connector Performance Specification
`177
`................................................................................................
`178
`
`5.2.2. Planar Implementation
`
`Chapter 6 Configuration Space
`
`.....................................................................................
`6.1. Configuration Space Organization
`190
`
`6.2. Configuration Space Functions .......................................................................................... 192
`
`...................................................................................................
`6.2.1. Device Identification
`192
`
`.............................................................................................................
`6.2.2. Device Control
`193
`
`6.2.3. Device Status ............................................................................................................... 196
`..............................................................................................
`6.2.4. Miscellaneous Registers
`198
`..........................................................................................................
`6.2.5. Base Addresses
`201
`.......................................................................................................
`6.2.5.1. Address Maps
`201
`6.2.5.2. Expansion ROM Base Address Register ........................................................... 204
`
`6.3. PC1 Expansion ROMs ........................................................................................................ 205
`
`....................................................................................
`206
`6.3.1. PC1 Expansion ROM Contents
`
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`...................................................................
`6.3.1.1. PC1 Expansion ROM Header Format
`206
`...................................................................................
`207
`6.3.1.2. PC1 Data Structure Format
`
`...............................................................................
`6.3.2. Power-on Self Test (POST) Code
`209
`
`6.3.3. PC-compatible Expansion ROMs ................................................................................ 209
`......................................................................................
`6.3.3.1. ROM Header Extensions
`209
`
`...............................................................................................................
`6.4. Vital Product Data
`212
`
`....................................................................................................................
`6.5. Device Drivers
`212
`
`6.6. System Reset
`
`......................................................................................................................
`213
`
`..................................................................................................................
`6.7. Capabilities List
`213
`
`6.8. Message Signaled Interrupts .............................................................................................. 214
`
`.......................................................................................
`6.8.1. Message Capability Structure
`214
`.......................................................................................................
`215
`6.8.1.1. Capability ID
`..........................................................................................................
`215
`6.8.1.2. Next Pointer
`...................................................................................................
`6.8.1.3. Message Control
`215
`6.8.1.4. Message Address .................................................................................................. 217
`.....................................................................
`6.8.1.5. Message Upper Address (Optional)
`217
`........................................................................................................
`218
`6.8.1.6. Message Data
`
`6.8.2. MSI Operation ..............................................................................................................
`218
`..............................................................................
`6.8.2.1. MSI Transaction Termination
`220
`....................................
`6.8.2.2. MSI Transaction Reception and Ordering Requirements
`220
`
`Chapter 7 66 Mhz PC1 Specification
`
`........................................................................................................................
`7.1. Introduction
`221
`
`7.2. Scope ...................................................................... ........................................................... 221
`
`7.3. Device Implementation Considerations ............................................................................. 222
`
`...
`7.3.1. Configuration Space : ................................................................................................ 222
`
`7.4. Agent Architecture ............................................................................................................. 222
`
`...............................................................................................................................
`7.5. Protocol
`222
`
`7.5.1. 66MHZ-ENABLE (M66EN) Pin Definition .............................................................. 222
`
`7.5.2. Latency ........................................................................................................................
`223
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`7.6. Electrical Specification ....................................................................................................... 223
`
`Revision 2.2
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`PAm
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`7.6.2. Transition Roadmap to 66 MHz PC1 ........................................................................... 224
`................................................................................................
`7.6.3. Signaling Environment
`224
`.................................................................................................
`225
`7.6.3.1. DC Specifications
`.................................................................................................
`7.6.3.2. AC Specifications
`225
`7.6.3.3. Maximum AC Ratings and Device Protection ..................................................... 226
`
`7.6.4. Timing Specification ................................................................................................... 226
`..............................................................................................
`7.6.4.1. Clock Specification
`226
`7.6.4.2. Timing Parameters ................................................................................................
`228
`.......................................................................
`7.6.4.3. Measurement and Test Conditions
`229
`
`7.6.5. Vendor Provided Specification
`
`...................................................................................
`231
`
`.......................................................................................................
`7.6.6. Recommendations
`231
`.....................................................................................
`7.6.6.1. Pinout Recommendations
`231
`.................................................................................
`7.6.6.2. Clocking Recommendations
`231
`
`7.7. System (Planar) Specification ............................................................................................ 232
`
`........................................................................................................
`7.7.1. Clock Uncertainty
`232
`
`7.7.2. Reset ............................................................................................................................
`233
`
`7.7.3. Pullups .........................................................................................................................
`233
`
`...........................................................................................................................
`233
`7.7.4. Power
`.............................................................................................
`7.7.4.1 . Power Requirements
`233
`7.7.4.2. Sequencing .............................................................................................................
`233
`7.7.4.3. Decoupling ............................................................................................................ 233
`
`................................................................................................
`7.7.5. System Timing Budget
`233
`
`................................................................................................
`236
`7.7.6. Physical Requirements
`..........................
`236
`7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards
`7.7.6.2. Planar Impedance ................................................................................................. 236
`........................................................................................
`7.7.7. Connector Pin Assignments
`236
`
`7.8. Expansion Board Specifications ......................................................................................... 237
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`Revision 2.2
`
`Appendix A Special Cycle Messages ....................................... 239
`
`Appendix B State Machines ...................................................... 241
`
`Appendix C Operating Rules ..................................................... 251
`
`Appendix D Class Codes ........................................................... 257
`
`Appendix E System Transaction Ordering ............................... 267
`
`Appendix F Exclusive Accesses ................................................ 279
`
`Appendix G 110 Space Address Decoding for
`Legacy Devices .................................................... 285
`
`Appendix H Capability IDS .......................................................... 287
`
`Appendix I Vital Product Data ................................................... 289
`
`Glossary ....................................................................................... 297
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`Revision 2.2
`
`Figures
`
`Figure 1- 1: PC1 Local Bus Applications .................................................................................... 2
`
`Figure 1-2: PC1 System Block Diagram ..................................................................................... 3
`
`Figure 2- 1 : PC1 Pin List ............................................................................................................. 7
`
`Figure 3- 1 : Address Phase Formats of Configuration Transactions ........................................ 31
`
`Figure 3-2: Layout of CONFIG-ADDRESS Register ............................................................. 32
`
`Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions
`Address Phase ....................................................................................................... 33
`
`Figure 3-4: Configuration Read ............................................................................................... 38
`
`Figure 3-5: Basic Read Operation ............................................................................................ 47
`
`Figure 3-6: Basic Write Operation ........................................................................................... 48
`
`Figure 3-7: Master Initiated Termination ................................................................................. 50
`
`Figure 3-8: Master-Abort Termination ....................................................................................
`
`51
`
`Figure 3-9: Retry ......................................................................................................................
`55
`
`Figure 3-10: Disconnect With Data .......................................................................................... 56
`
`Figure 3- 11 : Master Completion Termination ......................................................................... 57
`
`Figure 3-12: Disconnect-1 Without Data Termination ............................................................ 58
`
`Figure 3-13: Disconnect-2 Without Data Termination ............................................................ 58
`
`Figure 3-14: Target-Abort ........................................................................................................ 59
`
`Figure 3-15: Basic Arbitration ................................................................................................. 70
`
`Figure 3-16: Arbitration for Back-to-Back Access ................................................................ 74
`
`Figure 3- 17: DEVSEL# Assertion ........................................................................................... 89
`
`Figure 3-18: Address Stepping ................................................................................................. 92
`
`Figure 3-19: Interrupt Acknowledge Cycle .............................................................................. 93
`
`Figure 3-20: Parity Operation .................................................................................................. 94
`
`Figure 3-21: 64-bit Read Request With 64-bit Transfer ........................................................ 103
`
`Figure 3-22: 64-bit Write Request With 32-bit Transfer ....................................................... 104
`
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`Revision 2.2
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`.......................................................................
`107
`Figure 3.23 . 64-Bit Dual Address Read Cycle
`
`Figure 4- 1 :
`
`.........................................................................................
`PC1 Board Connectors
`114
`
`Figure 4-2:
`
`................................................................................
`120
`VfI Curves for 5V Signaling
`
`Figure 4-3:
`
`......................................................
`121
`Maximum AC Waveforms for 5V Signaling
`
`Figure 4-4:
`
`.............................................................................
`124
`V/I Curves for 3.3V Signaling
`
`Figure 4-5:
`
`...................................................
`125
`Maximum AC Waveforms for 3.3V Signaling
`
`Figure 4-6:
`
`Clock Waveforms ..............................................................................................