IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`COMCAST CABLE COMMUNICATIONS, LLC,
`
`Petitioner,
`
`V.
`
`ROVI GUIDES, INC.,
`Patent Owner.
`
`Patent No. 7,200,855
`
`Filing Date: May 24, 2001
`Issue Date: April 3, 2007
`
`Title: METHOD AND APPARATUS OF MULTIPLEXING A PLURALITY OF
`
`CHANNELS IN A MULTIMEDIA SYSTEM
`
`Inter Partes Review Nos.: IPR2020—00787, IPR2020—00788, IPR2020-00789
`
`DECLARATION OF DOANH VU
`
`1
`
`Comcast, Ex. 1007
`
`1
`
`Comcast, Ex. 1007
`
`

`

`I, Doanh Vu, make the following declaration pursuant to 28 U.S.C. § 1746:
`
`1.
`
`I am an independent contractor. I have been providing file history and
`
`non-patent literature retrieval services and other USPTO information services for
`
`more than 12 years. Generally, when I receive a request for a USPTO file history
`
`document, I travel to the USPTO where I work with the staff in the publically
`
`accessible File Information Unit (FIU) in Shirlington, VA, to request and copy the
`
`document.
`
`2.
`
`I provide this Declaration in connection with the above-identified
`
`Inter Partes Review proceeding requested at
`
`the United States Patent and
`
`Trademark Office by Comcast Cable Communications, LLC against Rovi Guides,
`
`Inc. under 35 U.S.C. § 311, 37 C.F.R. § 42.104. Unless otherwise stated, the facts
`
`stated in this Declaration are based on my personal knowledge.
`
`3.
`
`I was requested to obtain a copy of the file history of US. Patent No.
`
`6,218,864 and a copy of non-patent literature document entitled PC] Local Bus
`
`Specification, Revision 2.2 contained in the file history. A true and correct copy of
`
`the file history of US. Patent No. 6,218,864 that I obtained is attached hereto as
`
`Appendix A. A true and correct copy of the non-patent literature document entitled
`
`PCI Local Bus Specification, Revision 2.2 that I obtained is attached hereto as
`
`Appendix B.
`
`2
`
`

`

`4.
`
`To obtain the requested documents, I entered patent number 6,218,864
`
`in the patent file history request electronic system at the FIU that forwards the
`
`request to FIU warehouse staff who retrieve the history folder for the entered
`
`patent number. I retrieved the publically accessible file history folder from the FIU
`
`office, confirmed that it was marked with US. Patent No. 6,218,864.
`
`I located the
`
`requested documents therein and copied them using the document copiers at the
`
`FIU. Specifically I copied the file history and the non—patent literature document
`
`entitled PCI Local Bus Specification, Revision 2.2 from the history folder provided
`
`by the FIU warehouse staff.
`
`I scanned the copied documents and forwarded them
`
`by email to the requester.
`
`5.
`
`I understand that willful false statements and the like are punishable
`
`by fine or imprisonment, or both.
`
`I declare under penalty of perjury that the foregoing is true and correct. Executed
`
`this 15th day of April, 2020, at Falls Church, VA.
`
`Doanh Vu
`
`‘
`
`l/o
`
`3
`
`

`

`
`
`
`
`
`Appendix A
`Appendix A
`
`
`
`
`
`
`
`
`i4
`
`

`

`U.S. UTILITY PATENT APPLICATION
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`* ~ e d ~ n ~ ~ ~ ~ A F P ! ~
`STRUCTURE AND METHOD FOR GENERATING A CLOCK
`
`1 X-579 U S
`I Steven P. Young et al.
`T& I ENABLE SIGNAL IN A PLD
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`116
`117
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`118
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`119
`120
`121
`138
`140
`141
`142
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`123
`126
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`

`

`PATENT
`
`1
`2
`3
`4
`5
`
`STRUCTURE AND METHOD FOR GENERATING
`A CLOCK ENABLE SIGNAL IN A PLD
`Steven P. Young
`Jane W. Sowards
`Wilson K. Yee
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`This application relates to the following commonly assigned
`co-pending U.S. patent application: Serial No. 09/321,513
`L A . 4 - -
`"
`-invented
`
`by Andrew K. Percey, Trevor J.
`
`Bauer, and Steven P. Young entitled "Input/Output Interconnect
`Circuit for FPGAs", which is incorporated herein by reference.
`
`FIELD OF THE INVENTION
`The invention relates to programmable logic devices (PLDs).
`More particularly, the invention relates to a structure and
`method for generating a clock enable signal for a PLD.
`
`BACKGROUND OF THE INVENTION
`It is necessary for integrated circuits (ICs), including
`prog;ammable logic device (PLDs), to communicate according to
`established protocols. For example, when two or more ICs drive
`a single bit of a bus, only one IC can be allowed to provide the
`signal at a given time. If a single bus line is driven both
`high and low at the same time, then the line may assume an
`intermediate state, thereby producing both unpredictable logical
`results and an undesirable power drain at the signal
`destination. Further, if a data signal and a clock signal are
`both provided from a first IC to a second IC, the two signals
`must be provided at known relative times, to avoid latching the '
`wrong data.
`To avoid such situations, and to allow ICs from various
`manufacturers to communicate with each other, various standards
`have been developed specifying required input/output behavior at
`
`Express Mail No. EM253370003US
`
`1
`
`12
`
`

`

`X-579 US
`
`PATENT
`
`IC pins. Systems employing such a standard typically can
`include only devices adhezing to the standard. Therefore, the
`ability to meet such a standard is a strong commercial
`advantage.
`One such standard is the PC1 standard. PC1 is an open,
`
`n ~ n - ~ r o ~ r i & t a r ~ local bus standard offering high performance for
`multiple peripheral devices. The standard is becoming widely
`accepted throughout the computer industry. A complete PC1
`Revision 2.2 specification is available from PC1 Special
`Interest Group, P.O. Box 14070, Portland, OR 97214, and is
`incorporated herein by reference. PC1 works as a
`processor-independent bridge between a CPU and high-speed
`peripherals and allows PC1 cards built today to be used in many
`different systems. In essence, the PC1 standard specifies .a
`standard data bus width, address bus width, and control signals
`to control a standardized set of commands implemented by the
`standard, e.g., read, write, and so forth. Also specified are
`the required timing relationships among all of these signals.
`Fig. 1 shows a small part of a known circuit implementing
`,the PC1 standard (a "PC1 circuit") . As shown in Fig. 1, the
`control signals for the PC1 circuit include a tristate signal T
`for tristatable output buffers OBUF, as well as a data input
`signal I, a clock signal CK, and a Clock Enable signal PCI-CE
`for output registers OUTFF in which the output data is stored.
`(In the present specification, the same reference characters are
`used to refer to terminals, signal lines, and their
`corresponding signals. In the figures, input/output structures
`are shown as boxes including "XUs. These boxes represent
`buffered input/output pads such as are well, known in the art.)
`A maximum data bus width of 64 bits mandates provision for 64
`data input signals I, 64 data output registers OUTFF, and 64
`data output buffers OBUF. Clock enable signal PCI-CE is not
`supplied at an input pad; instead it is internally generated
`from two externally supplied signals specified by the PC1
`. The
`standard: initiator ready (I,,)
`and target ready (T,,)
`
`13
`
`

`

`X-579 US
`
`PATENT
`
`1 logical and timing interrelationships between signals Imy and
`
`Tmy are dictated by the PC1 standard. A PC1 circuit also
`
`includes other signals (not shown) requiring additional
`input/output pads, buffers, output registers and other
`circuitry. Some of the additional output registers are also
`driven by clock enable signal PCI-CE.
`The PC1 standard supports two different rates of data
`transfer, 33 MHz (megahertz) and 66 MHz, and two different data
`bus widths, 32 bits and 64 bits. (The data bus width of 32 or
`64 bits is typically used to identify the specific standard,
`although the bus implemented by the standard includes additional
`control signals and is therefore wider than the numerical
`designator.) Even the 33 MHz data rate is difficult to achieve
`with a 64-bit data bus, and the 66 MHz data rate is available in
`very few available devices at this writing. The standard is
`even more difficult to meet when attempting to implement a PC1
`circuit in a programmable logic device (PLD) such as a field
`programmable gate array (FPGA). A difficult requirement to meet
`,for the 66 MHz/64-bit standard is a 6 ns (nanosecond) maximum
`allowable clock-to-out delay for the output register. In other
`words, the delay from the time the clock signal CK is available
`at the clock input pad to the time the output signal appears on
`the output pad 0 can be no more than 6 ns. In order to meet
`this timing requirement, the output register OUTFF must be
`located at or near the output pad 0. Even so, typically several
`nanoseconds are consumed between the output register and the
`output pad. In one PLD, the virtexm device from Xilinx, Inc.,
`the data transfer from output register to output pad requires 3
`ns. Therefore, only 3 ns are available to provide the clock
`signal CK from the clock input pad to the output register. This
`timing is normally achievable using known methods (e. g., global
`clock networks).
`However, the clock enable signal PCI-CE must be present at
`the output register OUTFF prior to the arrival of the clock CK.
`
`6
`
`14
`
`

`

`PATENT
`
`Therefore, the clock enable signal PCI-CE has less than 3 ns to
`reach the output register. Fortunately, the I,,
`and T,,
`signals
`
`have a setup time of 3 ns 'at the input pads. Therefore, there
`is a total of less than 6 ns available between the arrival of
`I,,
`and T,,
`at the input pads and the PCI-CE signal arriving at
`
`the output register.
`As previously described (and as shown in Fig. I), the clock
`enable signal PCI-CE does not come directly from a buffered pad.
`Instead, the clock enable signal is generated on-chip from the
`two signals I,,
`and T,,.
`Therefore, some internal logic ("CE
`
`Logic" in Fig. 1) is of necessity included in the clock enable
`path. Further, the clock enable signal PCI-CE is very heavily
`loaded. The PC1 standard for the 64-bit bus specifies 64 data
`output registers driven by this signal, and there are typically
`several other output registers driven by PCI-CE (e.g., 13)
`required to implement the standard in the FPGA. Therefore, the
`clock enable signal PCI-CE has a fanout of more than 64.
`Consequently, the 3 ns I,,
`and T,,
`setup requirement is very
`
`difficult to meet. In particular, this requirement is difficult
`,to meet when implementing the 64-bit, 66 MHz PC1 standard in
`programmable logic devices, using the available programmable
`logic resources.
`It is desirable to provide a structure and method for
`supplying a PC1 clock enable signal from the signals I,,
`and T,,
`
`4
`
`to the clock enable pins of output registers in less than the
`time specified by the PC1 standard. It is yet further desirable
`to provide a similar structure and method for use in PLDs
`adhering to other standards.
`
`SUMMARY OF THE INVENTION
`The invention provides a structure and method of generating
`an internal clock enable signal in a programmable logic device
`(PLD). A first embodiment of the invention comprises a clock
`enable circuit implemented such that the critical paths between
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`1 the I,,
`
`and T,,
`
`signals and the PCI-CE signal have only two
`
`levels of logic. In this "embodiment, the critical paths are
`implemented in dedicated logic while other portions of the clock .'
`enable circuit are implemented using programmable logic. This
`mixture of dedicated and programmable logic allows the critical
`path requirements to be met while allowing less critical
`portions of the clock enable circuit to be implemented using
`standard logic blocks. When the same PLD is used to implement a
`non-PCI-compliant circuit, these logic blocks can be used for
`other purposes. Thus, the combination of dedicated and
`programmable circuitry enables the highly efficient use of
`device resources for all circuits, while allowing the
`implementation when required of circuits meeting or exceeding
`the very high PC1 standard.
`According to another embodiment of the invention, the clock
`enable circuit is located near the center of a first edge of the
`device. This location has the advantages of balancing the skew
`on the clock enable signal and minimizing the delay from the
`clock enable circuit to the farthest output register. A first
`(plurality of output registers are located along the first edge
`on either side of the clock enable circuit. A first clock
`enable interconnect line extends along the first edge adjacent
`to the output registers. Additional output registers are
`located along the two adjacent half-edges of the device, with
`two clock enable interconnect lines paralleling the two adjacent
`half-edges. Programmable interconnection points (PIPS) permit
`the clock enable interconnect line along the first edge to be
`programmably coupled to the two adjacent clock enable
`interconnect lines. This capability of, so to speak,
`"programmably extending the clock enable interconnect line
`around the corners" has two advantages. Firstly, when only the
`output registers along the first edge are used, the loading on
`the clock enable interconnect line is reduced, thereby speeding
`up this critical signal. Secondly, this technique allows the
`clock enable circuit of the invention to be used on a device or
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`package too small to have sufficient output registers along a
`single edge.
`In another embodiment, the clock enable circuit is
`duplicated in the centers of two opposite edges of the device.
`This arrangement allows the device to be mounted in a package in
`either the "face up" or "face down" position. Further, this
`arrangement works well in accommodating the pin locations
`recommended as part of the PC1 standard. Additionally, two
`independent PC1 interfaces can be simultaneously implemented in
`a single device.
`In one embodiment, the clock enable interconnect lines
`along the left and right edges of an FPGA are dedicated to the
`PCI-CE signal. However, the clock enable interconnect lines
`along the top and bottom of the FPGA are implemented using
`general interconnect resources. For example, in one embodiment
`the bi-directional hex lines described in U.S. Patent
`Application Serial No. 09/321,513 are used to form the top and
`bottom clock enable interconnect lines. Therefore, the
`horizontal clock enable lines can be extended in segments
`spanning 12 output registers (6 input/output blocks).
`In another embodiment, a programmable delay element is
`included in the clock enable circuit. Using the programmable
`delay element, the clock enable signal edge can be adjusted with
`respect to the clock signal edge so that it falls within the
`setup and hold time "window" for each output register in the
`PLD. This aspect of the invention allows the same clock enable
`circuit to be used in PLDs of widely varying sizes. In one
`embodiment, the programmable delay element is mask programmable.
`
`\
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention is illustrated by way of example, and
`not by way of limitation, in the following figures, in which
`like reference numerals refer to similar elements.
`Fig. 1 shows a known prior art structure for passing PC1
`data signals through an output register.
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`Fig. 2 shows a clock enable circuit according to one
`1
`2 embodiment of the invention.
`3
`Fig. 3 shows a PLD with two clock enable circuits arranged
`4 according to another embodiment of the invention.
`Fig. 4 shows a clock enable circuit according to another
`5
`6 embodiment of the invention.
`Fig. 5 shows a programmable delay element for the clock
`7
`8 enable circuit of Fig. 4.
`While the invention is susceptible to various modifications
`9
`10 and alternative forms, specific embodiments thereof are shown by
`11 way of example in the drawings and are described herein in
`12 detail. It should be understood, however, that the detailed
`description is not intended to limit the invention to the
`particular forms disclosed. On the contrary, the intention is
`to cover all modifications, equivalents, and alternatives
`falling within the spirit and scope of the invention as defined
`by the appended claims.
`
`\
`
`DETAILED DESCRIPTION OF'THE DRAWINGS
`In the following description, numerous specific details are
`set +orth to provide a more thorough understanding of the
`present invention. However, it will be apparent to one skilled
`in the art that the present invention may be practiced without
`these specific details.
`Fig. 2 shows a clock enable circuit according to one
`embodiment of the invention. Additional logic (not shown) is
`also used when generating a PC1 circuit according to the PC1
`standard. This logic is easily generated by those of ordinary
`skill in the relevant arts, therefore it is not shown in Fig. 2,
`for clarity. The additional logic is preferably implemented in
`programmable logic gates available in a logic array in the PLD.
`Signals coming from the additional logic are labeled in Fig. 2
`as "From General Interconnect".
`The clock enable circuit of Fig. 2 includes first and
`second AND-gates 201, 202 and 3-input OR-gate 203. A buffered
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`1 input pad provides the initiator ready signal I,,.
`
`The
`
`2 inversion of initiator ready signal I,,
`
`is ANDed in AND-gate 201 .'>
`
`3 with a signal from the general interconnect structure,
`4 preferably provided by the internal logic array. Thus, the
`5 origin of the signal is selectable by the user when programming
`6 the PLD, along with the additional logic described above. AND-
`7 gate 201 drives OR-gate 203, which provides the PC1 clock enable
`8 signal PCI-CE.
`Similarly to the initiator ready input signal I,,,
`9
`
`the
`
`10 target ready signal T,,
`
`is provided by a buffered input pad.
`
`11 The inversion of target ready signal T,,
`
`is ANDed in AND-gate'
`
`202 with a signal from the general interconnect structure,'
`preferably provided by the internal logic array. AND-gate 202
`also drives OR-gate 203, which provides the PC1 clock enable
`signal PCI-CE.
`The third input signal for OR-gate 203 comes from the
`general interconnect structure, preferably provided by the
`(internal logic array.
`By looking at Fig. 2, it is easily seen that the path from
`either of input signals I,,
`and T,,,
`to the clock enable signal
`
`4"
`
`PCI-CE comprises only two gate delays, the delay through one
`AND-gate (203 or 204) plus the delay through OR-gate 203. In
`one embodiment, the gates shown in Fig. 2 are implemented in
`equivalent CMOS logic comprising two NOR-gates and a NAND-gate.
`As is well-known to those of ordinary skill in the relevant
`arts, the clock enable signal itself is preferably buffered one
`or more times as it is distributed about the PLD. However, the
`delay engendered by generating the logic clock enable signal
`comprises only two gate delays. Note that the delay through the
`internal logic array has been removed from the critical paths
`between the input signals I,,
`and Tmy and the clock enable
`
`signal PCI-CE.
`Fig. 3 shows a PLD with two clock enable circuits arranged
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`1 according to another embodiment of the invention. The interior
`2 of the PLD comprises a logic array of programmable logic blocks
`3 or gates. Surrounding the logic array is a ring of input/output
`4 blocks comprising output registers (OUTFFx), output buffers
`5 (OBUFx), and output pads (Ox). The output registers are each
`6 driven by a programmable clock signal CK and a programmable
`7 clock enable signal CE. The output registers are also grouped
`8 into two groups, one on the left half of the PLD and one on the
`9 right half of the PLD. The clock signal CK and clock enable
`10 signal CE for each group are separate. Because the right half
`of the PLD is a mirror image of the left half, only the output
`registers on the left half of the PLD are described.
`The clock signal CK is provided by a global clock buffer
`CKBUFL located, in this embodiment, at the top center of the
`PLD. (In other embodiments, the clock buffer is located at the
`bottom of the PLD, a corner of the PLD, or in another location.)
`As with many known global clock distribution networks, the clock
`signal CK is first routed to the center of the PLD, then
`distributed globally from that point, to minimize skew. The
`clock signal CK is distributed to the output registers on an
`interconnect line running parallel to the edges of the PLD and
`outside 6
`the logic array. A single clock is used for all output
`registers on the left half of the PLD.
`The clock enable signal is provided by a clock enable
`circuit CE-CKT-L in the center of the left side of the PLD. The
`clock enable generation circuit CE-CKT-L can be implemented, for
`example, as shown in Fig. 2. In this embodiment, internal
`programmable logic signals are also provided by way of general
`interconnect lines from the logic array to the clock enable
`circuit CE-CKT-L. From this central location, the clock enable
`signal PCI-CE-L is distributed to the output registers along the
`left edge of the PLD, via a vertical interconnect line running
`parallel to the edge of the PLD and outside the logic array.
`This vertical interconnect line can be programmably coupled via
`a programmable interconnect point PIP-UL to a horizontal
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`1 interconnect line extending to the output registers positioned
`2 above the logic array. The vertical interconnect line carrying
`3 the PCI-CE-L signal can also be programmably coupled via a
`4 programmable interconnect point PIPLL to a horizontal
`5 interconnect line extending to the output registers positioned
`6 below the logic array.
`7
`The provision of programmable interconnect points (PIPS)
`8 between the vertical and horizontal clock enable interconnect
`9 lines permits the clock enable signal to be provided only to the
`10 output registers located along the left-hand edge of the PLD
`11 (OUTFF1 - OUTFFn and OUTFF33 - OUTFFm in the embodiment of Fig.
`12 3). The output registers along the top edge (OUTFFn+l -
`13 OUTFF32) and the bottom edge (OUTFFm+l - OUTFF64) are optionally
`14 decoupled from the clock enable circuit. This feature speeds up
`15 the clock enable signal significantly when less than a 64-bit
`16 bus is used, by significantly reducing the loading on the
`17 signal. The values of n and m vary depending on the number of
`18 output registers along the edge of the PLD. In one embodiment,
`19' all 64 data output registers are arrayed along the left edge of
`;he PLD. In other embodiments, a maximum data bus width