UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`INTEL CORPORATION
`Petitioner,
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`v.
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`PACT XPP SCHWEIZ AG
`Patent Owner
`________________
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`Case IPR2020-00537
`U.S. Patent 7,928,763
`________________
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`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
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`Case No. IPR2020-00537
`U.S. Patent No. 7,928,763
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`TABLE OF CONTENTS
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`
`INTRODUCTION ................................................................................ 1
`I.
`STATUTORY DISCLAIMER ............................................................. 2
`II.
`III. BACKGROUND .................................................................................. 3
`A.
`The ’763 Patent .......................................................................... 3
`B.
`Claims at Issue ............................................................................ 5
`C.
`Prior Art Cited In The Petition ................................................... 8
`1.
`Balmer .............................................................................. 8
`2. Wilkinson ....................................................................... 12
`IV. GROUNDS I, III, AND IV FAIL BECAUSE PETITIONER FAILS
`TO ESTABLISH THAT THE ALLEGED “BUS SYSTEM”
`INTERCONNECTS THE IDENTIFIED NON-VOLATILE
`MEMORY .......................................................................................... 14
`A. Ground I Fails (CLAIMS 19 AND 49) Because Petitioner Fails
`To Establish That The “Cross-Bar Switch” in Balmer
`Interconnects The “Optical Disc 5001” Or The “Hard Drive
`5002” ........................................................................................ 15
`Ground III Fails (CLAIMS 19 AND 49) Because Petitioner
`Fails To Establish That The Alleged “Bus System”
`Interconnects The “Card Mounted Hard Drives” .................... 24
`Ground IV Fails (CLAIMS 19 AND 49) For The Same Reason28
`C.
`THE PETITION SHOULD BE DENIED BECAUSE IT FAILS THE
`REQUIREMENT UNDER 35 U.S.C. 312 ......................................... 28
`VI. PETITIONER FAILS TO PROVE THAT MIYAMORI IS A PRIOR
`ART PUBLICATION ......................................................................... 30
`VII. THE PETITION SHOULD BE DENIED BASED ON THE
`BOARD’S DISCRETION .................................................................. 35
`VIII. THE PETITION SHOULD BE DENIED FOR ADDITIONAL
`REASONS .......................................................................................... 37
`A.
`Petitioner’s Service Is Not Appropriate ................................... 37
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`V.
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`B.
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`B.
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`C.
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`The Petition Should Be Denied Because of the Co-pending
`District Court Case ................................................................... 40
`1.
`The Advanced Stage of the Parallel District Court
`Proceedings and Significant Investment of Time and
`Resources by the Parties and District Court Counsels
`Weighs Against Institution. ........................................... 40
`Similar Invalidity Theories and Claims are at Issue in the
`Parallel District Court Proceeding ................................. 42
`The Petition Is Barred by Intel’s Declaratory Judgement Case
`Challenging Validity ................................................................ 42
`IX. CONCLUSION ................................................................................... 43
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`2.
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`TABLE OF AUTHORITIES
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`Page
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`CASES
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`Argentum v. Research Corp.,
`Case IPR2016-00204, Paper 19 (May 23, 2016) ...........................................33
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`Blast Motion, Inc. et al v. NewSpin Sports, LLC,
`Case IPR2019-00538, Paper 9 at 20 (July 8, 2019) ......................................27
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`Chevron Oronite Co. v. Infineum USA L.P., Case,
` IPR2018-00923, Paper 9 at 11 (Nov. 7, 2018) .............................................37
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`Cisco Systems, Inc. v. Chrimar Systems, Inc.,
`Case IPR2018-01511, Paper 11 (Jan. 31, 2019) ........................................2, 43
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`Click-to-Call Techs., LP v. Ingenio, Inc.,
`899 F.3d 1321, 1330 (Fed. Cir. 2018) ...........................................................38
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`Deeper UAB v. Vexilar, Inc.,
`Case IPR2018-01310, (Jan. 24, 2019) ............................................................. 2
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`Deeper UAB v. Vexilar, Inc.,
`Case, IPR2018-01310, Paper 7 (Jan. 24, 2019)
`(citing |SAS Inst. Inc. v. Iancu, 138 S. Ct. 1348 (2018) .................................36
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`Google LLC v. At Home Bondholders Liquidating Trust, 722 Fed.Appx.
`1044, 1049 (Fed. Cir. 2018) ................................................................... 23, 27
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`Harmonic Inc. v. Avid Tech., Inc.,
` 815 F.3d 1356, 1367 (Fed. Cir. 2016) ................................................... 36, 37
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`Homeland Housewares, LLC v. Whirlpool Corp.,
`865 F.3d 1372 (Fed. Cir. 2017) .....................................................................27
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`Hulu, LLC v. Sound View Innovations, LLC,
`Case IPR2018-01039, Paper 29 (Dec. 20, 2019).............................. 31, 32, 33
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`In-Depth Geophysical v. ConocoPhillips Company,
`Case IPR2019-00849, Paper 14 (Sept. 6, 2019) ..................................... 32, 33
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`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359, (Fed. Cir. 2016) ................................................. 19, 24, 27, 28
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`Monsanto Co. v. Syngenta Seeds, Inc.,
`503 F.3d 1352 (Fed. Cir. 2007) ....................................................................... 7
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`NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc.,
`Case IPR2018-00752, Paper 8 (Sept. 12, 2018) ............................................40
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`NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc., Case IPR2018-00752,
`Paper,
` 8 (Sept. 12, 2018).........................................................................................37
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`SAS Inst. Inc. v. Iancu,
`138 S. Ct. 1348 (2018) ..................................................................................... 2
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`Smart Microwave Sensors Gmbh v. Wavetronix LLC,
`Case IPR2016-00488, Paper 57 .......................................................... 6, 34, 35
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`Vectra Fitness, Inc. v. TNWK Corp.,
`162 F.3d 1379 (Fed. Cir. 1998) ....................................................................... 2
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`VIZIO, Inc. v. Polaris PowerLED Technologies, LLC, Case IPR2020-00043,
`Paper 30 at 6-12 (May 4, 2020) .....................................................................40
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`Wi-Lan, Inc. v. Apple, Inc.,
`811 F.3d 455 (Fed. Cir. 2016) ......................................................................... 7
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`STATUTES
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`35 U.S.C. § 112 .......................................................................................................... 7
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`35 U.S.C. § 253(a) ..................................................................................................... 2
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`35 U.S.C. § 312 ........................................................................................... 29. 30, 36
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`35 U.S.C. § 312(a) ...................................................................................................29
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`35 U.S.C. § 312(a)(3) ............................................................................ 19, 24, 27, 28
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`35 U.S.C. § 314(b) ...................................................................................................41
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`35 U.S.C. § 315(a) ...............................................................................................2, 43
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`35 U.S.C. 315(a)(1)). ...............................................................................................43
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`35 U.S.C. § 315 (b) ..................................................................................................39
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`35 U.S.C. 316(a) ......................................................................................................41
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`RULES
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`37 C.F.R. § 42.104(b)(4)–(5) ...................................................................................19
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`37 C.F.R. § 42.105(a) ........................................................................................ 38, 39
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`37 C.F.R. § 42.106(a)(2) ..........................................................................................38
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`37 C.F.R. § 42.106(a)(2), .........................................................................................39
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`37 C.F.R. § 42.107(e) ................................................................................................. 2
`37 C.F.R. § 42.107(e) ................................................................................................. 2
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`37 C.F.R. 1.321(a) ...................................................................................................... 2
`37 C.F.R. 1.321(a) ...................................................................................................... 2
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`37 CFR § 1.75 ............................................................................................................ 7
`37 CFR§ 1.75 ............................................................................................................ 7
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`37 C.F.R. § 42.4(a) ...................................................................................................37
`37 C.F.R. § 42.4(a) ................................................................................................... 37
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`EXHIBIT LIST
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`Exhibit No. Description
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`2001
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`2002
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`2003
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`2004
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`2005
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`2006
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`2007
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`2008
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`2009
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`2010
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`2011
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`2012
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`2013
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`2014
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`Certified translation of Commercial Register showing the
`change of name of Scientia Sol Mentis AG to PACT XPP
`Schweiz AG
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`Statutory Disclaimer disclaiming claims 1-3, 9-14, 16-18, 20-22,
`24, 26, 30-33, 39-44, 46-48, 50-52, 54, 56, and 60 of the ’763
`patent
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`Excerpts of the complaint in PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-267 (D. Del.).
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`Proof of service of PACT XPP Schweiz AG v. Intel Corporation,
`No. 19-cv-267 (D. Del.).
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`Notice of dismissal of PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-267 (D. Del.).
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`Power of attorney chain of the ’763 patent
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`The Scheduling Order in PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-1006 (D. Del.).
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`Order Extending Time
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`Docket summary of PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-1006 (D. Del.).
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`PACT’s Letter Regarding Claim Narrowing and Swapping
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`Excerpts of Petitioner’s invalidity contentions in the District
`Court case
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`Petitioner’s complaint in Intel Corporation v. PACT XPP
`Schweiz AG, No. 19-cv-2241 (N.D. Cal. April 25, 2019)
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`LinkedIn page of Gerard P. Greinier
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`Gerard P. Greinier’s declaration in Smart Microwave Sensors
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`Exhibit No. Description
`Gmbh v. Wavetronix LLC, Case IPR2016-00488, Exhibit 1023
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`I.
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`INTRODUCTION
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`On April 24, 2020, Patent Owner PACT XPP Schweiz AG (“Patent Owner”
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`or “PACT”) filed a statutory disclaimer of most of the claims challenged by the
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`Petitioner Intel Corporation (“Petitioner” or “Intel”). Ex. 2002.0002. The only
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`remaining claims at issue are claims 19 and 491 of U.S. Patent No. 7,928,763 (“the
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`’763 patent”). Claims 19 and 49 were challenged on Ground I of the Petition as
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`being obvious in view of Balmer, on Ground III as being obvious in view of
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`Wilkinson and Hennessy, and on Ground IV as being obvious in view of
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`Wilkinson, Hennessy, and Miyamori.
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`As analyzed below, Petitioner fails to establish that the relevant prior art
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`references alone or together disclose “a bus system for interconnecting the plurality
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`of data processing cells, the plurality of memory cells, and the at least one interface
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`unit” as recited in claims 1 and 31 and incorporated into claims 19 and 49.
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`Specifically, Petitioner fails to show that claims 19 and 49 are invalid because the
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`non-volatile memory in the prior art Petitioner relies upon is not connected to the
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`bus system as required in independent claims 1, 31. When the limitations of the
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`independent claims are incorporated into the dependent claims 19 and 49, they
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`1 Claims 19 and 49 depend on claims 1 and 31 respectively, so we continue to
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`reference the relevant limitations from claims 1 and 31.
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`require that all of the “plurality memory cells,” including the non-volatile
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`memories, must be interconnected by the bus system. The prior art relied upon by
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`Petitioner does not disclose these limitations.
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`In addition, Petitioner fails to provide the relevant portion of the prior
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`reference Hennessey and thus violates 35 U.S.C. § 312. Petitioner also fails to
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`establish that Miyamori is a printed publication. And Petitioner also failed to
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`serve the Petition properly before the one-year bar date.
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`The Petition should also be denied under the Board’s discretion, because the
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`validity of the ’763 patent may be considered in a jury trial before the Board’s final
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`decision. See Deeper UAB v. Vexilar, Inc., Case IPR2018-01310, Paper 7 at 42
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`(Jan. 24, 2019) (Informative) (citing SAS Inst. Inc. v. Iancu, 138 S. Ct. 1348, 1356
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`(2018) (“[Section] 314(a) invests the Director with discretion on the question
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`whether to institute review.”) Finally, the Petition is barred under 35 U.S.C.
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`§315(a) because Petitioner previously challenged the validity of the ’763 patent in
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`a district court case before filing the present Petition since Petitioner alleged it did
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`infringe and “valid” claim. Cisco Systems, Inc. v. Chrimar Systems, Inc., Case
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`IPR2018-01511, Paper 11 (Jan. 31, 2019) (Precedential) (denying institution under
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`AIA § 315(a)(1)).
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`II.
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`STATUTORY DISCLAIMER
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`Patent Owner has filed a statutory disclaimer under 35 U.S.C. § 253(a) of
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`claims 1-3, 9-14, 16-18, 20-22, 24, 26, 30-33, 39-44, 46-48, 50-52, 54, 56, and 60
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`of the ’763 patent in compliance with 37 C.F.R. 1.321(a). See Ex. 2002.0002.
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`The result of such disclaimer is that the ’763 Patent “is treated as though the
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`disclaimed claims never existed.” Vectra Fitness, Inc. v. TNWK Corp., 162 F.3d
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`1379, 1383 (Fed. Cir. 1998). “No inter partes review will be instituted based on
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`disclaimed claims.” 37 C.F.R. § 42.107(e). Therefore, no inter partes review may
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`be instituted based on disclaimed claims 1-3, 9-14, 16-18, 20-22, 24, 26, 30-33, 39-
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`44, 46-48, 50-52, 54, 56, and 60.
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`The only remaining claims challenged in the Petition are claims 19 and 49 of
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`the ’763 patent. As shown below, Petitioner fails to show any reasonable
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`likelihood of prevailing against these two claims.
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`III. BACKGROUND
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`A. The ’763 Patent
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`The ’763 patent relates to “a cell element field for data processing.”
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`Ex. 1003, Abstract. Such “cell element field” has “function cell means for
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`execution of algebraic and/or logic functions,” as well as “memory cell means for
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`receiving, storing and/or outputting information.” Id. “F[igure] 1 [of the ’763
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`patent] shows a cell element field according to the present invention.” Ex. 1003,
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`7:31-32.
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`Ex. 1003, Fig. 1. “According to FIG. 1, a cell element field 1 for data processing
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`includes function cell means 2 for execution of arithmetic and/or logic functions
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`and memory cell means 3 for receiving, storing and/or outputting information, a
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`control connection 4 connecting function cells 2 to memory cells 3.” Ex. 1003,
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`7:47-51. “Cell elements 2, 3 of cell element field 1 are arranged two-
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`dimensionally in rows and columns, one memory cell 3 being situated directly next
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`to a function cell 2 with three memory cell-function cell pairs per row, the function
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`cells and memory cells being interconnected by control connections 4.” Id., 7:63-
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`67. The “function cell” could be an ALU. See id., 8:61-62 (“FIG. 2 shows
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`function cell 2 as an ALU.”). “The memory cells may store data and/or
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`information in a volatile and/or nonvolatile form.” Id., 4:19-20 (emphasis added).
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`B. Claims at Issue
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`There are two claims at issue: claim 19 and claim 49. Claim 19 depends on
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`claim 1 and claim 49 depends on claim 31. The only difference between
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`independent claim 1 and independent claim 31 is in their last element, where
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`claim 1
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`recites “programmably
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`interconnecting” while claim 31
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`recites
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`“dynamically interconnecting.” Ex. 1003, cls. 1, 31. The extra limitations in the
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`two dependent claims, claim 19 and claim 49, are the same. See id., cls, 19, 49.
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`All four claims are set forth below:
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`1. A multi-processor chip, comprising:
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`a plurality of data processing cells, each adapted for
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`sequentially executing at least one of algebraic and logic
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`functions and having:
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`at least one arithmetic logic unit;
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`at least one data register file;
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`a program pointer; and
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`at least one instruction decoder;
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`a plurality of memory cells;
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`at least one interface unit;
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`at least one Memory Management Unit (MMU); and
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`a bus system for interconnecting the plurality of data processing
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`cells, the plurality of memory cells, and the at least one
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`interface unit;
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`wherein
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`the bus system
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`is adapted for programmably
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`interconnecting at runtime at least one of data processing cells
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`and memory cells with at least one of memory cells and one or
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`more of the at least one interface unit.
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`19. The multi-processor chip according to claim 1, wherein at least
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`one of the memory cells is adapted to store data in a non-volatile
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`manner.
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`31. A multi-processor chip, comprising:
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`a plurality of data processing cells, each adapted for
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`sequentially executing at least one of algebraic and logic
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`functions and having:
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`at least one arithmetic logic unit;
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`at least one data register file;
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`a program pointer; and
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`at least one instruction decoder;
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`a plurality of memory cells;
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`at least one interface unit;
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`at least one Memory Management Unit (MMU); and
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`a bus system for interconnecting the plurality of data processing
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`cells, the plurality of memory cells, and the at least one
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`interface unit;
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`wherein
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`the bus
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`system
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`is adapted
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`for dynamically
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`interconnecting at runtime at least one of data processing cells
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`and memory cells with at least one of memory cells and one or
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`more of the at least one interface unit.
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`49. The multi-processor chip according to claim 31, wherein at least
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`one of the memory cells is adapted to store data in a non-volatile
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`manner.
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`Ex. 1003, cls. 1, 19, 31, 49 (emphasis added). The term “memory cells” are used
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`in multiple places in the independent claims 1 and 31, and dependent claims 19 and
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`49. It first appears in the independent claims when claims 1 and 31 recite “[a]
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`multi-processor chip, comprising: . . . a plurality of memory cells.” Ex. 1003,
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`cls. 1, 31. This lays the antecedent basis for the term.
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`A later element in the independent claims sets out the interconnection
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`structure between the “memory cells” and other components, requiring that “a bus
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`system for interconnecting the plurality of data processing cells, the plurality of
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`memory cells, and the at least one interface unit.” Ex. 1003, cls. 1, 31 (emphasis
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`added). Dependent claims 19 and 49 further provide limitations “at least one of the
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`memory cells is adapted to store data in a non-volatile manner.” Ex. 1003, cls. 19,
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`49.
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`“Subsequent use of the definite articles ‘the’ or ‘said’ in a claim refers back
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`to the same term recited earlier in the claim.” Wi-Lan, Inc. v. Apple, Inc., 811 F.3d
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`455, 462 (Fed. Cir. 2016). Thus, “the memory cells” in claims 19 and 49 are the
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`same memory cells referenced in claims 1 and 31, and they are subject to the
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`limitations of the independent claims. See 35 U.S.C. § 112 (pre-AIA) (“A claim in
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`dependent form shall be construed to incorporate by reference all the limitations of
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`the claim to which it refers.”); 37 CFR § 1.75 (c) (same); Monsanto Co. v.
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`Syngenta Seeds, Inc., 503 F.3d 1352, 1357 (Fed. Cir. 2007) (same). In other
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`words, the “at least one of the memory cells” recited in claims 19 and 49 belong to
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`the “the plurality of memory cells” recited in claims 1 and 31, and thus must be
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`limited by the “interconnecting” structural limitation in claims 1 and 31, i.e., “a bus
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`system for interconnecting the plurality of data processing cells, the plurality of
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`memory cells, and the at least one interface unit.” Ex. 1003, cls. 1 and 31.
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`Petitioner fails to establish this element.
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`C.
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`Prior Art Cited In The Petition
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`The Petition has five grounds, all based on Section 103. There are three
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`primary references in these five grounds: Balmer, Wilkinson, and Hennessy.
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`Balmer and Wilkinson are particularly relevant in this Preliminary Response.
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`1.
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`Balmer
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`Balmer discloses “an image and graphics processor.” Ex. 1005, Abstract.
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`“The processor is structured with several individual processors all having
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`communication links to several memories.” Id. “A crossbar switch serves to
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`establish the processor memory links. The entire image processor, including the
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`individual processors, the crossbar switch and the memories, is contained on a
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`single silicon chip.” Id. Figure 1 below “show[s] an overall view of the elements
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`of the image processing system.” Id., 3:24-25.
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`Ex. 1005, Figure 1. The “ISP [“image system processor”] CHIP NODE” in
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`Figure 1 includes “a set of parallel processors 100-103 and a master processor 12
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`connected to a series of memories 10 via a cycle-rate local connection network
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`switch matrix 20 called a crossbar switch.” Id., 4:45-48. “Transfer processor 11
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`communicates with external memory 15 via bus 21.” Id., 5:4-5. Figure 4 below
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`“shows a more detailed view of [Figure 1] where the four parallel processors 100-
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`103 are shown interconnected by communication bus 40 and also shown connected
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`to memory 10 via crossbar switch matrix 20.” Id., 5:62-66.
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`Ex. 1005, Figure 4. “This structure allows data from memories 10-0, 10-2, 10-3
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`and 10-4 to be distributed to any of the processors 100-103.” Id., 6:49-51.
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`The image system processor or ISP disclosed in Balmer can be “use[d] . . .
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`on a local and remote basis” as shown in Figures 49-52. Ex. 1005, 3:63-64. The
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`embodiment relevant to this IPR is in Figure 50 below.
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`Ex. 1005, Figure 50. This figure “describes an imbedded application of the image
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`system processor [or “ISP”] 5000.” Id., 28:43-44. The “EXT MEM 5003” in
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`Figure 50 is used to store information “collect[ed] . . . from the world, such as the
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`presence of an intruder in a security application.” See id., 28:54-60.
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`In Figure 50, there are two separate devices disclosed as 5001 and 5002.
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`5001 is “an optical disc” and 5002 is “a hard drive”; they are used to store
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`“program or instructions” that is not specified in Balmer. See id., 28:56-57 (“The
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`program or instructions have been previously stored in an optical disc 5001 or a
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`hard drive 5002.”). “[I]n a security application,” 5001 and 5002 “can also be used
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`to store incidences of information such . . . the image of an intruder.” Id., 28:58-
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`60. In the Petition, Intel alleges that the optical disc 5001 and the hard drive 5002
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`are the non-volatile “memory cells” recited in claims 19 and 49. Petition at 44-45.
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`As analyzed below, by making this allegation, Intel necessarily fails to identify the
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`“bus system for interconnecting the plurality of data processing cells, the plurality
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`of memory cells, and the at least one interface unit” as recited in independent
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`claims 1 and 31 (emphasis added).
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`2. Wilkinson
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`Wilkinson discloses “[a] parallel array processor,” or “APAP,” “for
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`massively parallel applications.” Ex. 1007, Abstract; see also id., 3:56-57 (“We
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`call it Advanced Parallel Array Processor, and use the acronym APAP.”). This
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`APAP is illustrated in Figure 11 below.
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`Ex. 1007, Figure 11. “[T]he preferred APAP [in Figure 11] has a basic building
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`block of a one chip node. Each node contains 8 identical processor memory
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`elements (PMEs) and one broadcast and control interface (BCI).” Ex. 1007, 23:29-
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`32; see also id., 6:25-27 (“In accordance with our invention a node is formed of an
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`array of PMEs, and we refer to the set of PMEs as a node. Preferably a node is 8
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`PMEs.”). The interconnections of these PMEs are further illustrated in a later
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`section of Wilkinson: “Each PME supports four 8 bit wide inter-PME
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`communication paths. These connect to 3 neighboring PMEs on the chip and 1 off
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`chip PME.” Id., 37:28-30. The internal structure of the PME is shown in Figure 8
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`below. Id., 14:66-15:3.
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`Ex. 1007, Figure 8. On the upper right corner, it shows that “the PME has its 32K
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`by 16 bit main store in the form of two DRAM macros.” Id., 26:25-27.
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`In the last section of Wilkinson, “SOME SUMMARY FEATURES,”
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`Wilkinson states that “APAP systems will be configurable and can include card
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`mounted hard drives selected from one of the set of units that are compatible with
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`PS/2 or RISC/6000 units.” Ex. 1007, 69:19-22. However, the structure and
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`connection of such “card mounted hard drives” is not disclosed anywhere in
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`Wilkinson. In the Petition, Intel alleges that the “card mounted hard drives” are
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`the non-volatile “memory cells” recited in claims 19 and 49. Petition at 78-79.
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`Again, by making this allegation, Intel necessarily fails to identify the “bus system
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`for interconnecting the plurality of data processing cells, the plurality of memory
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`cells, and the at least one interface unit” as recited in independent claims 1 and 31
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`(emphasis added).
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`IV. GROUNDS I, III, AND IV FAIL BECAUSE PETITIONER FAILS TO
`ESTABLISH THAT THE ALLEGED “BUS SYSTEM”
`INTERCONNECTS THE IDENTIFIED NON-VOLATILE MEMORY
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`Independent claims 1 and 31 recite that “a plurality of memory cells” and “a
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`bus system for interconnecting the plurality of data processing cells, the plurality
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`of memory cells, and the at least one interface unit.” Ex. 1003, cls. 1, 31. In other
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`words, the “plurality of memory cells” must be interconnected by the “bus system”
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`to “data processing cells” and the “interface unit.” Claims 19 and 49 further
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`specify that “at least one of the memory cells” is non-volatile memory. See Ex.
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`1003, cls 19 and 49 (“at least one of the memory cells is adapted to store data in a
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`non-volatile manner.”). When the limitations of the independent claims are
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`incorporated into the dependent claims 19 and 49, they require that all of the
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`“plurality memory cells,”
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`including
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`the non-volatile memories, must be
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`interconnected by the bus system. This is what Petitioner fails to establish.
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`For the independent claim purposes, Petitioner points to one type of bus
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`system that interconnect the “plurality memory cells.” However, such bus system
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`does not interconnect any non-volatile memory. For claims 19 and 49, Petitioner
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`points to certain non-volatile memories, but fail to explain why such non-volatile
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`memories are interconnected by the “bus system” identified for the independent
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`claims. This fatal mistake is common to Grounds I, III, and IV, and thus, all three
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`grounds fail.
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`A. Ground I Fails (CLAIMS 19 AND 49) Because Petitioner Fails To
`Establish That The “Cross-Bar Switch” in Balmer Interconnects
`The “Optical Disc 5001” Or The “Hard Drive 5002”
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`Petitioner alleges that claims 19 and 49 are obvious in view of Balmer. Both
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`claims that “at least one of the memory cells is adapted to store data in a non-
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`volatile manner.” Ex. 1003, cls. 19, 49. As discussed above, the “at least one of
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`the memory cells” is part of the “plurality of memory cells” recited in independent
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`claims 1 and 31, and must meet the structural limitations in the independent claims,
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`i.e., “a bus system for interconnecting the plurality of data processing cells, the
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`plurality of memory cells, and the at least one interface unit.” Ex. 1003, cls. 1 and
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`31. Petitioner fails to establish this structural limitation for claims 19 and 49.
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`For claims 19 and 49, Petitioner points to “an optical disc 5001 or a hard
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`drive 5002” as the “at least one of the memory cells . . . adapted to store data in a
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`non-volatile manner.” Petitioner at 44-45. However, as shown the annotated
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`figure in the Petition (reproduced below), the optical disc 3001 and hard drive
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`5002 are separate from the ISP chip node 5000 and are not connected to the “bus
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`system” identified by the petition.
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`Petition at 45. This is clear if viewed together with the annotated Figure 1
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`(reproduced below) in the Petition that is used by Petitioner for the “bus system.”
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`Petition at 27. Petitioner argues that “Balmer discloses a ‘crossbar switch’ and
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`‘processor connection bus’ that correspond to the claimed bus system. Specifically,
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`Balmer’s crossbar switch and processor connection bus interconnect components
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`within the chip.” Petition at 26 (emphasis added). Petitioner alleges that:
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`For example, the crossbar interconnect 20 (yellow) in Figure 1
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`connects to a master processor, the parallel processors (blue), the
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`memory units (purple), and the transfer processor (orange), which
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`includes an interface to external memory. Id.; Ex. 1001 ¶105. And the
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`processor connection bus 40 (yellow) in Figure 1 connects processors
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`to other processors. Ex. 1005, 6:52-56, 43:24-29.
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`Petition at 27 (emphasis added). Petitioner also points to Figure 4 (reproduced
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`below) of Balmer. See Petition at 27 (“Figure 4 shows a more detailed view of the
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`crossbar and processor connection bus, including the wires that connect the various
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`components”).
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`Petition at 28. See also id. (“Also referred to as a ‘switch matrix,’ the crossbar
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`uses ‘a plurality of links to be individually operated at crosspoints thereof to effect
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`the different arrangements desired.’). In other words, Petitioner points to the
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`“crossbar interconnect 20” and the “processor connection bus 40” together as the
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`“bus system” recited in independent claims 1 and 31.
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`However, Petitioner provides no evidence at all that the “crossbar
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`interconnect 20” and the “processor connection bus 40” also interconnect the
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`“optical disc 5001” or the “hard drive 5002,” much less analyses as to how the
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`“crossbar interconnect 20” and the “processor connection bus 40” interconnect the
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`optical disc and hard drive with other components. The Petition simply fails to
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`address the optical disc and hard drive as part of the “memory cells” when it
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`analyzes the “bus system.”
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`It is Petitioner’s burden to identify, “in writing and with particularity, each
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`claim challenged, the grounds on