IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`In re U.S. Patent No. 6,240,376
`
`Trial Number:
`
`Filed:
`
`Issued:
`
`July 31, 1998
`
`May 29, 2001
`
`Inventors: Alain Raynaud
`Luc M. Burgun
`
`Assignee: Mentor Graphics Corporation
`
`Title:
`
`Method and Apparatus for Gate-Level Simulation of Synthesized
`Register Transfer Level Designs with Source-Level Debugging
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,240,376
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`OHSUSA:751856847.1
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`PACT - Ex. 2015.0001
`
`

`

`Inter Partes Review of U.S. Patent No. 6,240,376
`
`TABLE OF CONTENTS
`
`TABLE OF CONTENTS ...................................................................................... II
`
`EXHIBIT LIST ..................................................................................................... IV
`
`I. MANDATORY NOTICES...............................................................................1
`
`A. Real Party-In-Interest.......................................................................................1
`
`B. Related Matters .................................................................................................1
`
`C. Lead And Back-Up Counsel.............................................................................1
`
`D. Service Information ..........................................................................................2
`
`II. PAYMENT OF FEES.......................................................................................2
`
`III. REQUIREMENTS FOR INTER PARTES REVIEW................................2
`
`A. Grounds For Standing......................................................................................3
`
`Identification Of Challenge..............................................................................3
`B.
`1. Claims for which inter partes review is requested..........................................3
`2. The specific art and statutory ground(s) on which the challenge is based......3
`3. How the challenged claims are to be construed ..............................................4
`4. How the construed claims are unpatentable under the statutory grounds
`identified in paragraph (b)(2) of this section..........................................................5
`5. Supporting evidence relied upon to support the challenge..............................5
`
`IV.
`
`SUMMARY OF THE ’376 PATENT ..........................................................5
`
`A. Description Of The Alleged Invention ............................................................5
`
`B. Summary Of The Prosecution History ...........................................................6
`
`V. THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST ONE
`CLAIM OF THE ’376 PATENT IS UNPATENTABLE .....................................7
`
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`PACT - Ex. 2015.0002
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`

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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`A. Identification Of The References As Prior Art..............................................7
`
`B. Summary Of Invalidity Arguments ................................................................8
`1. Koch invalidates claims 1-5, 8-11, 20-28 and 32-33 of the ’376 patent.........9
`2. Gregory patent invalidates claims 1-15 and 20-33 of the ’376 patent ..........11
`3. The HDL-ICE Brochure invalidates claims 1, 2, 5, 10-11 and 28 of the ’376
`patent.....................................................................................................................12
`4. Sample invalidates claims 1, 2, 5, 10-11 and 28 of the ’376 patent..............13
`
`VI. DETAILED EXPLANATION....................................................................13
`
`A. Koch Claim Chart...........................................................................................14
`
`B. Koch In View Of 1995 Koch Claim Chart....................................................29
`
`C. Gregory Claim Chart......................................................................................31
`
`D. Gregory In View Of 1995 Koch Claim Chart ..............................................47
`
`E. HDL-ICE Claim Chart...................................................................................52
`
`F. Sample Claim Chart .......................................................................................55
`
`G. Sample In View Of 1995 Koch Claim Chart ................................................58
`
`VII. CONCLUSION ............................................................................................59
`
`CERTIFICATE OF SERVICE ............................................................................61
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`PACT - Ex. 2015.0003
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`EXHIBIT LIST
`
`1001. U.S. Patent No. 6,240,376 to Raynaud, et al.
`
`1002. Prosecution history of application Serial No. 09/127,584, which matured
`into the ‘376 patent.
`
`1003. Chen, et al., “A Source-Level Dynamic Analysis Methodology and Tool
`for High-Level Synthesis,” Proceedings of the Tenth International
`Symposium on System Synthesis, 1997, pp. 134-140, Sep. 1997.
`
`1004. Koch, et al., “Breakpoints and Breakpoint Detection in Source Level
`Emulation,” ISSS Proceedings of the 9th International Symposium on
`System Synthesis, pp. 26-31 (1996).
`
`1005. Koch Publication information from CiteCeerX and ACM archives.
`
`1006. Koch, et al., “Debugging of Behavioral VHDL Specifications by Source
`Level Emulation,” Proceedings of the European Design Automation
`Conference, pp. 256-261, September 1995.
`
`1007. U.S. Patent No. 6,132,109 to Gregory, et al.
`1008. HDL-ICETM ASIC Emulation System, Quickturn Design Systems, Inc.
`1009. Prosecution history for application Serial No. 08/566,401, which matured
`into U.S. Patent No. 5,838,948.
`
`1010. U.S. Patent No. 5,960,191 to Sample, et al.
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`PACT - Ex. 2015.0004
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`Petitioner Synopsys, Inc. (“Synopsys” or “Petitioner”) respectfully requests
`inter partes review for claims 1-15 and 20-33 of U.S. Patent No. 6,240,376 (the
`“’376 patent,” attached as Ex. 1) in accordance with 35 U.S.C. §§ 311-319 and 37
`C.F.R. § 42.100 et seq.
`
`I. MANDATORY NOTICES
`
`to 37 C.F.R. § 42.8(a)(1), Synopsys provides the following
`Pursuant
`mandatory disclosures.
`
`A. Real Party-In-Interest
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner certifies that Synopsys, Inc. is
`the real party-in-interest.
`
`B. Related Matters
`
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner is unaware of any judicial or
`administrative matters that would affect, or be affected by, a decision in this
`proceeding. The ‘376 patent was involved in litigation styled as Mentor Graphics
`Corp. v. EVE-USA, Inc. and Emulation and Verification Engineering, SA, 6:06-
`CV-341-AA, which was dismissed with prejudice on November 30, 2006.
`
`C. Lead And Back-Up Counsel
`
`to 37 C.F.R. § 42.8(b)(3), Petitioner provides the following
`Pursuant
`designation of counsel:
`
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`PACT - Ex. 2015.0005
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`Lead Counsel
`
`William H. Wright
`wwright@orrick.com
`Registration No. 36,312
`CA Bar No. 161580
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`777 S. Figueroa Street, Suite 3200
`Los Angeles, California 90017
`Tel: 213-629-2020
`Fax: 213-612-2499
`
`Backup Counsel
`Travis Jensen
`tjensen@orrick.com
`Registration No. 60,087
`CA Bar No. 259925
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`Tel: 650-614-7400
`Fax: 650-614-7401
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
`Petition.
`
`D. Service Information
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), service information for lead and backup
`counsel is provided above.
`
`II. PAYMENT OF FEES
`
`The undersigned authorizes the Office to charge $32,600 to Deposit Account
`No. 15-0665 as the fee required by 37 C.F.R. § 42.15(a) for this Petition for Inter
`Partes Review. Review of 29 claims is being requested, so an excess claims fee is
`included in this fee calculation. The undersigned further authorizes payment for
`any additional fees that might be due in connection with this Petition to be charged
`to the above referenced Deposit Account.
`
`III. REQUIREMENTS FOR INTER PARTES REVIEW
`
`As set forth below and pursuant to 37 C.F.R. § 42.104, each requirement for
`inter partes review of the ’376 patent is satisfied.
`
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`PACT - Ex. 2015.0006
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`A. Grounds For Standing
`
`Pursuant to 37 C.F.R. § 42.104(a), Petitioner hereby certifies that the ’376
`patent is available for inter partes review and that the Petitioner is not barred or
`estopped from requesting inter partes review challenging the claims of the ’376
`patent on the grounds identified herein.
`
`B.
`
`Identification Of Challenge
`
`Pursuant to 37 C.F.R. § 42.104(b), the precise relief requested by Petitioner
`is that the Patent Trial and Appeal Board (“PTAB”) invalidate claims 1-15 and 20-
`33 of the ’376 patent.
`
`1. Claims for which inter partes review is requested
`
`Petitioner requests inter partes review of claims 1-15 and 20-33 of the ’376
`patent.
`
`2. The specific art and statutory ground(s) on which the challenge
`is based
`
`Inter partes review of the ’376 patent is requested in view of the following
`references, each of which is prior art to the ’376 patent under 35 U.S.C. § 102(a),
`(b), and/or (e):
`
`(1) Koch, et al., “Breakpoints and Breakpoint Detection in Source Level
`Emulation,” (here, Koch, Ex. 1004);
`
`(2) Koch, et al., “Debugging of Behavioral VHDL Specifications by
`Source Level Emulation,” (here, 1995 Koch, Ex. 1006);
`
`(3) U.S. Patent No. 6,132,109 to Gregory, et al., (here, Gregory, Ex.
`1007);
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`PACT - Ex. 2015.0007
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`(4) HDL-ICETM ASIC Emulation System, (here, HDL-ICE Brochure, Ex.
`1008); and
`
`(5) U.S. Patent No. 5,960,191 to Sample, et al., (here, Sample, Ex. 1009).
`
`Koch (Ex. 1004) anticipates claims 1-5, 8-10, 20-24, 28 and 32-33 under
`section 102 and renders those claims obvious under section 103.
`Koch (Ex. 1004) taken in view of 1995 Koch (Ex. 1006) renders obvious
`claims 11 and 25-27 under section 103.
`Gregory (Ex. 1007) anticipates claims 1-9, 11-14, 24-25 and 28-33 under
`section 102 and renders those claims obvious under section 103.
`Gregory (Ex. 1007) taken in view of 1995 Koch (Ex. 1006) renders obvious
`claims 10, 15, 20-23 and 26-27 under section 103.
`HDL-ICE brochure (Ex. 1009) anticipates claims 1, 2, 5, 10-11 and 28 under
`section 102 and renders those claims obvious under section 103.
`Sample (Ex. 1010) anticipates claims 1, 2, 5, 10 and 28 under section 102
`and renders those claims obvious under section 103.
`Sample (Ex. 1010) taken in view of 1995 Koch (Ex. 1006) renders obvious
`claim 11 under section 103.
`
`3. How the challenged claims are to be construed
`
`A claim subject to inter partes review receives the “broadest reasonable
`construction in light of the specification of the patent in which it appears.” 42
`C.F.R. § 42.100(b). Petitioner submits, for the purposes of this inter partes review
`only, that the claim terms take on their ordinary and customary meaning that the
`terms would have to one of ordinary skill in the art. None of the challenged claims
`contains a means-plus-function or step-plus-function limitation.
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`PACT - Ex. 2015.0008
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`4. How the construed claims are unpatentable under the statutory
`grounds identified in paragraph (b)(2) of this section.
`
`An explanation of how claims 1-15 and 20-33 of the ’376 patent are
`unpatentable under
`the statutory grounds
`identified above,
`including the
`identification of where each element of the claim is found in the prior art patents or
`printed publications, is provided in Section VI, below, in the form of claim charts.
`
`5. Supporting evidence relied upon to support the challenge
`
`The exhibit numbers of the supporting evidence relied upon to support the
`challenge and the relevance of the evidence to the challenge raised, including
`identifying specific portions of the evidence that support
`the challenge, are
`provided in Section VI, below, in the form of claim charts. An Appendix of
`Exhibits identifying the exhibits is also attached.
`
`IV. SUMMARY OF THE ’376 PATENT
`
`A. Description Of The Alleged Invention
`
`(Ex. 1001) describes a method of “instrumenting”
`The ‘376 patent
`synthesizable source code to facilitate debugging a circuit description such as one
`in register transfer level (RTL) source code. Ex. 1001, Abstract, col. 1:11-13.
`“[I]nstrumentation logic is created for a synthesizable statement in the RTL source
`code either by modifying the RTL source code or by analyzing the RTL source
`code during the synthesis process. The instrumentation logic provides an output
`signal indicative of whether the corresponding synthesizable statement is active. A
`gate-level design including the instrumentation output is then synthesized.” Id. at
`col. 5:3-8. That is, instrumentation logic is added to or tracked within the RTL
`source code description of a circuit and that logic is synthesized with the circuit
`description to provide a gate-level design incorporating the instrumentation logic.
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`PACT - Ex. 2015.0009
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`Integrated circuit engineers use hardware description languages (HDL) to
`Id. at col. 1:15-17. Register transfer level
`design parts of integrated circuits.
`(RTL) source code is a subset of hardware description languages. Id. at col. 1:17-
`25. The ‘376 patent identifies both VHDL and Verilog as examples of RTL
`languages. Software tools known as synthesizers and compilers turn designs
`described in VHDL or Verilog into gate-level descriptions called netlists and
`eventually into data for making masks used in manufacturing an integrated circuit.
`Id., col. 1:35-36, col. 1:26-27 (“Synthesis is the process of generating a gate-level
`netlist from the high level description languages.”).
`How the ‘376 patent goes about “instrumenting” source code at the register
`transfer level is illustrated by comparing FIG. 4 with FIGS. 6A, 6B. The patent
`starts with a section of conventional VHDL or Verilog code and adds a number of
`statements to the code to preserve information or to add information to the
`synthesized code. Id. at col. 7:55-col. 8:49. Most of the RTL structures, such as
`the FIG. 8 Verilog “always” block and the FIG. 11 VHDL “process” statement are
`conventional and defined in the standards listed in the background of the patent.
`See id. at col. 1:18-33. The ‘376 patent indicates what it adds to this conventional
`source code in the figures by using italics. Id. at col. 8:4-5.
`
`B. Summary Of The Prosecution History
`
`Application Serial No. 09/127,584 (Ex. 1002) was filed with thirty-three
`claims. The Examiner rejected most of the original claims, using the Chen
`reference (Ex. 1003) as the primary reference. In response to the first rejection, the
`applicant amended independent claims 1, 5, 12, 16 and 20 to specify that the
`“source code” is “register transfer level (RTL)” or “register transfer level (RTL)
`synthesizable.” The applicant argued that Chen described “high level synthesis”
`and does not describe “designs that are synthesizable by logic synthesis tools.”
`-6-
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`PACT - Ex. 2015.0010
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`Following another rejection primarily based on the Chen reference, the applicant
`similarly argued that the result of synthesizing the Chen reference’s high level
`synthesis design is a synthesized RTL design rather than a gate-level netlist.
`Ex.1002 at 163-168.
`the recited
`to claims 24-27 that
`The applicant argued with respect
`“sensitivity list” is a recognized part of the VHDL definition of “process” and that
`the claims consequently complied with section 112. Id. at 169-171. The applicant
`also argued that the Chen reference was inapplicable to claims 24-33 because the
`Chen reference relates solely to “high level synthesis.” Ex. 1002 at 171-172.
`These arguments were successful and resulted in a notice of allowance.
`
`V. THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST ONE
`CLAIM OF THE ’376 PATENT IS UNPATENTABLE
`
`A.
`
`Identification Of The References As Prior Art
`
`Koch, et al., “Breakpoints and Breakpoint Detection in Source Level
`Emulation,” ISSS Proceedings of the 9th International Symposium on System
`Synthesis, pp. 26-31 (1996) (here, Koch) stands as prior art under section 102(b).
`The copy of Koch provided as Ex. 1004 is from the CiteSeerX archive of Penn
`State University. Ex. 1005 is the publication information for Koch from both the
`CiteSeerx and the ACM (Association of Computing Machinery) online archives,
`each of which list 1996 as the publication date. The Office has identified Koch as
`a prior art reference having a date of 1996 or November 1996 in at least the
`following patents: U.S. Patent Nos. 6,378,124; 6,378,125; 6,543,049; 6,587,967;
`6,823,497; 6,904,577; 7,020,871 and 7,065,481.
`Koch, et al., “Debugging of Behavioral VHDL Specifications by Source
`Level Emulation,” Proceedings of the European Design Automation Conference,
`
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`PACT - Ex. 2015.0011
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`pp. 256-261, September 1995, was cited in the ‘376 patent prosecution and stands
`as prior art under section 102(b).
`U.S. Patent No. 6,132,109 to Gregory, et al., “Architecture and Methods for
`a Hardware Description Language Source Level Debugging System,” issued from
`application Serial No. 08/253,470 filed June 3, 1994, which was a continuation in
`part of application Serial No. 08/226,147, filed April 12, 1994. Gregory is prior art
`under at least section 102(e).
`HDL-ICETM ASIC Emulation System, Quickturn Design Systems, Inc.,
`published no later than July 9, 1996. Ex.1008 is a product brochure for the
`Quickturn Design System product HDL-ICE, which was retrieved from the file
`history of U.S. Patent No. 5,838,948 (Ex. 1009), which demonstrates that the
`HDL-ICE brochure was a publication available to the public no later than July 9,
`1996, the date on which the brochure was filed in an Information Disclosure
`Statement in application Serial No. 08/566,401. Ex. 1009 at 75. The HDL-ICE
`brochure is prior art under sections 102(a) and (b).
`U.S. Patent No. 5,960,191 to Sample, “Emulation System with Time-
`Multiplexed Interconnect,” issued on September 28, 1999 from an application filed
`on May 30, 1997. The Sample ’191 patent is prior art to the ’376 patent under at
`least 35 U.S.C. § 102(e).
`
`B. Summary Of Invalidity Arguments
`
`The Examiner’s statement of reasons for allowance characterized the ‘376
`patent’s “invention” as “inserting instrumentation points into the Register Transfer
`Level (RTL) design, which can then be synthesized to the gate-level description”
`and stated that it allowed “simulation breakpoints [to be] implemented in a gate-
`level circuit simulation.” Ex. 1002 at 174-175. The references discussed below
`show that this conclusion was based on incomplete information. In fact, the Koch
`-8-
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`PACT - Ex. 2015.0012
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`reference (Ex. 1004) describes altering a VHDL source code circuit description to
`introduce hardware into the generated (gate-level) circuit design to set and detect
`breakpoints. Koch unambiguously describes “inserting instrumentation points”
`into RTL that is then synthesized so that those instrumentation points can be used
`to set and detect breakpoints. Koch presents a reasonable likelihood that at least
`one claim of the ‘376 patent is unpatentable.
`Further, Gregory describes inserting probes into VHDL code that is then
`synthesized and optimized to provide a gate-level circuit design. The Gregory
`system processes the probes in a way that prevents certain signals from being
`removed during optimization and further provides those signals to higher levels of
`the design so that the gate-level circuit design can be analyzed at the VHDL level.
`Gregory thus describes inserting instrumentation points into RTL and the modified
`RTL is then synthesized to the gate-level description. Gregory presents a
`reasonable likelihood that at least one claim of the ‘376 patent is unpatentable.
`that
`In addition,
`the Petition discusses references related to a product
`predated the ‘376 patent called “HDL-ICE.” Koch states, “Quickturn has
`addressed this problem with the HDL-ICE system, which allows [a user] to relate
`the probed signals to an RT-specification.” Ex. 1004 at 1. The HDL-ICE
`Brochure and Sample discuss different aspects of the HDL-ICE system and each
`anticipates a number of the claims of the ‘376 patent.
`
`1. Koch invalidates claims 1-5, 8-11, 20-28 and 32-33 of the ’376
`patent
`
`The 1996 Koch article, “Breakpoints and Breakpoint Detection in Source
`Level Emulation” describes “source level emulation” (SLE) using breakpoints to
`verify a gate-level circuit while monitoring and inputting information into the
`VHDL (RTL) source code. SLE analyzes gate-level designs through hardware
`
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`PACT - Ex. 2015.0013
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`emulation and keeps the correlation between the gate-level design and the VHDL
`(RTL) design. Ex. 1004 at 1. "The idea of SLE is to run the application on …
`emulator hardware and to keep the correlation between hardware elements and the
`behavioral VHDL source such that
`it
`is possible to stop the hardware by
`interrupting the clock and to extract values of variables in the source code by
`reading registers of the circuit. This correlation is mainly obtained through logging
`the synthesis steps of the high level synthesis." Id.
`The ‘376 patent explains that “instrumentation” can be “preserving some of
`the information available at the source code level.” Ex. 1001 at col. 5:4-8, col.
`5:32-44. Koch thus describes identifying a statement that will correspond to an
`instrumentation signal in the synthesized code. Koch also modifies a received
`VHDL circuit description to include additional VHDL statements so that, when the
`modified circuit is synthesized, the introduced hardware allows the user “to set and
`detect breakpoints, to read data-registers, and to control the circuit operation. Ex.
`1004 at 1. This allows “debugging at the source code level” while using a gate-
`level emulator.
`The Koch reference primarily used in this petition is not cumulative to the
`1995 Koch reference (Ex. 1006) that was made of record to the prosecution of the
`‘376 patent.
`Rather
`the Koch reference of Ex. 1004 includes additional
`information on encoding, detecting and using breakpoints as well as a more
`sophisticated debugging and logging process. Nevertheless,
`the 1995 Koch
`reference includes useful and supplementary disclosure that is discussed in section
`VI below. As discussed in greater detail below in section VI, Koch anticipates
`claims 1-5, 8-10, 20-24, 28 and 32-33. In addition, Koch taken in view of the 1995
`Koch reference renders obvious claims 11 and 25-27.
`
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`PACT - Ex. 2015.0014
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`2. Gregory patent invalidates claims 1-15 and 20-33 of the ’376
`patent
`
`Gregory describes using probes to accomplish debugging circuit designs.
`Ex. 1007 at col. 6:18-20. “For example, the designer would use a simulator to
`determine if the circuit produced appropriate outputs from specified inputs.” Id. at
`col. 2:34-36. Gregory describes an integrated CAD system that includes processor
`executable instructions for translating (synthesizing and optimizing) VHDL or
`Verilog (both types of RTL) code into a gate-level design. Id. at col. 2:63-col. 3:6;
`col. 11:19-27.
`“The present invention … provid[es] a designer with the ability to mark the
`synthesis source code in the places that the designer wants to be able to debug.
`The designer marks the source code with a particular text phrase, such as ‘probe’,
`along with some additional information optional information.” Id. at col. 8:21-26.
`“During translation, the translator generates a circuit [that] provides the same
`function as it did without the ‘probe’ statement, but adds additional information or
`components to the initial circuit that indicate that certain components should not be
`replaced during optimization. Because those components will not be replaced
`during optimization, the circuit analysis results corresponding to any unreplaced
`components that are in the final circuit will be directly and traceably related to
`those components … in the source HDL, and therefore [can] be displayed near the
`appropriate portion of the HDL.
`Gregory describes a block probe methodology for instrumenting all of the
`signals within a process statement such as the one illustrated in FIG. 12. Id. at col.
`14:20-29, 37-54 (four types of block probes). Using a block probe function on the
`FIG. 12 VHDL is shown in FIG. 16 and causes the VHDL code to be synthesized
`and optimized as shown in FIG. 18. The block probes force the optimization to
`
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`PACT - Ex. 2015.0015
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`Inter Partes Review of U.S. Patent No. 6,240,376
`
`leave in temporary input signals temp_in and the temporary output signals
`temp_out.
`As discussed in greater detail below in section VI, Gregory anticipates
`claims 1-9, 11-14, 24-25 and 28-33.
`In addition, Gregory taken in view of the
`1995 Koch reference renders obvious claims 10, 15, 20-23 and 26-27.
`
`3. The HDL-ICE Brochure invalidates claims 1, 2, 5, 10-11 and 28
`of the ’376 patent
`
`The HDL-ICE ASIC Emulation System was a logic emulation system
`known in the art by 1995 that could “directly read Verilog or VHDL designs in
`RTL” and emulate “designs with up to 250,000 emulation gates.” Ex. 1008 at 2.
`The user inputted “synthesizable RTL” into the HDL-ICE emulation system and
`HDL-ICE directly mapped the RTL to the emulation hardware primitives to
`Id. at 3.
`generate gate-level netlists.
`In addition to mapping the RTL into the
`emulation hardware, HDL-ICE provided an “[i]ntegrated logic analyzer” that
`interfaced with the gate level design and allowed users to “[d]ebug familiar RTL
`code with [a] Source Level Browser.” Id. at 2. That is, the HDL-ICE emulation
`system allowed a user to debug a gate-level design in a manner that the user could
`directly relate to the high-level (RTL) design description used to generate that
`gate-level design. This is because HDL-ICE “preserves the familiar RTL net
`names … to provid[e] an efficient debug environment.” Id. at 3.
`As discussed in greater detail below in section VI, the HDL-ICE brochure
`anticipates or renders obvious claims 1, 2, 5, 10-11 and 28.
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`4. Sample invalidates claims 1, 2, 5, 10-11 and 28 of the ’376
`patent
`
`Sample describes a logic emulation system that receives and synthesizes
`RTL using HDL-ICETM software. Ex. 1010 at col. 28:34-38. The Sample system
`provides integrated debugging, including breakpoints and event definition and
`detection. Although Sample was provided to the Examiner during prosecution of
`the ‘376 patent, it is apparent from the prosecution history and the discussion
`below that Sample’s disclosure was not fully appreciated.
`In particular, Sample
`anticipates a number of the claims of the ‘376 patent.
`Sample describes the “HDL-ICETM synthesizer 1002, which … takes
`register-transfer-level (RTL) Verilog or VHDL netlists and converts them through
`a logic synthesis process into the database format used by the netlist importer and
`Id. at col. 28, lines 54-59. Sample provides logic
`other compilation steps.”
`analyzer functionality, such as the scan register shown in FIG. 20b or the testbench
`1004 identified in FIG. 21, that is added to a user’s RTL design and synthesized
`with that user’s RTL design. Id. at col. 22:32-34 (“additional … logic is added to
`the user’s design which is programmed into logic chips 10 or 204”), col. 28:63-64.
`Users can input information to the emulation system by filling out a form displayed
`on a workstation prior to compilation (synthesis). Id. at col. 23:23-26, col. 29:13-
`18.
`Information provided to the form determines how configurable logic blocks
`are allocated to fit the required event logic. Id. at col. 27:23-36.
`As discussed in greater detail below in section VI, Sample anticipates or
`renders obvious claims 1, 2, 5, 10-11 and 28.
`
`VI. DETAILED EXPLANATION
`
`Pursuant to 37 C.F.R. § 42.104(b)(4), Petitioner provides in the following
`claim charts a detailed comparison of the claimed subject matter and the prior art
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`specifying where each element of challenged claim is found in the prior art
`references. All emphasis is added unless otherwise indicated.
`
`A. Koch Claim Chart
`
`Claim Language
`
`1. A method comprising
`the steps of:
`a) identifying at least
`one statement within a
`register transfer level
`(RTL) synthesizable
`source code; and
`
`Koch (Ex. 1004)
`
`Koch describes source level emulation (SLE), which
`analyzes gate-level designs through hardware
`emulation and keeps the correlation between the gate-
`level design and the VHDL (RTL) design. Ex. 1004 at
`1. "The idea of SLE is to run the application on an
`emulator hardware and to keep the correlation between
`hardware elements and the behavioral VHDL source
`such that it is possible to stop the hardware by
`interrupting the clock and to extract values of variables
`in the source code by reading registers of the circuit.
`This correlation is mainly obtained through logging
`the synthesis steps of the high level synthesis." Id.
`"Since we want to debug a running circuit at the
`source code level, we have to define a breakpoint as
`something which is visible in the source code. On the
`other hand, a breakpoint must also be visible in the
`circuit to enable us to detect it. Thus, we define a
`breakpoint as an operation like +, *, etc. If such an
`operation is executed by a component, we can detect it
`in the running hardware." Id. at 2.
`The ‘376 patent explains that “instrumentation” can be
`“preserving some of the information available at the
`source code level.” Ex. 1001 at col. 5:4-8, col. 5:32-
`44. Koch thus describes identifying a statement that
`will correspond to an instrumentation signal in the
`synthesized code.
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`Claim Language
`
`b) synthesizing the
`source code into a gate-
`level netlist including at
`least one instrument-
`ation signal, wherein the
`instrumentation signal is
`indicative of an execu-
`tion status of the at least
`one statement.
`
`Koch (Ex. 1004)
`
`Koch describes synthesizing the VHDL circuit design.
`This is implicit in Koch’s statement that SLE “log[s]
`the synthesis steps of the high level synthesis.” Ex.
`1004 at 1. It is necessary to synthesize a design to be
`able to the “log the synthesis steps.” See also id. at 5-
`6 (discussing synthesis tool and specific synthesized
`circuits). Also, Koch explains that its SLE technique
`includes “hardware emulation” and notes that
`“emulation works at the gate level.” Id. at 1. As the
`‘376 patent explains, synthesis generates a “gate-level
`netlist.” Ex. 1001 at col. 1:26-27.
`As part of the SLE technique, Koch alters each register
`as shown in Koch Figure 7 so that the value in the
`register can be read out, providing a value that can be
`“backannotat[ed]” to allow debugging at the source
`level. Id. at 1, 5. The register values are
`instrumentation signals because they indicate the
`execution status of the “backannotat[ed]” statement or
`statements at the source level.
`Koch detects breakpoints using the synthesized
`circuitry illustrated in Figure 5. Breakpoints indicate
`the execution status of various operations. Id. at 2
`(“Thus, we define a breakpoint as an operation like +,
`*, etc. If such an operation is executed by a
`component, we can detect it in the running
`hardware."). In addition, Koch describes creating a
`finite state machine, using the VHDL description of
`Figure 4, which is a controller with different states
`associated with different breakpoint IDs. Id. at 4.
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`Inter Partes Review of U.S. Patent No. 6,240,376
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`Claim Language
`
`Koch (Ex. 1004)
`
`2. The method of claim
`1 wherein step b)
`includes the step of:
`i) generating instru-
`mentation logic to
`provide the instrument-
`ation signal as if the
`source code included a
`corresponding signal
`assignment statement
`within a same execu-
`table branch of the
`source code as the
`identified statement.
`
`Koch Figure 4 shows a VHDL process that, when
`synthesized, generates a finite state machine (FSM)
`i