UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`INTEL CORPORATION
`Petitioner,
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`v.
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`PACT XPP SCHWEIZ AG
`Patent Owner
`________________
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`Case IPR2020-00532
`U.S. Patent 8,471,593
`________________
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`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
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`I.
`II.
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`B.
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`V.
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`INTRODUCTION ........................................................................................... 1
`BACKGROUND ............................................................................................. 3
`A. Overview of the ’593 Patent .................................................................. 3
`B.
`Claims at Issue ....................................................................................... 5
`C.
`Overview of the Prior Art ...................................................................... 8
`1.
`Balmer (Ex. 1005) ....................................................................... 8
`2.
`Budzinski (Ex. 1006) ................................................................ 10
`III. CLAIM CONSTRUCTION .......................................................................... 12
`A.
`“a first structure dedicated for data transfer in a first direction” /
`“a second structure dedicated for data transfer in a second
`direction” (Claims 1 and 16) ............................................................... 13
`IV. THE PETITION FAILS TO DEMONSTRATE A REASONABLE
`LIKELIHOOD THAT ANY CLAIM IS INVALID ..................................... 17
`A.
`Balmer Does not Disclose a “First Structure Dedicated for Data
`Transfer in a First Direction” and a “Second Structure
`Dedicated for Data Transfer in a Second Direction” .......................... 19
`Budizinski Does not Disclose a “First Structure Dedicated for
`Data Transfer in a First Direction” and a “Second Structure
`Dedicated for Data Transfer in a Second Direction” .......................... 25
`THE PETITION SHOULD BE DENIED FOR PROCEDURAL
`REASONS ..................................................................................................... 30
`A.
`Petitioner’s Service Is Not Appropriate .............................................. 30
`B.
`The Petition Should Be Denied Because of the Co-Pending
`District Court Case .............................................................................. 34
`1.
`The Advanced Stage of the Parallel District Court
`Proceedings and Significant Investment of Time and
`Resources by the Parties and District Court Counsels
`Weighs Against Institution. ...................................................... 35
`The Same Invalidity Theories and Claims are at Issue in
`the Parallel District Court Proceeding ...................................... 36
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`TABLE OF CONTENTS
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`Page
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`2.
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`C.
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`The Petition Is Barred by Intel’s Declaratory Judgement Case
`Challenging Validity ........................................................................... 37
`VI. CONCLUSION .............................................................................................. 37
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`TABLE OF AUTHORITIES
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`Page(s)
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`Cases
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`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ..............................................................................22
`Cisco Systems, Inc. v. Chrimar Systems, Inc.,
`Case IPR2018-01511, Paper 11 (Jan. 31, 2019)...............................................2, 37
`Click-to-Call Techs., LP v. Ingenio, Inc.,
` 899 F.3d 1321 (Fed. Cir. 2018) ...........................................................................31
`Deeper UAB v. Vexilar, Inc.,
`Case IPR2018-01310, Paper 7 (Jan. 24, 2019)....................................................... 2
`Digital-Vending Servs. Int’l, LLC v. Univ. of Phoenix, Inc.,
`672 F.3d 1270 (Fed. Cir. 2012) ................................................................. 2, 16, 18
`NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc.,
`Case IPR2018-00752, Paper 8 (Sept. 12, 2018) ...................................................34
`SAS Inst. Inc. v. Iancu,
`138 S. Ct. 1348 (2018)............................................................................................ 2
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007). ...........................................................................13
`VIZIO, Inc. v. Polaris PowerLED Technologies, LLC,
`Case IPR2020-00043, Paper 30 at (May 4, 2020) ................................................34
`Statutory Authorities
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`35 U.S.C. § 314(b) ...................................................................................................35
`35 U.S.C. § 315(a) ...............................................................................................2, 37
`35 U.S.C. § 315(b) ............................................................................................ 30, 34
`35 U.S.C. § 316(a) ...................................................................................................35
`Rules and Regulations
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`37 C.F.R. § 42.100(b) ....................................................................................... 12, 13
`37 C.F.R. § 42.105(a) .................................................................................. 32, 33, 34
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`Additional Authorities
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`Changes to the Claim Construction Standard for Interpreting Claims in Trial
`Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg.
`51,340 (Oct. 11, 2018) ..........................................................................................13
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`EXHIBIT LIST
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`Exhibit No. Description
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`2001
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`2002
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`2003
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`2004
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`Certified translation of Commercial Register showing the
`change of name of Scientia Sol Mentis AG to PACT XPP
`Schweiz AG
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`Excerpts of the complaint in PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-267 (D. Del.).
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`Proof of service of PACT XPP Schweiz AG v. Intel Corporation,
`No. 19-cv-267 (D. Del.).
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`Notice of dismissal of PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-267 (D. Del.).
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`2005
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`The power of attorney chain of the ’593 patent
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`2006
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`Attorney address on the record of the ’593 patent
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`2007
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`2008
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`2009
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`2010
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`2011
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`2012
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`2013
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`The Scheduling Order in PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-1006 (D. Del.).
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`Stipulation and Order Regarding Document Production
`Deadline
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`Docket summary of PACT XPP Schweiz AG v. Intel
`Corporation, No. 19-cv-1006 (D. Del.).
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`PACT’s Letter Regarding Claim Narrowing and Swapping
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`Excerpts of Petitioner’s invalidity contentions in the District
`Court case
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`Petitioner’s complaint in Intel Corporation v. PACT XPP
`Schweiz AG, No. 19-cv-2241 (N.D. Cal. April 25, 2019)
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`The Illustrated Dictionary of Electronics (8th ed. 2001):
`“dedicated”
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`2014
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`Modern Dictionary of Electronics (7th ed.1999): “dedicated”
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`Case No. IPR2020-00532
`U.S. Patent No. 8,471,593
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`I.
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`INTRODUCTION
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`On February 7, 2020, Petitioner Intel Corporation (“Petitioner” or “Intel”)
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`waited until the last minute and filed the Petition to challenge Patent Owner PACT
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`XPP Schweiz AG’s (“Patent Owner” or “PACT”) patent at issue: U.S. Patent No.
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`8,471,593 (the “’593 patent”). Petitioner challenges both independent claims and
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`most dependent claims of the ’593 patent based on three obviousness grounds.
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`Ground I relies on Balmer (Ex. 1005) as the primary obviousness reference;
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`Grounds II and III rely on Budzinski (Ex. 1006) as the primary obviousness
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`reference. Each challenged claim is challenged under all three grounds.
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`The independent claims at issue are claims 1 and 16. For each of the three
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`Grounds, Petitioner fails to establish that the prior art discloses two necessary
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`elements, 1) “a first structure dedicated for data transfer in a first direction,” and 2)
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`“a second structure dedicated for data transfer in a second direction,” which are
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`common to both independent claims 1 and 16. Petitioner relies exclusively on
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`Balmer and Budzinski for these elements, and does not contend they are disclosed
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`by any secondary references. For both Balmer and Budzinski, the Petition alleges
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`that the “first structure” and “second structure” are disclosed by structures that
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`switch data onto a plurality of paths. A structure that can route data onto multiple
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`different paths, however, is not “dedicated for data transfer in a [first/second]
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`direction.” Put another way, the Petition attempts to improperly read out the
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`“dedicated” language in the claims. This is improper. Digital-Vending Servs.
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`Int’l, LLC v. Univ. of Phoenix, Inc., 672 F.3d 1270, 1275 (Fed. Cir. 2012) (“In
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`Phillips, this court reinforced the importance of construing claim terms in light of
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`the surrounding claim language, such that words in a claim are not rendered
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`superfluous.”). Because Petitioner fails to show that either Balmer or Budzinski
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`discloses these elements, Petitioner has failed to establish an invalidity case for any
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`of the challenged claims.
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`The Petition should also be denied because the Petitioner failed to serve the
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`Petition properly before the one-year bar date. In addition, the Board may exercise
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`its discretion pursuant to 35 U.S.C. § 314(a) to deny institution because the validity
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`of the ’593 patent may be considered in a jury trial before the Board’s final
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`decision. See Deeper UAB v. Vexilar, Inc., Case IPR2018-01310, Paper 7 at 42
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`(Jan. 24, 2019) (Informative) (citing SAS Inst. Inc. v. Iancu, 138 S. Ct. 1348, 1356
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`(2018) (“[Section] 314(a) invests the Director with discretion on the question
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`whether to institute review.”). The Petition is also barred under 35 U.S.C. §315(a)
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`because Petitioner previously challenged validity in a district court case before the
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`filing of the Petition. Cisco Systems, Inc. v. Chrimar Systems, Inc., Case IPR2018-
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`01511, Paper 11 (Jan. 31, 2019) (Precedential) (denying institution under AIA §
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`315(a)(1)). As such, the Board should deny institution.
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`II. BACKGROUND
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`A. Overview of the ’593 Patent
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`The ’593 patent describes an improved bus system for a data processor on a
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`chip. The patent recognizes that conventional bus systems in a processor
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`“become[] problematic when a great many communicating units need access to the
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`bus.” Ex. 1003 (’593 patent) at 2:4-6. The patent thus proposes a “segmented”
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`architecture using smaller “subbus systems” to connect components that are
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`“disposed close together” on a chip. Id. at 2:18-30.
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`Figure 9 (reproduced and annotated below) illustrates one embodiment of a
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`data processor chip in accordance with the invention. The chip includes multiple
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`processing cores (e.g., the PAE in blue), on-chip memories (e.g., the memory in
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`orange), as well as interface units (the input/output, or “I/O,” interfaces in red) for
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`communicating with memory that is external to the chip. Ex. 1003 (’593 Patent) at
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`Claim 1 and 16; id. at 9:34-48, Figs. 1-2, 9.
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`To solve the problems associated with bus communications on data
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`processors with a large number of components, the ’593 patent discloses an
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`improved bus system that flexibly interconnects the components of the data
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`processor chip. Id. at Abstract, 2:37-58, Figs. 2, 9. In particular, the ’539 patent
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`teaches that “two-way communication” of components can be enabled with
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`“separate bus systems … for opposite running directions.” Id. at 5:30-39. The
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`separate bus segments for communication in opposite directions may further be
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`facilitated by providing registers as interline elements. Id. at 5:40-45. These
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`registers are illustrated in Figure 9, in which a Forward Register (FReg) and
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`Backward Register (BReg) are connected to bus segments dedicated for forward
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`and backward communications, respectively. See id. at Fig. 9. By dividing the bus
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`system into segments and providing separate bus systems to enable communication
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`between components running in different directions, the bus system of the ’593
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`patent is able to increase data processing speeds. See id. at 2:37-58.
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`B. Claims at Issue
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`Petitioner challenges claims 1, 2, 4-11, 14-17, and 19-27 of the ’593 patent.
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`Claims 1 and 16 are independent claims; the remaining challenged claims depend
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`from either claim 1 or claim 16.
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`Claims 1 and 16 are reproduced below.
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`Claim 1: A data processor on a chip comprising:
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`a plurality of data processing cores, each of at least some of the processing
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`cores including:
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`at least one arithmetic logic unit that supports at least division and
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`multiplication of at least 32-bit wide data; and
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`at least 3 registers for storing at least 32-bit wide data;
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`a plurality of memory units to buffer at least 32-bit wide data;
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`at least one interface unit for providing at least one communication channel
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`between the data processor and external memory; and
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`a bus system flexibly interconnecting the plurality of processing cores, the
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`plurality of memory units, and the at least one interface;
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`wherein:
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`the bus system includes a first structure dedicated for data transfer in a
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`first direction and a second structure dedicated for data transfer in a
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`second direction; and
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`each of at least some of the data processing cores includes a
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`physically dedicated connection to at least one physically assigned
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`one of the plurality of memory units, the assigned one of the plurality
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`of memory units being accessible by another of the data processing
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`cores via a secondary bus path of the bus system.
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`Claim 16: A data processor on a chip comprising:
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`a plurality of data processing cores, each of at least some of the processing
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`cores including:
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`at least one arithmetic logic unit that supports at least division and
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`multiplication of at least 32-bit wide data; and
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`at least 3 registers for storing at least 32-bit wide data;
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`a plurality of memory units to buffer at least 32-bit wide data;
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`at least one interface unit for providing at least one communication channel
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`between the data processor and external memory; and
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`a bus system flexibly interconnecting the plurality of processing cores, the
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`plurality of memory units, and the at least one interface;
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`wherein:
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`the bus system includes a first structure dedicated for data transfer in a
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`first direction and a second structure dedicated for data transfer in a
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`second direction; and
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`each of at least some of the data processing cores includes a dedicated
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`connection to at least one assigned one of the plurality of memory
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`units each situated such that no other data processing core and no
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`other memory unit is positioned between the respective data
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`processing core and the respective assigned memory unit, the assigned
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`one of the plurality of memory units being accessible by another of
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`the data processing cores via a secondary bus path of the bus system.
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`Of particular significance to the Petition, both independent claims 1 and 16
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`(and, by extension, the challenged dependent claims that depend from claim 1 or
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`claim 16) require the claimed bus system to include “a first structure dedicated for
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`data transfer in a first direction and a second structure dedicated for data transfer in
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`a second direction.”
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`C. Overview of the Prior Art
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`1.
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`Balmer (Ex. 1005)
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`Balmer discloses “an image and graphics processor.” Ex. 1005, Abstract.
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`“The processor is structured with several individual processors all having
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`communication links to several memories.” Id. “A crossbar switch serves to
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`establish the processor memory links. The entire image processor, including the
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`individual processors, the crossbar switch and the memories, is contained on a
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`single silicon chip.” Id. Figure 1 below “show[s] an overall view of the elements
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`of the image processing system.” Id. at 3:24-25.
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`Ex. 1005, Figure 1. The “ISP [“image system processor”] CHIP NODE” in
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`Figure 1 includes “a set of parallel processors 100-103 and a master processor 12
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`connected to a series of memories 10 via a cycle-rate local connection network
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`switch matrix 20 called a crossbar switch.” Id. at 4:45-48. “Transfer processor 11
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`communicates with external memory 15 via bus 21.” Id. at 5:4-5. Figure 4 below
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`“shows a more detailed view of [Figure 1] where the four parallel processors 100-
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`103 are shown interconnected by communication bus 40 and also shown connected
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`to memory 10 via crossbar switch matrix 20.” Id. at 5:62-66.
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`Of particular relevance to the instant Petition, Balmer’s crossbar switch uses
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`“crosspoints” at the intersection of different connections to create data paths
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`between the various processors and memory units at different times during
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`execution. See id. at 5:62-6:15, Fig. 4. As shown in Figure 18 of Balmer
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`(reproduced below), the crossbar switch includes “prioritization circuitry” that
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`implements a “round-robin prioritization scheme” for “connect[ing] processor bus
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`1932 to memory bus 1931.” Id. at 15:44-56, 18:20-54, Figs. 18, 19. Specifically,
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`the crosspoint switch at each intersection of a horizontal and vertical line can be
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`enabled to create a data path between a particular processor and a particular
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`memory during a given clock cycle. See id. at 15:67-18:68.
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`Ex. 1005, Figure 18. “This structure allows data from memories 10-0, 10-2, 10-3
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`and 10-4 to be distributed to any of the processors 100-103.” Id. at 6:49-51.
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`2.
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`Budzinski (Ex. 1006)
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`Budzinski teaches an integrated circuit with four processors, data and control
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`memories, and external interfaces. Ex. 1006 at Abstract. “The processors include
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`reconfigurable connections through a status bus” and “are connected to data,
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`control, and status busses.” Id.
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`More specifically, Budzinski discloses a system in which “multiple 16-bit
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`processors access[] a common memory, with the interconnections between the
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`processors being alterable in software.” Ex. 1006 at 1:5-10. As illustrated in
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`Figure 19 (reproduced and annotated below), “[e]ach processor PR0-PR3 is
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`connected, via its memory mapper 34, to a bus control unit (BCU) 58, which
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`provides interface with the data bus 56. Each BCU 58 is also connected to a
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`corresponding memory scheduler unit (MSU) 68, and each BCU 58 and MSU 68
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`are both connected to a corresponding RAM memory module 60.” Id. at 33:15-22.
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`The BCUs on the data bus provide two alternate paths to memory. First, the BCU
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`provides a “direct[]” path between a processor and “its own memory module.” Id.
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`at 33:23-35. Second, the BCU provides a path between a processor and “a
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`memory module other than its own.” Id. at 33:35-34:13.
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`Ex. 1006 (Budizinski) at Fig. 19.
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`Figures 20 and 21 show the internal structure of each BCU. The BCU
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`includes “three bidirectional switches 178, 180, and 182.” Id. at 34:29-31.
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`Depending on the positions of the bidirectional switch, the BCU (1) enables “each
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`processor [to] access its corresponding memory module 60, in parallel” (id. at
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`34:35-35:1); or (2) connects a memory module to the data bus (for communicating
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`with other processors) (id. at 35:1-10).
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`Ex. 1006 (Budizinski) at Fig. 20.
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`III. CLAIM CONSTRUCTION
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`In an inter partes review, a claim “shall be construed using the same claim
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`construction standard that would be used to construe the claim in a civil action
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`under 35 U.S.C. § 282(b).” 37 C.F.R. § 42.100(b) (2019); see Changes to the
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`Claim Construction Standard for Interpreting Claims in Trial Proceedings Before
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`the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
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`37 C.F.R. § 42.100(b) effective Nov. 13, 2018). Under this standard, claim terms
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`are given their ordinary and customary meaning as would have been understood by
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`a person of ordinary skill in the art at the time of the invention and in the context of
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`the entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed.
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`Cir. 2007).
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`Patent Owner contends that the term “a first structure dedicated for data
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`transfer in a first direction” and “a second structure dedicated for data transfer in a
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`second direction” should be construed as set forth below.
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`A.
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`“a first structure dedicated for data transfer in a first direction” /
`“a second structure dedicated for data transfer in a second
`direction” (Claims 1 and 16)
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`The ’593 patent includes two independent claims, which both recite “a first
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`structure dedicated for data transfer in a first direction” and “a second structure
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`dedicated for data transfer in a second direction.” Consistent with the patent
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`disclosure and the ordinary and customary meaning of the claim language, Patent
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`Owner contends that these terms should be construed as follows:
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` “a first structure dedicated for data transfer in a first direction” should
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`be construed to mean “a first structure assigned exclusively for data
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`transfer in a first direction.”
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` “a second structure dedicated for data transfer in a second direction”
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`should be construed to mean “a second structure assigned exclusively
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`for data transfer in a second direction.”
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`Patent Owner’s construction is consistent with the ordinary and customary
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`meaning of the term “dedicated.” Dictionary definitions from the time of the ’593
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`patent define the term “dedicated” as a thing that is “assigned exclusively” to a
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`particular task or purpose. Ex. 2013 at 173; see also Ex. 2014 at 181 (“assigned to
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`one particular use only”). Thus, the claim language makes clear that the first
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`structure is dedicated (i.e., assigned exclusively) for transferring data in a first
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`direction, and the second structure is dedicated (i.e., assigned exclusively) for
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`transferring data in a second direction. Patent Owner’s construction merely
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`expresses the plain meaning of the claim term “dedicated,” and should be adopted
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`because it is consistent with the ordinary and customer meaning of the claims.
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`Patent Owner’s construction is also consistent with the disclosures of the
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`’593 patent. The ’593 patent discloses that its bus system includes a first structure
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`assigned exclusively for data transfer in a first direction and second structure
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`assigned exclusively for data transfer in a second direction. Indeed, the
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`specification states that to “enable the communication of the cells in two
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`directions, separate bus systems are provided for opposite running directions”:
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`In an additional aspect of the present invention, two-way
`communication of the cells is possible for the logic cell
`array. In bus systems having interline elements, such as
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`drivers and/or registers, directions of travel are defined.
`In order to enable the communication of the cells in two
`directions, separate bus systems are provided for
`opposite running directions. At least in one direction, it
`is once again possible to provide at least two different
`segment lines with shorter and longer segments, in
`particular ones that are once again generally parallel.
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`If the segment lines are separate for the two directions of
`travel, a register may be provided for at least one
`direction of travel. As explained above, the register may
`be provided in the bus system that is routed in the reverse
`direction, i.e., to that bus system, with which signals may
`be routed back from an element output to an element
`input.
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`Ex. 1003 (’593 patent) at 5:30-45.
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`Similarly, the’593 patent provides illustrations of the bus system which
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`clearly show a “first structure” and “second structure” that are assigned exclusively
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`for transfer in a respective first and second direction, which are opposite to each
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`other. For instance, Figure 9 shows a first structure (e.g., FReg) exclusively
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`dedicated for data transfer in a first direction and a second structure (e.g., BReg)
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`exclusively dedicated for data transfer in a second direction:
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`Ex. 1003 (’593 patent) at Fig. 9 (excerpt with color annotations added).
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`The Petition does not propose an express construction for these claim terms.
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`However, the Petition seeks to deviate from the plain and ordinary meaning of the
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`claim language in its application of the prior art. Indeed, as discussed below in
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`Section IV.A, the Petition seeks to read the term “dedicated” out of the claim
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`language by alleging that the claimed “first structure” and “second structure” are
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`disclosed by structures that switch data onto multiple different paths. The Board
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`should adopt Patent Owner’s construction and reject Petitioner’s attempt to read
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`the term “dedicated” out of the claim language. Digital-Vending, 672 F.3d at 1275
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`(“In Phillips, this court reinforced the importance of construing claim terms in light
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`of the surrounding claim language, such that words in a claim are not rendered
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`superfluous.”).
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`IV. THE PETITION FAILS TO DEMONSTRATE A REASONABLE
`LIKELIHOOD THAT ANY CLAIM IS INVALID
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`The ‘593 patent includes two independent claims: Claims 1 and 16. Each of
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`these independent claims recites a bus system that flexibly interconnects the
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`processing cores, memory units, and interface units on the chip. The claimed bus
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`system includes “a first structure dedicated for data transfer in a first direction” and
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`“a second structure dedicated for data transfer in a second direction.”
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`For example, Claim 1 recites:
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`a bus system flexibly interconnecting the plurality of
`processing cores, the plurality of memory units, and the
`at least one interface; wherein:
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`the bus system includes a first structure dedicated
`for data transfer in a first direction and a second
`structure dedicated for data transfer in a second
`direction; and
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`each of at least some of the data processing cores
`includes a physically dedicated connection to at
`least one physically assigned one of the plurality of
`memory units, the assigned one of the plurality of
`memory units being accessible by another of the
`data processing cores via a secondary bus path of
`the bus system.
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`Ex. 1003 (’593 Patent) at 12:19-44 (emphasis added).
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`The prior art relied upon in the Petition does not teach or render obvious the
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`claimed bus system. The Petition presents three grounds: Ground 1 challenges the
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`independent claims based on the combination of Balmer and Hennessy; Ground 2
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`challenges the independent claims based on the combination of Budzinski and
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`Hennessy; Ground 3 challenges the independent claims based on the combination
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`of Budzinski, Hennessy, and Gilbertson. Pet at 4. For Ground 1, the Petition relies
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`solely on the disclosures of Balmer for the limitation of “the bus system includes a
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`first structure dedicated for data transfer in a first direction and a second structure
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`dedicated for data transfer in a second direction.” Pet. at 29-32. And for Grounds
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`2 and 3, the Petition relies solely on the disclosures of Budzinski. Id. at 75-79.
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`Balmer and Budzinski do not disclose the claimed first and second
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`structures.
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`First, as discussed above in Section III, the Board should apply the ordinary
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`and customary meaning of the claim language, which requires that the claimed
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`“first structure” be “dedicated” (i.e., assigned exclusively) “for data transfer in a
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`first direction” and the claimed “second structure” be “dedicated” (i.e., assigned
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`exclusively) “for data transfer in a second direction.” For both Balmer and
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`Budzinski, the Petition alleges that the “first structure” and “second structure” are
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`disclosed by switching structures that switch data onto a plurality of paths. A
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`structure that switches data onto multiple paths, however, is not “dedicated for data
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`transfer in a [first/second] direction.” Put another way, the Petition attempts to
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`improperly read out the “dedicated” language in the claims. This is improper.
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`Digital-Vending Servs., 672 F.3d at 1275 (“In Phillips, this court reinforced the
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`importance of construing claim terms in light of the surrounding claim language,
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`such that words in a claim are not rendered superfluous.”).
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`Second, even under the Petition’s implicit interpretation of the claims, which
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`improperly reads out the “dedicated” limitation, Petitioner fails to identify a “first
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`structure” or “second structure” in Balmer or Budzinski that transfers data in a first
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`and second direction, as required by the claims. Rather, the structures identified
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`by Petitioner transfer data along different paths. Both the claims and the
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`specification of the ’539 patent distinguish between paths and directions.
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`Compare, e.g., Ex. 1003 (’593 patent) at cl. 1 (reciting a “secondary bus path of the
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`bus system”) with id. at cl. 2 (“the at least one secondary bus path includes
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`respective dedicated structures for each of two directions of data transfer”); see
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`also id. at 11:21-35 (describing “forward” and “reverse” registers that may be
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`connected to a “data path”). The Petition fails to identify any structure in Balmer
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`or Budzinski that are dedicated to transfer data in different directions along a given
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`path; indeed, Balmer and Budzinski are silent as to directionality of data.
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`For these reasons, the Board should deny the Petition.
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`A. Balmer Does not Disclose a “First Structure Dedicated for Data
`Transfer in a First Direction” and a “Second Structure Dedicated
`for Data Transfer in a Second Direction”
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`Balmer discloses an “image processor” that uses a conventional “crossbar
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`switch 20,” also referred to as a “switch matrix,” for connecting processors (e.g.,
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`processors 11-12 and 100-103) to memory 10. Ex. 1005 (Balmer) at Abstract,
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`4:60-5:5, 5:48-6:15 Figs. 2, 4. Petitioner points to Balmer’s crossbar switch as the
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`claimed bus system (Pet. at 28-29) and alleges that the crosspoints of the crossbar
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`switch disclose the claimed “first structure dedicated for data transfer in a first
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`direction” and “second structure dedicated for data transfer in a second direction”
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`(Pet. at 30). But the claim language makes clear the crosspoints are not the
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`claimed first or second structure.
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`A crossbar switch is a matrix that contains an array of horizontal and vertical
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`connections. Figure 4 (below) illustrates Balmer’s crossbar switch (yellow):
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`
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`Ex. 1005 (Balmer) at Fig. 4; see also id. at 5:62-66. Places on the crossbar where
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`the connections cross are called “crosspoints.” Id. at 5:66-6:6, 15:44-66, Figs. 4,
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`18; see also Ex. 1001 at ¶ 102.
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`Each crosspoint is a structure comprising a switch capable of creating a data
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`path between a horizontal data line and a vertical data line. For instance, Figure 19
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`of Balmer (below) illu