Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
`
`PACT XPP SCHWEIZ AG
`Patent Owner
`
`U.S. PATENT NO. 8,471,593
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`TABLE OF CONTENTS
`INTRODUCTION ......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 1
`A.
`37 C.F.R. § 42.8(b)(1): Real Party-in-Interest ...................................... 1
`B.
`37 C.F.R. § 42.8(b)(2): Related Matters ............................................... 2
`C.
`37 C.F.R. § 42.8(b)(3): Counsel Information........................................ 2
`D.
`37 C.F.R. § 42.8(b)(4): Service Information ......................................... 2
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.103 ..................................... 3
`IV. CERTIFICATION OF GROUNDS FOR STANDING .............................. 3
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ............... 3
`A.
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested ........... 3
`B.
`37 C.F.R. § 42.104(b)(2): Grounds for Challenge ................................ 3
`C.
`37 C.F.R. § 42.104(b)(3): Claim Construction ..................................... 5
`D.
`37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable ............. 5
`E.
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge .................. 5
`VI. OVERVIEW OF THE TECHNOLOGY ..................................................... 6
`A.
`Processors .............................................................................................. 6
`B.
`Bus Systems .......................................................................................... 6
`VII. OVERVIEW OF THE ’593 PATENT .......................................................... 7
`A.
`The Alleged Problem in the Art ............................................................ 7
`B.
`Prosecution History ............................................................................... 9
`VIII. LEVEL OF ORDINARY SKILL IN THE ART ........................................ 10
`IX. OVERVIEW OF THE PRIMARY PRIOR ART ...................................... 10
`A.
`Balmer ................................................................................................. 11
`B.
`Budzinski ............................................................................................. 12
`C.
`Gilbertson ............................................................................................ 14
`D. Hennessy ............................................................................................. 15
`SPECIFIC GROUNDS FOR PETITION ................................................. 15
`A. Ground I: Challenged Claims Are Obvious In View Of Balmer
`in Combination with Hennessy ........................................................... 16
`
`X.
`
`i
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`1.
`Independent Claims 1, 16 ......................................................... 16
`Dependent Claims 2, 17 ............................................................ 35
`2.
`Dependent Claims 4, 19 ............................................................ 36
`3.
`Dependent Claims 5, 20 ............................................................ 39
`4.
`Dependent Claims 6, 21 ............................................................ 42
`5.
`Dependent Claims 7, 22 ............................................................ 45
`6.
`Dependent Claims 8, 23 ............................................................ 45
`7.
`Dependent Claims 9, 24 ............................................................ 49
`8.
`Dependent Claims 10, 25 .......................................................... 51
`9.
`10. Dependent Claims 11, 26 .......................................................... 53
`11. Dependent Claim 14 ................................................................. 54
`12. Dependent Claim 15 ................................................................. 56
`13. Dependent Claim 27 ................................................................. 58
`Ground II: Challenged Claims Are Obvious In View Of
`Budzinski in Combination with Hennessy .......................................... 60
`1.
`Independent Claims 1, 16 ......................................................... 60
`2.
`Dependent Claims 2, 17 ............................................................ 83
`3.
`Dependent Claims 4, 19 ............................................................ 86
`4.
`Dependent Claims 5, 20 ............................................................ 88
`5.
`Dependent Claims 6, 21 ............................................................ 89
`6.
`Dependent Claims 7, 22 ............................................................ 90
`7.
`Dependent Claims 8, 23 ............................................................ 91
`8.
`Dependent Claims 9, 24 ............................................................ 92
`9.
`Dependent Claims 10, 25 .......................................................... 94
`10. Dependent Claims 11, 26 .......................................................... 96
`11. Dependent Claim 14 ................................................................. 97
`12. Dependent Claim 15 ................................................................. 99
`13. Dependent Claim 27 ............................................................... 101
`Ground III: Challenged Claims Are Obvious In View Of
`Budzinski in Combination with Hennessy and Gilbertson ............... 102
`1.
`Independent Claims 1, 16 ....................................................... 102
`
`ii
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`B.
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`C.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`2.
`Dependent Claims 2, 4-11, 14-15, 17, 19-27 .......................... 105
`XI. CONCLUSION .......................................................................................... 105
`CERTIFICATE OF COMPLIANCE ................................................................ 107
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`
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`In re Dance,
`160 F.3d 1339 (Fed. Cir. 1998) .................................................................... 22, 65
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................ 5
`Statutes
`35 U.S.C. § 102 .......................................................................................................... 3
`35 U.S.C. § 103 .......................................................................................................... 4
`Rules
`37 C.F.R. § 1.68 ......................................................................................................... 6
`37 C.F.R. § 42.8(b) ................................................................................................ 1, 2
`37 C.F.R. § 42.10(b) .................................................................................................. 2
`37 C.F.R. § 42.15(a)(1) .............................................................................................. 3
`37 C.F.R. § 42.103 ..................................................................................................... 3
`37 C.F.R. §42.104(a) .................................................................................................. 3
`37 C.F.R. § 42.104(b) ............................................................................................ 3, 5
`Other Authorities
`MPEP § 2143(F) ...................................................................................................... 92
`
`
`
`iv
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`PETITIONER’S EXHIBIT LIST1
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`Description
`Declaration of Dr. Pinaki Mazumder
`Curriculum Vitae of Dr. Pinaki Mazumder
`U.S. Patent No. 8,471,593 (“Vorbach”)(’593 patent”)
`File History of U.S. Patent No. 8,471,593
`U.S. Patent No. 5,197,140 (“Balmer”)
`European Patent Application 0071727A1 (“Budzinski”)
`U.S. Patent No. 6,240,458 (“Gilbertson”)
`Chuan-lin Wu and Tse-yun Feng, “Interconnection Networks for
`Parallel and Distributed Processing,” IEEE Computer Society Press
`(1984)
`PACT XPP Schweiz AG v. Intel Corp., Case No. 1:19-cv-1006-
`RGA (D. Del.), District Court Joint Claim Construction Chart
`Kenneth J. Thurber and Leon D. Wald, Associative and Parallel
`Processors, 7 Computing. Surveys (1975) (“Thurber & Wald”)
`Declaration of Rachel J. Watters in Support of Public Availability
`of Associative and Parallel Processors (Thurber & Wald)
`John L. Hennessy & David A. Patterson, Computer Organization
`and Design: The Hardware/Software Interface (2d. ed. 1998)
`(“Hennessy”)
`Declaration of Rachel J. Watters in Support of Public Availability
`of Computer Organization and Design: the Hardware/Software
`Interface (2d ed. 1998)
`Philip H. Enslow, Multiprocessors and Parallel Processing, New
`York, NY: John Wiley & Sons (1974) (“Enslow”)
`Declaration of Rachel J. Watters in Support of Public Availability
`of Multiprocessors and Parallel Processing (1974)
`Declaration of Pamela Stansbury in Support of Public Availability
`of Interconnection Networks for Parallel and Distributed
`Processing, (1984)
`
`1 Unless otherwise specified, citations are to the original page, column, and line
`
`1013
`
`1014
`
`1015
`
`1016
`
`numbers in exhibits. Brackets ([]) are used to refer to the sequential page numbers
`
`added to exhibits pursuant to 37 C.F.R. § 42.63(d)(2)(i).
`
`v
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Intel Corporation (“Intel” or “Petitioner”) requests inter partes review (“IPR”)
`
`of claims 1, 2, 4-11, 14-17, 19-27 (“Challenged Claims”) of U.S. Patent No.
`
`8,471,593 ( “’593 patent”) (Ex. 1003).
`
`I.
`
`INTRODUCTION
`The ’593 patent is directed to a bus system for logic cell arrays that enables a
`
`large number of cells to communicate with each other. The claimed invention
`
`employs “dedicated” and “secondary bus path[s]” (segmented busses) that facilitate
`
`communications between processors and memory units. The claimed invention was
`
`well-known in the prior art. Indeed, the ’593 patent acknowledges that segmented
`
`buses—like the “dedicated” and “secondary” bus paths—existed in the prior art, yet
`
`the patent purports to distinguish its alleged invention on the basis that prior-art bus
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`systems “may not work well when integrated on semiconductor chips, such as in
`
`CMOS technology.” Ex. 1003, 2:31-34. As demonstrated in this petition, however,
`
`the patent’s alleged distinction over the prior art would have been obvious to a
`
`skilled artisan. Accordingly, IPR should be instituted, and the Challenged Claims
`
`should be cancelled.
`
`II. MANDATORY NOTICES
`37 C.F.R. § 42.8(b)(1): Real Party-in-Interest
`A.
`Intel is the real party-in-interest for Petitioner.
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`1
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`37 C.F.R. § 42.8(b)(2): Related Matters
`B.
`PACT XPP Schweiz AG (“PACT”) has asserted the ’593 patent in PACT XPP
`
`Schweiz AG v. Intel Corp., Case No. 1:19-cv-1006-JDW (D. Del.). This case may
`
`affect, or be affected by, decisions in these proceedings. Additionally, there is a
`
`pending application that claims priority to the ’593 patent: U.S. Patent Appl. No.
`
`15/488,384 (filed April 14, 2017).
`
`C.
`
`37 C.F.R. § 42.8(b)(3): Counsel Information
`Lead Counsel
`Backup Counsel
`Kevin Bendix
`Robert A. Appleby, P.C.
`Reg. No. 67,164
`Reg. No. 40,897
`kevin.bendix@kirkland.com
`robert.appleby@kirkland.com
`Postal and Hand-Delivery Address:
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`KIRKLAND & ELLIS LLP
`555 South Flower Street
`601 Lexington Avenue
`Los Angeles, CA 90071
`New York, New York 10022
`Telephone: (213) 680-8400
`Telephone: (212) 446-4800
`Facsimile: (213) 680-8500
`Facsimile: (212) 446-4900
`
`Gregory S. Arovas, P.C.
`Reg. No. 38,818
`greg.arovas@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, New York 10022
`Telephone: (212) 446-4800
`Facsimile: (212) 446-4900
`
`
`37 C.F.R. § 42.8(b)(4): Service Information
`D.
`Intel concurrently submits a Power of Attorney, 37 C.F.R. § 42.10(b), and
`
`consents to electronic service directed to Intel_PACT_IPR@kirkland.com.
`
`2
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.103
`
`The undersigned authorizes the Office to charge fees set forth in 37 C.F.R. §
`
`42.15(a)(1) for this Petition to Deposit Account No. 506092. The undersigned
`
`further authorizes payment for any additional fees that may be due in connection
`
`with this Petition to this deposit account.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Intel certifies pursuant to 37 C.F.R. §42.104(a) that the ’593 patent is available
`
`for IPR and Intel is not barred/estopped from requesting IPR challenging the claims
`
`on grounds identified herein.
`
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested
`A.
`Intel challenges claims 1, 2, 4-11, 14-17, 19-27 of the ’593 patent.
`
`37 C.F.R. § 42.104(b)(2): Grounds for Challenge
`B.
`The claims are challenged based on the following references:
`
`1. U.S. Patent No. 5,197,140 (“Balmer”) (Ex. 1005); filed November 17, 1989;
`
`issued March 23, 1993, prior art under §§ 102(a), (b), and (e). 2
`
`
`2 Provisions of 35 U.S.C. § 102 prior to the enactment of the America Invents Act
`
`(AIA) apply to this petition. Any reference to a subsection of 35 U.S.C. § 102
`
`refers to the pre-AIA version of the subsection.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`2. European Patent Application 0071727A1 (“Budzinski”) (Ex. 1006); filed June
`
`23, 1982; published February 16, 1983, prior art under §§ 102(a), (b), (e).
`
`3. U.S. Patent No. 6,240,458 (“Gilbertson”) (Ex. 1007); filed December 22,
`
`1998; issued May 29, 2001, prior art under § 102(e).
`
`4.
`
`John L. Hennessy & David A. Patterson, Computer Organization and Design:
`
`The Hardware/Software Interface (2d. ed. 1998) (“Hennessy”) (Ex. 1012);
`
`published 1998, prior art under §§ 102(a), (b).
`
`None of these references were before the Patent Office during prosecution of
`
`the ’593 patent.
`
`Petitioner requests IPR on the following grounds:
`
`Ground
`
`Claims
`
`Proposed Statutory Rejection
`
`1
`
`2
`
`3
`
`1, 2, 4-11, 14-
`17, 19-27
`1, 2, 4-11, 14-
`17, 19-27
`1, 2, 4-11, 14-
`17, 19-27
`
`Obvious under § 103 in view of Balmer in
`combination with Hennessy
`Obvious under § 103 in view of Budzinski in
`combination with Hennessy
`Obvious under § 103 in view of Budzinski in
`combination with Gilbertson and Hennessy
`
`
`Grounds 1-3 present substantially different discussions of how the Challenged
`
`Claims are unpatentable. Ground 1 discusses the interconnection of multiple
`
`processors and memory utilizing a crossbar, including dedicated paths for certain
`
`memories. Ground 2 discusses bus control units that enable the disclosed bus system
`
`to switch between dedicated paths and a larger data bus. Ground 3 combines the bus
`
`control unit of Ground 2 with certain dedicated connections disclosed in Gilbertson.
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`4
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Grounds 1, 2, and 3 thus present different solutions to the problem of flexibly and
`
`efficiently interconnecting computer processors with memory over a bus system, and
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`all distinctly render obvious the Challenged Claims of the ’593 patent.
`
`37 C.F.R. § 42.104(b)(3): Claim Construction
`C.
`Terms in an IPR should be construed in accordance with the principles set
`
`forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005). See 37 C.F.R.
`
`§ 42.104(b)(3).
`
`In the co-pending District Court Action, the Patent Owner proposed that the
`
`preambles of claims 1 and 16 are limiting. Ex. 1009 (Joint Claim Construction
`
`Chart). Petitioner demonstrates how the prior art renders obvious the Challenged
`
`Claims regardless of whether the preambles are limiting. Consequently, the Board
`
`does not need to decide this issue to institute.
`
`Petitioner asserts no other terms require construction for purposes of this
`
`Petition. To the extent Patent Owner hereafter asserts additional terms require
`
`construction, Petitioner reserves the right to respond.
`
`37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable
`D.
`A detailed explanation of how the Challenged Claims are unpatentable is
`
`provided in Section XI.
`
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge
`E.
`A list of exhibits is provided at the beginning of this Petition. The relevance
`
`of this evidence and the specific portions supporting the challenge is provided in
`
`5
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Section IX. Intel submits a declaration of Dr. Pinaki Mazumder (Ex. 1001) in
`
`support of this Petition under 37 C.F.R. § 1.68.
`
`VI. OVERVIEW OF THE TECHNOLOGY
`Processors
`A.
`A general-purpose processor retrieves an instruction and data stored in an
`
`external memory and decodes the instruction to perform logical and arithmetic
`
`operations on that data. Ex. 1001 ¶¶45-53. This is generally accomplished by an
`
`arithmetic logic unit (“ALU”), which executes the instructions. Id., ¶¶45. As an
`
`example, a “32-bit architecture” will receive a sequence of 32-bit instructions in
`
`which the first 8 bits define the instruction, and the remaining bits correspond to: the
`
`data to be operated upon, an address where data can be stored, or other information.
`
`Id., ¶¶45. Processors use caches, registers, and other memory components to
`
`temporarily store data that is being processed. Id., ¶¶45-53.
`
`Bus Systems
`B.
`Within data processing devices (e.g., multiprocessors), components
`
`communicate with each other using a system of physical interconnections (e.g.,
`
`wires) referred to as a bus or “bus system.” Ex. 1001 ¶¶54-67. A bus system
`
`facilitates the transfer of data or instructions among processors, memory, and
`
`external devices. Id. The simplest bus systems provide permanent interconnections
`
`that do not change over time. On the other hand, reconfigurable bus systems—
`
`which can assemble or disassemble interconnections as needed and thus provide
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`flexibility—have existed since at least the late 1970s. Ex. 1001 ¶¶54-67; e.g.¸ Ex.
`
`1010 (Thurber & Wald, Associative and Parallel Processors, 7 Computing. Surveys
`
`(1975)), 215. It has long been recognized that reconfigurable interconnections
`
`promote efficiency and parallel processing in computer systems. Ex. 1001 ¶¶54-67.
`
`One well-known method of implementing a reconfigurable bus system is to divide
`
`buses into segments and selectively activate or deactivate each segment to form a
`
`communication path from one component to another. Ex. 1001 ¶¶54-67.
`
`VII. OVERVIEW OF THE ’593 PATENT
`The ’593 patent issued from U.S. App. No. 13/289,296, filed November 4,
`
`2011, claiming priority to U.S. Patent Application No. 60/238,855, filed on October
`
`6, 2000. Ex. 1003, Cover, Cert. of Correction. For purposes of this Petition only,
`
`Petitioner does not contest that the ’593 patent is entitled to the October 6, 2000
`
`priority date.
`
`A. The Alleged Problem in the Art
`The ’593 patent describes the present invention as “relat[ing] to logic cell
`
`arrays.” Ex. 1003, 1:18. The patent notes that in systems utilizing logic cell arrays,
`
`there exists “the need to optimize designs, which, in particular can be structured in
`
`a space-saving manner…and/or can be operated in an energy-saving manner.” Ex.
`
`1003, 1:46-49. It further notes that “conventional systems” suffer from the difficulty
`
`where “a large number of cells have to communicate with each other,” which can be
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`particularly problematic “if a cell is supposed to further process the results from
`
`another cell, e.g., by linking of the result obtained there to results obtained from one
`
`or more other cells.” Ex. 1003, 1:51-58.
`
`The ’593 patent acknowledges one prior-art solution to this problem: a bus
`
`system where “bus lines may be routed to all receivers,” and then either each
`
`processor is assigned a time-slice to use the bus or control signals are used to
`
`“ensure[] that only those receivers[] that are supposed to receive the data” respond.
`
`Ex. 1003, 1:66-2:4. According to the patent, this arrangement is allegedly less
`
`effective when numerous components need access to the bus “because the
`
`communication of data must wait…until the bus has been released by other units[.]”
`
`Ex. 1003, 2:4-13. Alternatively, the ’593 patent describes another prior-art solution
`
`in which buses are segmented, consisting of sub-bus systems that connect various
`
`components. Ex. 1003, 2:18-23. The ’593 patent critiques such segmented bus
`
`systems because they “may not work well when integrated on semiconductor
`
`chips…where the structure is typically complex and the operation is energy
`
`inefficient.” Ex. 1003, 2:31-34.
`
`The ’593 patent allegedly solves these problems through a bus system that
`
`“includes different segment lines having shorter and longer segments for connecting
`
`two points in order to be able to minimize the number of bus elements traversed
`
`between separate communication start and end points.” Ex. 1003, 2:38-44. Longer
`
`8
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`bus segments can bypass “long paths in a logic cell array,” whereas short segment
`
`lines “ensure[] that all points are addressable as needed.” Ex. 1003, 2:45-50. But
`
`this was not a new solution. Multiple prior art references—which the Examiner did
`
`not consider—render obvious the claimed bus system.
`
`Prosecution History
`B.
`U.S. Patent Application No. 13/289,296 ( “’296 application”)—which issued
`
`as the ’593 patent—was filed on November 4, 2011, claiming priority to U.S. Patent
`
`application No. PCT/EP01/11593 on October 8, 2001. U.S. Patent No. 8,471,593
`
`File History (“’593 File History”) (Ex. 1004), 1-34. The applicant filed a
`
`preliminary amendment in November 2011, “cancel[ling]…claims 1-37, add[ing]
`
`new claims 38-67, and amend[ing] the title,” without adding new matter. Id., 35-42.
`
`Notably, the cancelled claims did not relate to “data processor[s]” or “data
`
`processing cores,” but instead claimed a “configurable computing processor chip”
`
`comprising “a plurality of programmable gate array (PGA) elements” and “a
`
`plurality of dedicated multi-bit ALU elements.” Id., 18. Patent Owner then filed a
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`9
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
`
`Request for Certificate of Correction to claim benefit and priority to U.S. Patent
`
`Application Ser. No. 60/238,855, which was filed on October 6, 2000.3
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`A POSITA at the time of the alleged invention would have had at least M.S.
`
`in electrical engineering or computer engineering (or equivalent experience), and at
`
`least three years of experience with processor design and memory architecture. Ex.
`
`1001 ¶75.
`
`IX. OVERVIEW OF THE PRIMARY PRIOR ART
`The claimed bus system―connecting multiple processors and memory units
`
`with bus segments of varying lengths―was known or obvious in view of the art
`
`before the ’593 patent’s priority date (“Priority Date”). Balmer in combination with
`
`Hennessy (Ground 1), Budzinski in combination with Hennessy (Ground 2), and
`
`Budzinski in combination with Hennessy and Gilbertson (Ground 3) teach
`
`
`3 During prosecution, Patent Owner filed a Request for Certificate of Correction to
`
`claim benefit and priority to U. S. Patent Application Ser. No. 60/238,855, filed on
`
`Oct. 6, 2000. Petitioner does not agree that Patent Owner is entitled to this priority
`
`date; however, the prior art presented in this Petition predates Patent Owner’s
`
`earliest asserted priority date, so the Board does not need to decide this issue to
`
`institute.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`substantially similar bus interconnect structures that render the Challenged Claims
`
`obvious to a POSITA.
`
`A. Balmer
`Balmer describes a multiprocessor system with a bus system that allows a
`
`memory to be accessed via multiple bus paths. Ex. 1005, Abstract. As shown in
`
`Figure 4, Balmer’s bus system (yellow) allows processors (blue) to access their own
`
`memories (purple) using paths connecting to the processors’ local port (L), as well
`
`as memories of other processors using paths connecting to the processors’ global
`
`port (G). Id.
`
`
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`11
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Id., Figure 4, 6:6-19.4 As Balmer explains, “any processor can access any of a
`
`number of memories, while certain memories are dedicated to handling instructions
`
`for the individual processors.” Id., 3:11-17.
`
`Budzinski
`B.
`Budzinski discloses a multiprocessor system with a reconfigurable
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`interconnect system that allows a memory to be accessed via multiple bus paths. Ex.
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`1006, Abstract, 1:5-10. Figure 19 shows Data Bus (green) consisting of multiple
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`bus paths, including a dedicated path that allows processors (blue) to access their
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`own memories (purple), as well as a secondary bus path that allows the processors
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`to access memories associated with other processors:
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`
`4 Highlighting and color coding throughout petition added for clarity.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Ex. 1006, Fig. 19.
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`Budzinski’s bus control units (“BCUs”) can select to transfer/receive data
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`from either a dedicated connection with the corresponding RAM Memory module
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`or the data bus. As Budzinski discusses, “[w]hen a processor accesses its own
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`memory module 60, the processor is directly connected through its BCU 58 to its
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`MSU [memory scheduler unit] 68.” Id., 33:23-25. “[T]he BCUs 58 [shown below
`
`in Figure 20] play a crucial role in permitting all processors to access the respective
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`adjacent memory module 60, while also permitting each processor to access any
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`other remote memory module over the data bus 56.” Id., 34:25-28.
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`Id., Figure 20.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`C. Gilbertson
`Gilbertson also discloses a multiprocessor system with an interconnect system
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`that allows a memory to be accessed via multiple bus paths. In Gilbertson, “one or
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`more Memory Storage Units (MSUs)” and “one or more Processing Modules
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`(PODs)” are connected so that, “[e]ach unit in MSU 110 is interfaced to all
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`PODs…via a dedicated, point-to-point connection referred to as an MSU Interface
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`(MI).” Ex. 1007, 5:38-55. “Each MI provides the respective POD 120 direct access
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`to data stored in the respective MSU 110.” Id.
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`Ex. 1007, Fig. 1 (showing processors (blue), bus interconnect (yellow), interface
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`(orange), and memory (purple)).
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`D. Hennessy
`Hennessy is a textbook titled Computer Organization and Design, published
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`in 1998. It covers topics including processor architecture and bus systems that
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`interconnect processors with other processors, memory, and I/O. Hennessy’s
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`content reflects the knowledge that a POSITA would have had before the Priority
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`Date. For example, Hennessy explains that a bus is “a shared communication link,
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`which uses one set of wires to connect multiple subsystems,” and that versatility and
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`low cost are two major advantages of the bus organization:
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`By defining a single connection scheme, new devices can easily be
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`added, and peripherals can even be moved between computer systems
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`that use the same kind of bus. Furthermore, buses are cost-effective
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`because a single set of wires is shared in multiple ways.
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`Ex. 1012, 655. Hennessy also discusses bus protocols to define “how a word
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`or block of data should be communicated on a set of wires.” Id. at 673.
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`X.
`
`SPECIFIC GROUNDS FOR PETITION
`The sections below demonstrate in detail how the prior art renders obvious
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`the Challenged Claims. Secondary considerations do not support a finding of
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`nonobviousness. Ex. 1001 ¶197. Should PACT hereafter submit alleged evidence
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`relating to secondary considerations, Intel respectfully requests an opportunity to
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`respond.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`In view of the substantial overlap in claims, often including verbatim the same
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`limitations, we address analogous claims together in each of the grounds below.
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`A. Ground I: Challenged Claims Are Obvious In View Of Balmer in
`Combination with Hennessy
`Independent Claims 1, 16
`1.
`a.
`“A data processor on a chip comprising:”
`Balmer discloses this limitation. Balmer describes “[a] multiprocessor
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`system” whereby “[t]he processor is structured with several individual processors
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`all having communication links to several memories.”5 Ex. 1005, Abstract; Ex.
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`1001, ¶89. Balmer’s invention is “contained on a single silicon chip.” Id.
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`b.
`
`“a plurality of data processing cores, each of at least
`some of the processing cores including:”
`Balmer discloses this limitation. Balmer describes “[a] multiprocessor
`
`
`
`system” in which “[t]he processor is structured with several individual processors
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`all having communication links to several memories.” Ex. 1005, Abstract. As
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`shown below in Figures 1 and 4 (illustrating the same embodiment), Balmer’s
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`“several individual processors” (“parallel processor” or “PP”; highlighted in blue)
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`correspond to the “data processing cores” since “processors” were often referred to
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`as “cores” at the time of the ’593 patent. Ex. 1001, ¶90; Ex. 1005, 35:42-47 (the
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`parallel processors provide “a formidable data processing capability”).
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`
`5 All emphasis is added unless otherwise stated.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`Ex. 1005, Fig. 1.
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`
`
`
`
`
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`Id., Fig. 4; id., Fig. 17, 4:45-59, 15:29-41, 35:40-56.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`c.
`
`“at least one arithmetic logic unit that supports at least
`division and multiplication of at least 32-bit wide data;
`and”
`Balmer, either alone or in combination with Hennessy, renders obvious this
`
`
`
`limitation. Balmer discloses a 32-bit ALU and separate multiply/divide logic that a
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`POSITA at the time of the ’593 patent would have been motivated to incorporate
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`into the ALU. Ex. 1001, ¶91. For example, each of Balmer’s parallel processors
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`includes “three main units”: “the program flow control unit 3002, the address unit
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`3001 and the data unit 3000.” Ex. 1005, 37:31-34. “Data unit 3000 (shown in FIG.
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`33) contains 8 multiport data registers 3300, a full 32-bit barrel shifter 3301, a 32-
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`bit ALU 3302, left-most-1 right-most-1 and number-of-1s logic 3303, divide
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`iteration logic and a 16x16 single-cycle multiplier 3304.” Id., 38:33-37.
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`
`
`Id., Fig. 33; id., 56:64-68.
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`
`
`
`
`A POSITA would have been motivated to combine Balmer’s divide iteration
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`logic and multiplier (yellow) with the ALU (pink) to form a single block that
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`“supports at least division and multiplication of at least 32-bit wide data.” Ex. 1001,
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`¶¶90-92. First, Balmer pre-dated the ’593 patent by nearly 10 years, and by the
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`Priority Date, ALUs with multiplication and division functionality were commonly
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`used throughout the industry. Ex. 1001, ¶93. For example, Hennessy discloses a
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`32-bit ALU design that was well-known and could perform multiplication and
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`Petition for Inter Partes Review of U.S. Patent No. 8,471,593
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`division. Ex. 1012, 234-241 (s