`ANALANA
`US005197140A
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`115
`United States Patent
`5,197,140
`[11] Patent Number:
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`[45] Date of Patent: Mar. 23, 1993
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`Balmer
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`[54] SLICED ADDRESSING MULTI-PROCESSOR
`AND METHOD OF OPERATION
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`[75]
`Inventor: Keith Balmer, Bedford, England
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`[73] Assignee: Texas Instruments Incorporated,
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`Dallas, Tex.
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`[21] Appl. No.: 437,946
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`[22] Filed:
`Nov. 17, 1989
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`[51]
`Int. Cho oe GO6F 12/00; GO6F 15/00;
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`GO06F 7/33; GO6F 7/50
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`[82] ULS. C1. cece ectetsteeeeteterens 395/400; 395/300;
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`364/749; 364/786; 364/787
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`[58] Field of Search............... 395/400, 800, 163, 166;
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`364/749, 786, 787
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`[56]
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`Image Processing”, Lew Brown, Electronic Imaging
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`°87, International Electronic Imaging Exposition and
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`Conference, Nov. 2, 1987, pp. 1057-1060.
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`“VITec Parallel C Compiler”, by Butler, Electronic
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`Imaging °89, International Electronic Imaging Exposi-
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`tion and Conference, Nov. 1989, pp. 741-747.
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`“A Single Board Image Computer with 64 Parallel
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`Processors” by Stephen Wilson, Electronic Imaging
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`°87, International Electronic Imaging Exposition &
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`Conference, Nov. 2, 1987, pp. 470-475.
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`“The Androx Parallel Image Array Processor”, Wayne
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`Threatt, Electronic Imaging °87, International Elec-
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`tronic Imaging Exposition & Conference, Nov.2, 1987,
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`pp. 1061-1064.
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`“Design of a Massively Parallel Processor”, Kenneth
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`Batcher, IEEE Transactions on Computers, v. C-29,
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`References Cited
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`No.9, Sep. 1980, pp. 836-840.
`U.S. PATENT DOCUMENTS
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`“High Resolution Frame Grabbing and Processing
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`3,260,840 7/1966 King .0......cecceeeesseeseeteereeees 364/787
`Through Parallel Architecture”, Daniel Crevier, Elec-
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`8/1972 Hanslip ..........essseesenreees 364/749
`3,683,163
`tronic Imaging °87, International Electronic Imaging
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`3,728,532 4/1973 PLyOTD ....sscssscseeecsereesentersenens 364/787
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`Exposition & Conference, Nov. 2, 1987, pp. 681-682.
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` 4,562,535 12/1985 Vincent et al. occ 395/325
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`(List continued on next page.)
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`4,644,496
`2/1987 Andrewsoc
`sesessceteeees 395/800
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`4,747,043 5/1988 Rodman ......cccsceereeesee 395/425
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`8/1989 Lumelsky«0.0.0...
`cscs 395/163
`4,860,248
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`Primary Examiner—Joseph L. Dixon
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`4,888,679 12/1989 Fossum etal. .
`wee 395/800
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`Assistant Examiner—Michael A. Whitfield
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`4,953,101 8/1980 Kelleher et al.0...eee 395/166
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`Attorney, Agent, or Firm—Robert D. Marshall, Jr.;
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`§,101,338
`3/1992 Fujiwara et al. vue 395/400
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`James C. Kesterson; Richard L. Donaldson
`OTHER PUBLICATIONS
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`ABSTRACT
`[57]
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`“The Connection Machine”, W. D. Hillis, published in
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`A multi-processor system arranged, in one embodiment,
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`The MIT Press (1985).
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`as an image and graphics processor. The processor is
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`“Handling Real Time Images Comes Naturally to Sys-
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`structured with several individual processors all having
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`tolic Array Chip”, by Hannaway,Shea, Bishop in Elec-
`communication links to several memories. An address-
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`tronic Design, pp. 289-300, Nov. 1984.
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`ing scheme, called sliced addressing, is used to spread
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`“Systolic Array Chip Recognizes Visual Patterns
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`contiguous related data over several memories so that
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`Quicker Than a Wink”, by W. W. Smith, P. Sullivan, in
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`the data can be concurrently accessed by several pro-
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`Electronic Design, pp. 257-266, No. 29, 1984.
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`cessors. A crossbar switch serves to establish the pro-
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`“Real Time 3D Object Tracking in a Rapid Prototyping
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`cessor memory links. The entire image processor, in-
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`Environment”, Robert J. Gove, Electronic Imaging
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`cluding the individual processors, the crossbar switch
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`88, Oct. 4, 1989, pp. 54-59.
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`“Integration of Symbolic and Multiple Digital Signal
`and the memories, is contained on a single silicon chip.
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`Processors with the Explorer/Odyssey for Image Pro-
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`cessing and Understanding-Applications”, Robert J.
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`Gove, Proceedings to the IEEE International Sympo-
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`sium of Circuits and Systems, pp. 968-971 (May, 1987).
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`“The Use of Parallel-Processing Computers in Digital
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`13 Claims, 35 Drawing Sheets
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`SUCE MASK BUS FROM PROCESSOR REGISTER
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`INTEL - 1005
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`5,197,140
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`Page 2
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`OTHER PUBLICATIONS
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`“Multiple Digital Signal Processor Environment for
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`Intelligent Signal Processors by Gasset al.”, Proceed-
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`ings of the IEEE, v. 75, No. 9 (Sep. 1987) pp.
`1246-1259.
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`“Architecture and Design of the Mars Hardware Ac-
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`celerator”, AGRA Wall, in 24th ACM/IEEE Design
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`Automation Conference (1987), pp. 101-107.
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`‘*A 200 MIPS Single-Chip IKFFY Processor”, by oO.
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`‘Brien, Mather & Holland, IEEE International Solid-S-
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`-tate Circuits Conference, Feb. 16, 1989, pp. 166-167.
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`“An Architectural Study, Design and Implementation
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`of Digital Image Acquisition Processing and Display
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`Systems with Micro-Processor-Based Personal Com-
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`puters and Charge-Coupled Device Imaging Technol-
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`ogy”, a Dissertation by Robert J. Gove, SMU, May 17,
`1986.
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`““A Medium Grained Parallel Computer for Image Pro-
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`| cessing” by R. S. Cok, published by Digital Technology
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`‘Center, Eastman Kodak Co., Rochester, N.Y., pp.
`927-936.
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`INTEL - 1005
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`U.S. Patent
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`Mar. 23, 1993
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`Sheet 1 of 35
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`5,197,140
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`MIMD COMMMUNICATION/SYNCHRONIZATION NETWORK
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`PACKET REQUEST
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`Sheet 2 of 35
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`FIG.
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`U.S. Patent
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`Mar. 23, 1993
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`Sheet 3 of 35
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`MASTERPROCESSOR
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`Sheet 4 of 35
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`U.S. Patent
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`Sheet 5 of 35
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`FIG. 18
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`U.S. Patent
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`Mar. 23, 1993
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`Sheet 6 of 35
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`U.S. Patent
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`Mar.23, 1993
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`Sheet 7 of 35
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`5,197,140
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`U.S. Patent
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`Mar. 23, 1993
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`Sheet 8 of 35
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`U.S. Patent
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`Mar,23, 1993
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`INTEL - 1005
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`INTEL - 1005
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`

`

`
`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`Sheet 11 of 35
`
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`5,197,140
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`
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`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 12 of 35
`
`5,197,140
`
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`

`U.S. Patent
`
`Mar.23, 1993
`
`Sheet 13 of 35
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`5,197,140
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`

`
`U.S. Patent
`
`
`
`
`
`Mar.23, 1993
`
`
`
`Sheet 14 of 35
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`
`5,197,140
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`6-61
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`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 15 of 35
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`5,197,140
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`INTEL - 1005
`
`INTEL - 1005
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`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 16 of 35
`
`
`5,197,140
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`
`
`
`PARALLEL
`PROCESSOR iTT—— T3100
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`DATA UNIT
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`FIG. 30
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`INTEL - 1005
`
`INTEL - 1005
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`

`

`U.S. Patent
`
`
`
`
`Mar, 23, 1993
`
`
`
`
`Sheet 17 of 35
`
`
`5,197,140
`
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`
`
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`

`

`U.S. Patent
`
`
`
`
`Mar.23, 1993
`
`
`
`
`
`Sheet 18 of 35
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`
`5,197,140
`
`
`
`
`ADDRESS UNIT
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`FIG. 32
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`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 19 of 35
`
`
`5,197,140
`
`
`
`Sf Sea ee ee eee SE ee Se SS eeeeee
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`INTEL - 1005
`
`INTEL - 1005
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`

`

`U.S. Patent
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 20 of 35
`
`
`5,197,140
`
`
`
`SIMD PAUSE
`
`
`
`
`FIG. 35
`
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`Anm — NO MASTER PHASE OF THE ADDRESS UNIT, THUS NO REGISTER MODIFY.
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`Exb — CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
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`COMPLETE INTO TEMPORARY LATCHES, MASTER PHASE OF DATA UNIT
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`Enm — NO MASTER PHASE OF DATA UNIT.
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`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
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`Egl - CONTENTION DETECTED ON BOTH GLOBAL AND LOCAL BUSES.
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`PIPE NOT LOADED.
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`Eg - CONTENTION DETECTED ON GLOBAL BUS.
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`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`
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`DATA UNIT PERFORMS {TS ALU/MPY OPERATIONS.
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`Anm — NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTER NOT MODIFIED.
`
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`NO MASTER
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`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar, 23, 1993
`
`
`
`
`Sheet 21 of 35
`
`
`5,197,140
`
`
`
`F
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`Fsa — START ADDRESS OF LOOP.
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`LOOP COUNTER NOT ONE. LOAD PC
`Fer — END ADDRESS, REPEAT LOOP.
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`WITH START ADD.
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`LOOP COUNTER IS ONE.
`Fen — END ADDRESS, NO-REPETTION.
`PC
`
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`INCREMENTS NORMALLY.
`
`FIG. 37
`
`
`
`
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`FIG. 38
`
`
`
`
`
`|
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`SIMD BRANCH—TAKEN
`
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`Fd2 pc:=ba
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`ret:=pc+1
`
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`
`
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`Epc — COPY PC+1 INTO RET.
`
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`
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`
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`
`
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`INSTRUCTION FETCH.
`
`
`
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`
`Fd2 — DELAY SLOT 2 INSTRUCTION FETCH.
`
`
`
`
`Fba — FETCH INSTRUCTION FROM BRANCH ADDRESS.
`
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`* — INTERRUPTS LOCKED OUT.
`
`
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`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar, 23, 1993
`
`
`
`
`Sheet 22 of 35
`
`
`5,197,140
`
`
`
`
`
`|
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`...
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`SIMD “MASTER” PP TO “SLAVE” PP INTERRUPT SIGNAL
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`Apv — CALCULATE INTERRUPT VECTOR ADDRESS.
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`Epv — COPY PC TO RET.
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`
`
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`Fpr - PSEUDO INSTRUCTION.
`(PUSH RET).
`
`
`
`
`Apr — CALCULATE STACK PUSH ADDRESS.
`
`
`
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`
`Epr — PUSH RET ONTO STACK.
`
`
`
`
`
`Fps — PSEUDO INSTRUCTION.
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`
`
`
`
`Aps — CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`
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`
`
`Eps - PUSH SR ONTO STACK.
`CLEAR S,
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`
`
`
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`
`Fin — FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`
`
`
`
`
`
`
`
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`—- SYNC,
`INTERRUPTS AND LOOPING DISABLED UNTIL AFTER SR HAS BEEN PUSHED.
`$
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`
`
`
`
`
`
`
`NEITHER OF FIRST TWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`
`
`
`
`
`
`FIG. 39
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`Sheet 23 of 35
`
`
`5,197,140
`
`
`
`SIMD + MASTER’ PP TO “SLAVE” PP's INTERRUPT SIGNAL
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`
`
`
`
`
`Int Fps|Aps|Eps
`
`
`
`
`
`$Fin|
`IN
`A
`E
`
`
`
`
`Slave $F|A
`
`PP
`
`
`
`
`
`
`
`
`
`
`
`peti! peti! peti! pe|pe|pe|pe}pe!pe|peti
`
`
`
`
`Fid - IDLE INSTRUCTION FETCHED.
`
`
`
`
`
`
`
`
`PIPELINE NOT LOADED.
`Frm - NO MASTER PHASE ON INSTRUCTION FETCH.
`
`
`
`
`
`
`
`
`
`Anm — NO MASTER PHASE ON INSTRUCTION FETCH. ADDRESS REGISTERS NOT MODIFIED.
`
`
`
`
`
`
`
`
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT OPERATIONS
`
`
`
`
`
`
`
`
`
`KILLED
`
`
`
`
`
`Enm ~ NO MASTER PHASE IN DATA UNIT.
`
`
`
`Int - INTERRUPT OCCURS.
`EtL - TEMPORARY LATCH DATA (LOAD5) COMPLETEwr0 DESTINATION REGISTER(S).
`
`
`
`
`
`
`
`
`Fpv — PSEUDO INSTRUCTION.
`(PC TO RET. VECTORETCH INTO PC).
`
`
`
`
`
`
`DATA UNIT PERFORMS ITS ALU/MPY OPERA
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Apy - CALCULATE INTERRUPT VECTOR ADDRESS.
`
`
`
`
`
`
`
`
`Eov — COPY PC TO RET.
`FETCH INTERRUPT VECTOR INTO PC.
`
`
`
`
`
`Fpr - PSEUDO INSTRUCTION.
`(PUSH RET).
`
`
`
`
`Aor - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`Epr — PUSH RET ONTO STACK.
`
`
`
`
`Fps - PSEUDO INSTRUCTION.
`(PUSH SR).
`
`
`
`
`Aps - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`
`
`
`
`Eps - PUSH SR ONTO STACK.
`| AND CLD BITS IN SR.
`CLEAR S,
`
`
`
`
`
`
`Fin - FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`—
`
`
`
`
`
`
`
`
`
`
`$¢ — SYNC,
`INTERRUPTS AND LOOPING DISABLED UNTIL AFTER SR HAS BEEN PUSHED.
`
`
`
`
`
`
`
`
`
`NEITHER OF FIRST TWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`
`
`FIG. 40
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 24 of 35
`
`5,197,140
`
`
`
`
`FIG. 47
`
`
`
`|
`|
`
`
`
`INCOMING SYNC SIGNAL
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PC UNALTERED.
`PIPE NOT LOADED.
`Fns — NO SYNC CONDITION.
`
`
`
`
`
`
`
`
`Anm — NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTERS NOT MODIFIED.
`
`
`
`
`
`
`
`
`Exb — CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`
`
`
`
`
`
`
`
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT
`
`
`OPERATIONS KILLED.
`
`
`
`
`
`Enm — NO MASTER PHASE IN DATA UNIT.
`
`
`
`
`
`
`
`
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESIGNATION REGISTER(S).
`
`
`
`
`
`
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`
`
`
`
`
`LOADS:
`
`
`
`
`
`(ASSUMING NO SIGN—EXTENSION)
`
`
`
`FIG.
`
`
`
`42
`
`
`
`
`
`SOURCE DATA:
`
`0000h =
`
`0004h =
`
`
`
`DESTINATION
`
`=
`
`
`BYTE NO.
`
`3210
`
`DCBA
`
`HGFE
`
`2223
`
`(MEMORY)
`
`
`
`(REGISTER)
`
`
`
`ADD.
`
`
`16-BiT
`
`
`
`
`REG VALUE
`_LOADS...
`
`
`
`OOBA
`0000h OOBA
`
`
`
`
`OOBA
`0002h ----
`
`
`
`00O0ih ---B ?778
`
`
`
`§=0003)h OOC-
`ODOCB
`
`
`
`0002h OODC OdDC
`
`
`
`§«=60004h ----
`OODC
`
`
`
`0003h ---D ?770D
`
`
`
`
`O0005h OOE-
`OOED
`
`
`oP.
`
`LO
`LOU
`
`
`
`
`LD
`LOU
`
`
`LD
`LOU
`
`
`
`
`
`
`LD
`LOU
`
`
`
`
`OP.
`
`LD
`LDU
`
`
`
`
`LD
`LDU
`
`
`
`LD
`LDU
`
`
`
`
`LD
`LU
`
`
`
`ADD.
`
`
`
`0000h
`
`—0004h
`
`
`
`
`
`03h
`
`—0007h
`
`000th
`05h
`
`02h
`—0006h
`
`32-BIT
`
`
`
`
`DCBA
`
`
`
`
`
`
`
`
`REG VALUE
`
`
`
`
`
`DCBA
`
`DCBA
`
`?0CB
`
`EDCB
`
`
`??D0C
`
`FEDC
`
`22??0D
`
`GFED
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 25 of 35
`
`5,197,140
`
`
`
`STORES:
`
`
`
`OP.
`
`
`
`
`ST
`
`ADD.
`
`
`
`0000h
`
`
`
`
`
`
`
`
`SOURCE DATA: = DCBA
`
`
`BYTE NO
`
`
`
`
`DESTINATION DATA = 3210
`o000h
`22722
`=
`
`
`
`
`000th =
`22?
`
`
`
`
`
`
`STORES...
`
`OOBA
`
`0004h
`
`??BA
`2222
`
`27BA
`222?
`
`(REGISTER)
`
`
`
`(MEMORY)
`
`32-BIT
`
`
`
`
`STORES...
`
`DCBA
`
`ADD.
`
`
`
`0000h
`
`
`
`
`OP.
`
`
`ST
`
`REG VALUE
`
`
`
`
`
`STU
`
`
`
`0002h
`
`
`----
`
`STV
`
`
`
`0004h
`
`
`
`
`
`
`
`
`ST
`
`
`000th
`
`
`--A-
`
`ST
`
`
`
`0001h
`
`
`
`
`
`
`
`0005h
`
`
`
`?A??
`2927?
`
`
`
`
`
`
`
`
`
`
`B--- BA?? STU=0006h
`0004h
`STU
`
`
`222?
`
`
`
`
`
`Y~arvrmOYOVYMOE
`
`
`
`
`
`
`
`VOpw>CU°VVvOeovod2p>YY>YVoro
`
`STU
`
`
`
`0003h
`
`
`
`
`-B--
`
`
`
`?7A?
`2272?
`
`?BA?
`2222
`
`ST
`
`
`
`
`
`
`
`
`ST
`
`0002h
`
`
`
`
`-A--
`
`ST
`
`
`
`0002h
`
`
`
`
`
`ST
`
`
`
`
`0003h
`
`STU
`
`
`
`0005h
`
`
`
`
`
`
`A--- A222
`
`2222
`
`
`
`---B A???
`
`??2B
`
`ST
`
`
`
`0003h
`
`
`
`
`
`STU
`
`
`
`0007h
`
`
`
`
`
`
`
`
`
`
`
`VrVr,VoOvDVOVOVOVS
`
`Ovvw
`
`
`
`
`
`
`
`FIG. 48
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 26 of 35
`
`5,197,140
`
`ADD WITH SATURATE
`
`ADDM
`MRCM
`
`DO, D1, 02
`D2, D3, 02
`
`- MAXIMUM
`
`TRANSPARENCY
`
`SUBM
`MRCM
`
`DO, D1, D2
`DO, D1, D2
`
`-CNPM
`MRGM
`
`DO, D1
`DO, D2, D3
`
`pO = 89 23 CD 67
`DO = 89 23 CD 67
`DO = 89 23 CD 67
`(-)D1 = 23 23 23 23
`-Di = 01 AB 45 EF
`+D1 = 01 AB 45 EF
`
`(= 66 00 8A 44)
`D2: = 88 67 88 67
`D2: = BA CE 12 56
`
`MFLACS: = 22 22.22.23 -MFLAGS: = 22 22.97.25©MFLAGS: = 22 72 2? 24
`D2 = BA CE 12 56
`DO = 89 23 CD 67
`DO = 89 23 CD 67
`D3 = FF FF FF FF
`DT = O1 AB AS EF
`D2 = 87 65 43 21
`D2: = 8A CE FF FF
`02: = 89 AB CD EF
`D3: = 89 65 CD 67
`emer eee eee eee wee me cam ree es en eee ree ee ee ee ee eee eee ce cm eee ee ee ee ee ee ee ee ee ee ee ee ee
`
`COLOUR EXPANSION
`
`COLOUR COMPRESSION
`
`GUIDED COPY
`
`LD
`MRGM
`
`+A0, MFLAGS
`DO, DI, D2
`
`MFLAGS = XX XX XX X6
`
`11 17 «11
`DO = 11
`D1 = 88 88 88 88
`
`CMPM
`
`00, Dt, 02
`
`DO = 89 23 CD 67
`(-)D1 = 89 B9 89 B9
`= 00 89 44 CD)
`MFLAGS = 2? 2? 2? 78
`
`LD
`MRGM
`
`+A0, MFLAGS
`DO, Di, D1
`
`MFLAGS = XX XX XX XC
`
`DO = 89 23 CD 67
`Di = 87 65 43 21
`
`D2: = 11 88 88 11
`
`FIG. 44
`
`Di: = 87 65 CD 67
`
`Lk OF 512 PIXELS
`
`FIG. 45
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 27 of 35
`
`
`5,197,140
`
`
`
`
`
`FIG. 47
`
`
`
`o
`
`oo
`
`of 1
`
`0
`
`
`REMOTE
`
`aeeee,
`
`TRANSMISSION
`
`RECEIVER
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 28 of 35
`
`
`5,197,140
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4903
`
`
`
`4306
`CCD's
`
`
`
`
`AP
`ACQUISITION
`UNIT
`
`ENGINE
`
`IMAGE.
`
`
`
`
`INFORMATION
`
`
`
`
`
`
`
`
`OBJECT OR
`
`DOCUMENT
`
`FOR COPYING
`
`
`
`
`
`
`
`
`
`
`
`
`
`RYa.
`
`
`
`
`
`5001
`
`
`
`5002
`
`
`
`
`
`9007
`
`
`
`
`ACCUMULATED
`
`
`
`
`
`
`
`
`
`CONTROLLED
`
`MECHANISM
`
`5010
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 29 of 35
`
`
`5,197,140
`
`
`
`
`
`9207
`
`
`
`
`
`
`
`
`
`FIG. 52
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 30 of 35
`
`
`5,197,140
`
`
`
`
`
`5424
`
`Z
`Z
`Z
`
`eePoof
`
`|54260 1 5426b|,5436| 5426c
`
`428
`543607
`,5428a
`
`54340( )54320 5434
`m 54505450
`
`
`
`Il ||
`
`|
`
`|
`
`
`
`0
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 31 of 35
`
`5,197,140
`
`
`
`5666
`\
`
`ROW
`COUNTS
`
`5668
`
`FIG. 56
`
`012354
`
`CODDDDCOO-
`
`CODDDODCOON
`
`oorrerrsoon
`
`Ooror-o000+
`
`CO-o-0000
`
`COoroo0d00o00wo
`
`ODoOO9D0D0000m%
`
`DOCDDOCCOCOwo
`
`5670
`
`m-NMOAWNDOMOM
`wweFrran==©
`
`COLUMN
`COUNTS
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`Mar. 23, 1993
`
`
`
`Sheet 32 of 35
`
`
`5,197,140
`
`
`
`5703
`
`
`
`
`5701
`
`5700
`
`
`
`9702
`
`
`
`EXPAND/ALIGN LOGIC
`
`8 x 64 BIT FIFO
`|
`
`
`
`
`
`source9EI
`
`ADDRESS
`
`DESTINATION
`E———4
`
`
`ADDRESS
`GENERATOR
`—
`
`
`
`STATE
`MACHINE
`
`5708
`
`
`
`
`
`
`
`
`
`32-BiTADDRESSBUS
`
`
`
`
`
`
`FIG. 57
`
`
`
`
`
`
`FROM CCD
`
`
`
`
`
`
` ASYNC CLOCK
`
`
`
`PIXEL INPUT
`
`(A/D CONVERTER)
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 33 of 35
`
`
`5,197,140
`
`
`
`5901
`
`
`MIMD.GENERAL_CASE
`
`
`
`
`
`
`FIG, 59
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`(PRIOR ART)
`FIG. 60
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 34 of 35
`
`
`5,197,140
`
`
`
`20
`
`10
`
`MMU
`
`
`
`CT 4 Passe
`
`
`
`3002 ——
`i= ||
`
`
`
`HOT LowPaKo—LHENO
`
`
`
`
`
`
`ot
`pL!__!__|_pinsrroction
`Sees
`
`| | MEMORY
`
`
`
`
`
`DATA PATH TT DATA MEMORY
`Py
`
`3002 RR
`
`
`3100
`V
`1
`|
`
`
`
`i DATA PATH > DATA MEMORY
`—T |
`[
`|
`ry | 4 MEMORY
`
`
`
`
`
`FIG. 671~{dataPatKa===>)DATAWEWORY|103
`| wD ——_——
`
`
`
`10
`20
`|
`
`
`
`/rT Fe
`©|paar
`INSTRUCTION
`
`
`
`
`
`
`PROCESSORSYNCBUS
`
`
`
`3100
`
`
`
`
`
`3100
`
`3100
`
`
`
`|
`
`|
`
`|
`
`|
`
`I
`
`|
`
`to
`
`|
`
`|
`
`MEMO
`
`| | | | | | | ||
`
`| | | | | | | |
`
`
`
`
`
`
`
`a
`cy STRUCTION
`
`
`
`
`
`
`
`
`
`
`PROCESSORSYNCBUS
`
`
`
`
`
`
`FIG. 62
`
`
`
`MEMORY
`
`INSTRUCTION
`MEMORY
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 35 of 35
`
`
`5,197,140
`
`
`
`MIM
`
`
`
`40
` PROCESSOR
`SYNCBUS
`
`
`
`3100
`
`
`
`
`
`101
`
`i
`
`
`
`|
`
`|
`
`|
`
`3100
`
`103
`
`
`
`or | Ll as
`
`
`
`7A
`OFF
`MS
`
`
`
`
`eonmoue keSTN
`
`
`tf
`|
`MEMORY
`
`
`| |
`
`
`SoeatK-40MNO
`
`
`
`
`BScommoumKpPSRTETN
`
`
`
`3100 STS
`boot
`|
`
`
`
`
`
`
`
`
`ool |i tt
`
`
`
`
`a DATA PATH oY DATA MEMORY
`
`DSoman ttf WET
`[STZ_ [11 L_MEMORY
`
`
`
`It
`of
`|
`
`
`
`
`
`
`FIG. 68 OTAPATHKe DATA MEMORY||
`2
`20
`
`
`
`
`
`
`SIMD/MIMD 3002-1 C RecN]
`
`
`
`
`
`
`|
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`OTAMIO]
`i
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`|
`
`
`
`
`
`
`1 ||NSIRUGTON |
`3100 y bot
`
`
`
`
`
`
`
`PR101
`
`| sup
`
`
`
`
`
`30.-—— 4-—--++------ itn)
`AScommour
`P>{_CONTROLLERJ
`
`
`3100 7|| 1 |
`
`a DATA PATH sea DATA MEMORY
`
`
`
`
`1:
`
`
`
`
`mS CONTROLLER KO INSTRUCTION
`Siz) rT TY
`L_MEMORY
`
`
`
`FIG. 64 m ontptKy DATA MEMORY
`
`
`
`
`
`
`
`
`40
`
`
`
`PROCESSORSYNCBUS
`
`103
`
`|
`Low be a
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`1
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`SLICED ADDRESSING MULTI-PROCESSOR AND
`METHOD OF OPERATION
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`TECHNICAL FIELD OF THE INVENTION
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`This invention relates generally to multi-processor
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`systems and moreparticularly to an addressing arrange-
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`ment and method for use in such systems. CROSS REF-
`ERENCE TO RELATED APPLICATIONS
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`All of the following patent applications are cross-
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`referenced to one another, andall have been assigned to
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`Texas Instruments Incorporated. These applications
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`have been concurrently filed and are hereby incorpo-
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`rated in this patent application by reference.
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`U.S. Pat. Application
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`Ser. No.
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`437,591
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`15
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`20
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`25
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`2
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`throughput of the system and negating much of the
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`powerof the multi-processing system.
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`Accordingly, there exists a need in the art for a paral-
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`lel processing system which can store contiguous data
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`in different concurrently accessible address spaces.
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`There also exists a need in the art for such a system
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`where the fact of the actual location is transparent to
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`the user such that the address spaces continue to have
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`consecutive addresses regardless of the physical loca-
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`tion of the corresponding storage locations.
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`One method of solving the huge interconnection
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`problem in complex systems such as the image process-
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`ing system shownin one embodimentofthe inventionis
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`to construct the entire processor as a single device.
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`Conceptually this might appear easy to achieve, but in
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`reality the problems are complicated.
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`First of all, an architecture must be created which
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`allowsfor the efficient movementof information while
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`at the same time conserving precious silicon chip space.
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`Thearchitecture must allow a very high degree offlexi-
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`bility, since once fabricated,it cannot easily be modified
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`for different applications. Also, since the processing
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`capability of the system will be high, there is a need for
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`high band width in the movementofinformation on and
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`off the chip. This is so since the physical number of
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`leads which can attach to any one chipis limited.
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`It is also desirable to design an entire parallel proces-
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`sor system, such as an image processor, on a single
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`silicon chip while maintaining the system flexible
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`enough to satisfy wide ranging and constantly changing
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`operational! criteria.
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`It is further desirable to construct such a single chip
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`parallel processor system where the processor memory
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`interface is easily adaptable to operation in various
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`modes, such as SIMD and MIMD,as well as adaptable
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`to efficient on-off chip data cor munications.
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`SUMMARYOF THE INVENTION
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`These problems have been solved by designing a
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`multi-processing system to handle image processing and
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`graphics in a manner which allows memories to have a
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`block of data spread across several different physical
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`memories while maintaining a continuously addressable
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`space. This is called sliced addressing.
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`Memoryaddressing is typically controlled in blocks
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`where the boundaries between the blocks correspond to
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`a nextdigit in an address. This is implementedby divert-
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`ing the carry path on an adder so that when thebit
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`toggles from one to zero the next adjacent bit in an
`address word is incremented.
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`In sliced addressing, the carry bit is applied to a multi-
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`plexer and is extended to a bit further down the address
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`word. This has the effect of skipping several address
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`locations. If the multiplexer and skip arrangement are
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`established properly, the new skipped address is physi-
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`cal