Trials@uspto.gov
`571-272-7822
`
`Paper 36
`Date: June 7, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG DISPLAY CO., LTD.,
`Petitioner,
`v.
`SOLAS OLED LTD.,
`Patent Owner.
`
`IPR2020-00320
`Patent 7,446,338 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, JESSICA C. KAISER, and JULIA HEANEY,
`Administrative Patent Judges.
`KAISER, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
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`IPR2020-00320
`Patent 7,446,338 B2
`
`INTRODUCTION
`I.
`On December 18, 2019, Samsung Display Co. Ltd. (“Petitioner”)1
`filed a Petition requesting an inter partes review of claims 1–3 and 5–13 of
`U.S. Patent No. 7,446,338 B2, issued on November 4, 2008 (Ex. 1001, “the
`’338 patent”). Paper 1 (“Pet.”). Solas OLED Ltd. (“Patent Owner”) filed a
`Preliminary Response. Paper 6. Taking into account the arguments
`presented in Patent Owner’s Preliminary Response, we determined the
`information presented in the Petition established that there was a reasonable
`likelihood that Petitioner would prevail in challenging at least one of claims
`1–3 and 5–13 of the ’338 patent, and we instituted this inter partes review,
`as to all challenged claims, on June 23, 2020. Paper 9 (“Dec. on Inst.”).
`During the course of the trial, Patent Owner filed a Patent Owner
`Response (Paper 18, “PO Resp.”); Petitioner filed a Reply to the Patent
`Owner Response (Paper 23, “Pet. Reply”); and Patent Owner filed a Sur-
`reply (Paper 25, “PO Sur-reply”). An oral hearing was held on March 25,
`2021, and a transcript of the hearing is included in the record. Paper 35
`(“Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This decision is a Final
`Written Decision under 35 U.S.C. § 318(a) as to the patentability of
`claims 1–3 and 5–13 of the ’338 patent. For the reasons discussed below,
`we hold that Petitioner has demonstrated by a preponderance of the evidence
`that claims 1–3 and 5–13 are unpatentable.
`
`
`1 Apple Inc. filed a petition in IPR2020-01275, and was joined as a
`petitioner in this proceeding. Paper 24. Subsequently, we granted a joint
`motion to terminate Apple Inc. as a petitioner in this proceeding, leaving
`Samsung as the sole remaining petitioner. Paper 31.
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`IPR2020-00320
`Patent 7,446,338 B2
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`II. BACKGROUND
`A. The ’338 Patent (Ex. 1001)
`The ’338 patent describes a display panel comprised of pixels, the
`pixels having a particular arrangement of transistors driving the pixels’ light-
`emitting elements. Ex. 1001, 2:34–41, code (57). Figure 1 of the ’338
`patent is reproduced below.
`
`
`Figure 1 shows four adjacent pixels in display panel 1. Display panel 1 is
`comprised of pixels 3; in particular, the figure shows four adjacent pixels
`arranged in a 2-by-2 configuration, i.e., the pixels are arranged in an array.
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`IPR2020-00320
`Patent 7,446,338 B2
`Id. at 4:53–55, 4:65–66. Each pixel 3 is comprised of red sub-pixel Pr,
`green sub-pixel Pg, and blue sub-pixel Pb. Id. at 4:63–65. Each sub-pixel
`Pr, Pg, Pb is connected to corresponding signal line Yr, Yb, Yg,
`respectively. Id. at 5:12–15. Further, each sub-pixel is connected to select
`interconnection 89, feed interconnection 90, and common interconnection
`91. Id. at 5:23–40; see id. at 6:47–48. Still further, each sub-pixel Pr, Pg,
`Pb have a similar circuit arrangement. Id. at 6:47–48.
`Figure 2 is reproduced below.
`
`
`Figure 2 shows the sub-pixel circuit arrangement, which includes organic
`electroluminescence (EL) element 20, switch transistor 21, holding transistor
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`IPR2020-00320
`Patent 7,446,338 B2
`22, driving transistor 23, and capacitor 24. Id. at 6:48–55. Further, scan line
`Xi is electrically connected to select interconnection 89, switch transistor 21,
`and holding transistor 22; signal line Yj is electrically connected to switch
`transistor 21; and supply line Zi is electrically connected to feed
`interconnection 90 and driving transistor 23. Id. at 6:61–62, 6:65–67, 7:3–6,
`7:11–13, 14:47–50.
`The ’338 patent describes two operating periods for the pixel circuit: a
`“selection period” and a subsequent “light emission period.” Id. at 15:28,
`15:58–61. During the selection period, a “feed driver applies a write feed
`voltage VL to supply a write current to the driving transistors 23 connected
`to” supply line Zi. Id. at 14:46–50; see id. at Fig. 7. The “write current
`(pull-out current) . . . flows from the feed interconnection 90 and supply line
`Zi through the drain-to-source path of the driving transistor 23 and the drain-
`to-source path of the switch transistor 21” and to signal line Yj. Id. at
`15:34–41. Notably, “the switch transistor 21 functions to turn on (selection
`period) and off (light emission period) of the current between the signal line
`Yj and the source 23s of the driving transistor 23.” Id. at 17:26–29. That is,
`switch transistor 21 controls whether the write current flows through driving
`transistor 23, depending on whether the switch transistor is respectively
`turned on or off. See id.; see id. at 15:58–61. In the “subsequent light
`emission period,” switch transistor 21 is “turned off.” Id. at 15:58–61.
`Furthermore, the ’338 patent describes that such pixel circuit
`arrangements for a display are formed “by stacking various kinds of layers
`on [an] insulating substrate.” Id. at 8:21–22. Figure 6, reproduced below, is
`a cross-sectional view of a pixel showing such stacked layers.
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`Patent 7,446,338 B2
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`
`As shown in Figure 6, the aforementioned circuit elements are layered over
`insulating substrate 2 to form the previously described circuit arrangement.
`Id. at 8:18–53. In particular, transistor array substrate 50 includes transistors
`21–23. Id. at 8:25–9:2. Interconnections are then stacked to “project
`upward from the upper surface of the planarization film 33” (id. at 11:39–
`41), i.e., the surface of the transistor array substrate (id. at 10:45–47; see id.
`at 10:49–50). Further, “sub-pixel electrodes 20a are arrayed in a matrix
`on . . . the upper surface of the transistor array substrate 50” (id. at 11:50–
`52) and “organic EL layer 20b of the organic EL element 20,” i.e., a light-
`emitting layer, “is formed on the sub-pixel electrode 20a” (id. at 12:14–16).
`Additionally, “counter electrode 20c functioning as the cathode of the
`organic EL element 20 is formed on the organic EL layers 20b.” Id. at
`13:28–30.
`B. Illustrative claim
`Of the challenged claims, claim 1 is independent and is reproduced
`below.
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`IPR2020-00320
`Patent 7,446,338 B2
`1. A display panel comprising:
`a transistor array substrate which includes a plurality of
`pixels and comprises a plurality of transistors for each pixel, each
`of the transistors including a gate, a gate insulating film, a source,
`and a drain;
`a plurality of interconnections which are formed to project
`from a surface of the transistor array substrate, and which are
`arrayed in parallel to each other;
`a plurality of pixel electrodes for the plurality of pixels,
`respectively, the pixel electrodes being arrayed along the
`interconnections between the interconnections on the surface of
`the transistor array substrate;
`a plurality of light-emitting layers formed on the pixel
`electrodes, respectively; and
`a counter electrode which is stacked on the light-emitting
`layers,
`wherein said plurality of transistors for each pixel include
`a driving transistor, one of the source and the drain of which is
`connected to the pixel electrode, a switch transistor which makes
`a write current flow between the drain and the source of the
`driving transistor, and a holding transistor which holds a voltage
`between the gate and source of the driving transistor in a light
`emission period.
`Ex. 1001, 24:14–38.
`C. Related Proceedings
`Petitioner and Patent Owner identify the following related litigation
`asserting the ’338 patent: Solas OLED Ltd. v. Samsung Display Co., Ltd., et
`al., No. 2:19-cv-00152-JRG (E.D. Tex.);2 Solas OLED Ltd. v. Apple Inc.,
`
`
`2 The parties have informed us that there has been a jury verdict in the
`related Eastern District of Texas proceeding. Ex. 1030, 5:11–6:4, 7:12–17.
`The jury, however, was not presented with any invalidity arguments as to the
`’338 patent during that trial. Id. Thus, we are presented with different
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`Patent 7,446,338 B2
`No. 6:19-cv-00527-ADA (W.D. Tex.); and Solas OLED Ltd. v. Google Inc.,
`No. 6:10-cv-00515-ADA (W.D. Tex.). Pet. 9; Paper 3, 1–2.
`D. References
`Petitioner relies on the following references:
`1.
`“Kobayashi” (US 2002/0158835 A1; published Oct. 31, 2002)
`(Ex. 1003);
`2.
`“Shirasaki” (US 2004/0113873 A1; published June 17, 2004)
`(Ex. 1004); and
`3.
`“Childs” (WO 03/079441 A1; published Sept. 25, 2003) (Ex.
`1005).
`E. Grounds Asserted
`Petitioner asserts that claims 1–3 and 5–13 are unpatentable on the
`following grounds:
`References
`35 U.S.C. §3
`Claims Challenged
`Kobayashi, Shirasaki
`103
`1, 2, 5, 6, 9–11
`Childs, Shirasaki
`103
`1–3, 5–13
`Petitioner also relies on testimony from Adam Fontecchio, Ph.D. (Ex.
`1018). Patent Owner relies on testimony from Richard Flasck (Ex. 2005).
`
`
`
`
`issues to resolve in this Decision than was the jury in the related district
`court proceeding as to the ’338 patent.
`3 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 285–88 (2011), amended 35 U.S.C. § 103, effective March 16,
`2013. Because the application from which the ’338 patent issued was filed
`before this date, the pre-AIA version of § 103 applies.
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`Patent 7,446,338 B2
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`III. ANALYSIS
`
`A. Legal Principles
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art; (3)
`the level of ordinary skill in the art; and (4) when in the record, objective
`evidence of nonobviousness.4 See Graham v. John Deere Co., 383 U.S. 1,
`17–18 (1966). In that regard, an obviousness analysis “need not seek out
`precise teachings directed to the specific subject matter of the challenged
`claim, for a court can take account of the inferences and creative steps that a
`person of ordinary skill in the art would employ.” KSR, 550 U.S. at 418.
`B. Level of Ordinary Skill in the Art
`In the Institution Decision, we adopted Petitioner’s formulation of the
`level of ordinary skill in the art and determined that a person of ordinary
`skill in the art “would have had a relevant technical degree in electrical
`engineering, computer engineering, physics, or the like, and 2–3 years of
`experience in active matrix display design and/or manufacturing.” Dec. on
`Inst. 9 (quoting Pet. 21). In its Patent Owner Response, Patent Owner
`proposes a similar formulation for the level of ordinary skill in the art. See
`PO Resp. 11–12 (citing Ex. 2005 ¶ 29). We maintain our determination
`
`
`4 Neither party presents such evidence in this case.
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`Patent 7,446,338 B2
`from the Institution Decision because that level of skill is consistent with the
`’338 patent and the asserted prior art.
`C. Claim Construction
`In an inter partes review, we construe claim terms according to the
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303, 1312–17 (Fed.
`Cir. 2005) (en banc). 37 C.F.R. § 42.100(b) (2019). Under that standard,
`we construe claims “in accordance with the ordinary and customary meaning
`of such claim as understood by one of ordinary skill in the art and the
`prosecution history pertaining to the patent.” Id. Furthermore, we expressly
`construe the claims only to the extent necessary to resolve the parties’
`dispute. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co. Ltd.,
`868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that
`are in controversy, and only to the extent necessary to resolve the
`controversy.’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999))).
`In our Institution Decision, we discussed the terms “write current” and
`“transistor array substrate” and determined we did not need to explicitly
`construe those or any other claim terms at that stage of the proceeding. Dec.
`on Inst. 10–13. We invited the parties to further address the proper
`constructions of those terms during trial. Id. In its trial briefing, Patent
`Owner addresses claim constructions for the following terms: (1) “transistor
`array substrate”; (2) “project from a surface of the transistor array substrate”;
`(3) “write current”; and (4) “the pixel electrodes being arrayed along the
`interconnections between the interconnections on the surface of the
`transistor array substrate.” PO Resp. 12–13. Regarding these terms, Patent
`Owner relies upon the constructions provided in the Claim Construction
`Memorandum and Order (Ex. 1020) issued in a related district court case
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`Patent 7,446,338 B2
`involving these parties and the ’338 patent.5 Id. (citing Ex. 1020, 8, 18); see
`Ex. 1020, 8–23. In its Reply, Petitioner addresses constructions for the same
`terms. Pet. Reply 1–4. For purposes of this decision, we determine we need
`only address the construction of the following claim terms: (1) “project
`from a surface of the transistor array substrate,” and (2) “the pixel electrodes
`being arrayed along the interconnections between the interconnections on
`the surface of the transistor array substrate.” See Nidec, 868 F.3d at 1017.
`1. “project from a surface of the transistor array substrate”
`In the related district court proceeding, the district court construed
`“project from a surface of the transistor array substrate” to mean “extend
`beyond an outer surface of the transistor array substrate.” Ex. 1020, 15–18.6
`We have considered the district court’s claim construction order (37 C.F.R.
`§ 42.100(b)), as well as the parties’ arguments, and as discussed in detail
`below, we adopt the district court’s construction of this term as consistent
`with the ordinary and customary meaning as understood by one of ordinary
`skill in the art. After considering the parties’ arguments in this proceeding,
`we are not persuaded to adopt any additional refinements to the district
`court’s construction.
`Petitioner initially proposed that the term “a plurality of
`interconnections which are formed to project from a surface of the transistor
`array substrate” “should be interpreted to encompass a plurality of
`interconnections which are formed to extend above the upper surface of the
`
`
`5 Solas OLED Ltd. v. Samsung Display Co., Ltd. et al., No. 2:19-cv-00152-
`JRG (E.D. Tex.).
`6 At the district court, the dispute as to this term focused on whether the
`interconnections must extend beyond an outer surface of the transistor array
`substrate. Ex. 1020, 15–18; PO Sur-reply 7–8.
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`topmost layer of the transistor array substrate.” Pet. 23–24 (citing Ex. 1018
`¶ 84). Petitioner contends that the disclosure of “the ’338 patent defines the
`‘surface of the transistor array substrate’ as the upper surface of the topmost
`layer of the transistor array substrate, on which pixel electrodes are formed.”
`Id. at 23 (citing Ex. 1001, 10:48–51, 11:50–52; Ex. 1018 ¶ 83). Petitioner
`next addresses “project from” a surface by citing to the embodiment
`depicted in Figure 6 of the ’338 patent and contends that each of the “select
`interconnection 89, feed interconnection 90, and common interconnection 91
`. . . are formed . . . to project [with] respect to the surface of the transistor
`array substrate 50.” Id. at 23–24 (quoting Ex. 1001, 12:62–67) (citing Ex.
`1001, 10:54–58, 11:36–41, Fig. 6; Ex. 1018 ¶¶ 83–84).
`Patent Owner states that it has applied the district court’s
`constructions in its Patent Owner Response. PO Resp. 12. In responding to
`Petitioner’s unpatentability challenges, however, Patent Owner seeks to
`further limit the district court’s construction of “project from a surface of the
`transistor array substrate.” See id. at 27, 29–30; PO Sur-reply 3–5.
`Specifically, Patent Owner argues that this limitation need not be construed
`to encompass common interconnection 91 in Figure 6 of the ’338 patent
`“[b]ecause the claims at issue use the ‘comprising’ transition.” PO Resp. 28.
`Relying on the declaration from Mr. Flasck, Patent Owner contends that the
`district court’s “construction . . . requires that there be some connection or
`relationship between the thing ‘projecting’ and the surface it is projecting
`from.” Id. at 27 (citing Ex. 2005 ¶ 95; Ex. 1020, 17; Ex. 2008, 3 (dictionary
`definition of “projecting”)). Patent Owner further argues that this limitation
`encompasses structures that “begin near [the transistor array substrate]
`surface and extend a significant distance away from the surface, both
`relative to their distance from the surface and relative to their overall
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`IPR2020-00320
`Patent 7,446,338 B2
`dimensions,” but excludes structures that “are far above the surface, relative
`to their own dimensions, and their extent in the vertical direction (the
`direction they would need to be ‘projecting’ or ‘protruding’[)] is small
`relative to the other relevant dimensions.” Id. at 29–30 (citing Ex. 2005
`¶ 99).
`
`Petitioner replies that the construction proposed in its Petition (Pet.
`23–24) “is fully consistent with the district court’s construction.” Pet. Reply
`2–3 (citing Ex. 1020, 18). Petitioner contends that the district court
`construction of “extend beyond an outer surface of the transistor array
`substrate” is broader than, but consistent with, Petitioner’s proposed
`construction of “encompass[ing] interconnections which are formed to
`extend above the upper surface of the topmost layer of the transistor array
`substrate.” Id. (citing Pet. 23–24).7 Petitioner also contends that Patent
`Owner’s attempt to further limit this term is inconsistent with the ’338
`patent’s preferred embodiment describing and depicting common
`interconnection 91 on top of insulating line 61, which sits on top of the
`transistor array substrate. Id. at 3–4 (citing Ex. 1001, 10:54–58, Fig. 6).
`Specifically, Petitioner notes that the ’338 patent describes common
`interconnection 91 as “project[ing] upward from the surface of planarization
`
`
`7 Petitioner also notes that the district court struck testimony from Patent
`Owner’s district court expert Mr. Credelle that the plain meaning of “project
`from a surface” and the district court’s construction requires “that there be
`some connection or relationship between the thin[g] ‘projecting’ and the
`surface it is projecting from.” See Pet. Reply 3 (citing PO Resp. 29; Ex.
`1026, 88:8–17 (pretrial hearing transcript)); see also id. at 15–16 (citing Ex.
`1024 ¶ 221; Ex. 1027, 9, 12 (claim construction order)). Patent Owner
`contends the dispute before the district court was different and thus this
`argument is a “red herring.” PO Sur-reply 7–10.
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`film 33” (i.e., the transistor array substrate). See id. (quoting Ex. 1001,
`10:54–58).
`In its Sur-reply, Patent Owner emphasizes the importance of “formed
`to project from” and contends “the claim term ‘from’ introduces an obvious
`additional spatial requirement beyond just being located above a surface.”
`PO Sur-reply 5. In particular, Patent Owner contends “the [transistor array
`substrate] surface must [] be a ‘starting point’ from which the
`interconnection projects.” Id. (citing to dictionary definitions of “from”).
`Patent Owner cites to the deposition of Petitioner’s expert, Dr. Fontecchio,
`and asserts that Dr. Fontecchio and Petitioner misinterpret “project from a
`surface” as “formed anywhere above a surface.” Id. at 4 (citing Ex. 2007,
`121:9–11) (emphasis omitted).
`
`After having reviewed the claim language, the arguments, and the
`evidence, we determine that the district court’s construction of “project from
`a surface of the transistor array substrate” is consistent with the ordinary and
`customary meaning of the phrase in light of the Specification, and we adopt
`that construction for purposes of this Decision. We have considered the
`additional requirements as asserted by Patent Owner, but do not find them
`supported by the evidence as discussed below.
`
`Turning first to the claim language, we agree with Patent Owner that
`the plain meaning of the term, and the district court’s construction, requires
`“some connection or relationship between the thing ‘projecting’ and the
`surface it is projecting from.” PO Resp. 27 (citing Ex. 1020, 17; Ex. 2005
`¶ 95; Ex. 2008, 3). The district court relied on a dictionary definition of
`“project” to inform that relationship as “extend[ing] outward beyond
`something else,” i.e., extending outward beyond the transistor array
`substrate. Ex. 1020, 17–18. Here, Patent Owner goes further and relies
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`upon dictionary definitions8 of “from” to further limit the surface of the
`transistor array substrate as the “starting point” from which the
`interconnection projects. PO Sur-reply 5. We do not interpret these
`definitions to narrowly limit “from” in the way Patent Owner argues. In the
`disputed limitation, the surface of the transistor array substrate is a point of
`reference and the interconnection extends in a direction away from the
`surface; thus there is a relationship between the thing projecting (i.e., the
`interconnection) and the surface it is projecting from (that of the transistor
`array substrate). While we agree with Patent Owner that “[e]ach element
`contained in a patent claim is deemed material to defining the scope of the
`patent invention” (id. (citing Warner-Jenkinson Co. v. Hilton Davis Chem.
`Co., 520 U.S. 17 (1997)), the district court’s construction as “extend
`beyond” does not read any sort of positional or spatial requirements out of
`the claim limitation.
`Turning to the Specification, the ’338 patent discloses that “[t]he
`common interconnection 91 is formed by electroplating and is therefore
`formed to . . . project upward from the surface of the planarization film 33”
`(i.e., “the upper surface of the transistor array substrate 50”). Ex. 1001,
`10:52–58, 11:50–52. In addition, the ’338 patent also describes “select
`interconnection 89, feed interconnection 90, and common interconnection 91
`. . . are formed between the sub-pixel electrodes 20a adjacent in the vertical
`direction to project [with] respect to the surface of the transistor array
`
`8 Because a sur-reply may not be accompanied by new evidence (37 C.F.R.
`§ 42.23(b)), Patent Owner provides only websites for these definitions.
`Although it is generally improper to introduce evidence in this way in a sur-
`reply, we have considered these definitions in this instance because they
`inform our understanding of Patent Owner’s claim construction arguments,
`which we find unpersuasive for the reasons explained below.
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`substrate 50.” Id. at 12:62–67. Although Patent Owner is correct that the
`transitional phrase “comprising” in claim 1 is non-limiting (PO Resp. 28),
`the written description of the ’338 patent describes common interconnection
`91 as being formed to project from the surface of the transistor array
`substrate. In other words, even though common interconnection 91 does not
`have planarization film 33 as its starting point (see Ex. 1001, Fig. 6
`(depicting insulating line 61 between common interconnection 91 and
`planarization film 33)), the written description describes common
`interconnection 91 as projecting upward from the surface of planarization
`film 33 (id. at 10:54–58). Thus, the written description makes clear that
`“project from” does not exclude such intermediate structures.
`We are also not persuaded that the ’338 patent Specification requires
`any specific relative dimensions for the interconnection to “project from” the
`surface of the transistor array substrate. The ’338 patent discloses “[t]he
`common interconnection 91 is formed by electroplating and is therefore
`formed to be much thicker than the signal line Y, scan line X, and supply
`line Z and project upward from the surface of the planarization film 33 [i.e.,
`the surface of the transistor array substrate].” Id. at 10:54–58. The ’338
`patent also discloses “[t]he thick select interconnection 89, feed
`interconnection 90, and common interconnection 91 whose tops are much
`higher than that of the insulating line 61 are formed between the sub-pixel
`electrodes 20a adjacent in the vertical direction to project [with] respect to
`the surface of the transistor array substrate 50.” Id. at 12:62–67. Regarding
`interconnections 89 and 90, the ’338 patent discloses:
`The select interconnections 89 and feed interconnections 90 are
`formed by electroplating and are therefore much thicker than the
`signal lines Y, scan lines X, and supply lines Z. The thickness
`of the select interconnection 89 and feed interconnection 90 is
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`larger than the total thickness of the protective insulating film 32
`and planarization film 33 so that the select interconnection 89
`and feed interconnection 90 project upward from the upper
`surface of the planarization film 33 [i.e., surface of the transistor
`array substrate].
`Id. at 11:33–41.
`We view these disclosures as non-limiting descriptions of a preferred
`embodiment of the ’338 patent. See id. at 4:46–48 (“[T]he spirit and scope
`of the present invention are not limited to the following embodiments and
`illustrated examples.”). We observe that in the Figure 6 embodiment, select
`interconnection 89 and feed interconnection 90 begin below planarization
`film 33 within protective film 32, and thus the Specification describes those
`interconnections as being larger than the total thickness of both films so that
`those interconnections project from (i.e., “extend beyond”) the outer surface
`of the transistor array substrate. In contrast, the Specification states that
`“common interconnection 91 is formed by electroplating and is therefore
`formed to be much thicker than the signal line Y, scan line X, and supply
`line Z and project upward from the surface of the planarization film 33.”
`Ex. 1001, 10:54–58. In other words, the Specification identifies a relative
`thickness for the common interconnection in the Figure 6 embodiment as
`compared to the signal line Y, scan line X, and supply line Z, but does not
`indicate that that relative thickness is required for common interconnection
`91 to project from the surface of planarization film 33. We also agree with
`Petitioner that “[n]othing in the ’338 patent’s claims or specification
`indicates the term ‘project from’ has any relationship to the thickness of the
`insulating layer between an interconnection and the transistor array
`substrate.” Pet. Reply 18–19 (citing PO Resp. 29–30). Thus, we find that
`the Specification of the ’338 patent does not require the further limitations
`
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`IPR2020-00320
`Patent 7,446,338 B2
`that Patent Owner argues we should adopt in the construction of “project
`from a surface of the transistor array substrate.”9
`For the foregoing reasons, we agree with the district court’s
`construction of “project from a surface of the transistor array substrate” as
`“extend beyond an outer surface of the transistor array substrate” (Ex. 1020,
`15–18), and we do not adopt Patent Owner’s proposed further limitations to
`this construction.
`2. “the pixel electrodes being arrayed along the interconnections
`between the interconnections on the surface of the transistor
`array substrate”
`The district court construed “the pixel electrodes being arrayed along
`the interconnections between the interconnections on the surface of the
`transistor array substrate” to mean “the pixel electrodes are arrayed along the
`interconnections and located between the interconnections, and the pixel
`electrodes are on the surface of the transistor array substrate.” Ex. 1020, 8 &
`n.2. As Petitioner indicates, “[t]he district court adopted this as an agreed
`construction.” Pet. Reply 2 (citing Ex. 1020, 8); see also Ex. 1020, 8 n.2
`(“[T]he Court finds that the parties’ agreed construction of this term
`comports with [the] Court’s view.”). We have considered the district court’s
`claim construction order (37 C.F.R. § 42.100(b)), as well as the parties’
`arguments, and as discussed in detail below, we adopt the district court’s
`claim construction of this term as consistent with the ordinary and customary
`meaning as understood by one of ordinary skill in the art. After considering
`
`
`9 Although the prosecution history of the ’338 patent is in the record (Ex.
`1002) and discussed as background in the Petition (Pet. 19–21) and Patent
`Owner Response (PO Resp. 9–11), we note that neither Petitioner nor Patent
`Owner specifically argues that the prosecution history affects the proper
`construction of this claim term.
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`IPR2020-00320
`Patent 7,446,338 B2
`the parties’ arguments in this proceeding, we are not persuaded to adopt any
`additional refinements to the district court’s construction.
`Petitioner initially proposed that “the pixel electrodes being arrayed
`along the interconnections between the interconnections on the surface of
`the transistor array substrate” means “that the pixel electrodes: (1) are
`arrayed along the interconnections between the interconnections; and (2) are
`arrayed on the surface of the transistor array substrate.” Pet. 25 (citing Ex.
`1018 ¶ 85). Petitioner supports this construction by citing to the disclosure
`of the ’338 patent that states “[t]he plurality of sub-pixel electrodes 20a are
`arrayed in a matrix on the upper surface of the planarization film 33, i.e., the
`upper surface of the transistor array substrate,” and “these sub-pixel
`electrodes are arrayed between the interconnections 89, 90, and 91 . . . as
`depicted in [] Figure 6.” Id. (citing Ex. 1001, 11:50–52, 12:30–54, Fig. 6;
`Ex. 1018 ¶ 86).
`Patent Owner states that it has applied the district court’s
`constructions in its Patent Owner Response. PO Resp. 12. In responding to
`Petitioner’s unpatentability challenges, however, Patent Owner seeks to
`further limit the district court’s construction of “the pixel electrodes being
`arrayed along the interconnections between the interconnections on the
`surface of the transistor array substrate.” See id. at 32, 44–45; PO Sur-reply
`13–19, 22–23, 25–26. Relying on the declaration from Mr. Flasck, Patent
`Owner contends that if “[parts] or portions of the pixel electrodes are almost
`directly below [or beneath] the interconnections,” then those pixel electrodes
`“are not ‘arrayed along’ or ‘located between’ the interconnections, as those
`terms would be understood by” a person of ordinary skill in the art. PO
`Resp. 32, 45 (citing Ex. 2005 ¶¶ 104, 133) (emphasis added). Patent Owner
`further contends that if “large portions of the pixel electrodes are buried
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`IPR2020-00320
`Patent 7,446,338 B2
`within and under the transistor array substrate,” then those electrodes are not
`“on the surface” of the transistor. Id. at 44 (citing Ex. 2005 ¶ 133).
`Petitioner replies that the construction proposed in its Petition is
`consistent with the agreed upon construction of “the pixel electrodes are
`arrayed along the interconnections and located between the interconnections,
`and the pixel electrodes are on the surface of the transistor array substrate.”
`Pet. Reply 2 (citing Ex. 2004, 1; Ex. 1020, 8). Petitioner argues that being
`“arrayed along and between” does not require the electrode