IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`SAMSUNG DISPLAY CO., LTD., SAMSUNG
`ELECTRONICS CO., LTD., AND SAMSUNG
`ELECTRONICS AMERICA, INC.,
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`Civil Action No. 2:19-cv-00152-JRG
`
`FILED UNDER SEAL
`
`Defendants.
`
`DEFENDANTS SAMSUNG DISPLAY CO., LTD., SAMSUNG
`ELECTRONICS CO., LTD., AND SAMSUNG ELECTRONICS AMERICA, INC.’S
`RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`

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`TABLE OF CONTENTS
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`INTRODUCTION ................................................................................................................... 1
`I.
`II. LEGAL STANDARD ............................................................................................................. 1
`III.
`ARGUMENT ....................................................................................................................... 2
`A.
`Background of the ’338 Patent ......................................................................................... 2
`B.
`Disputed Terms of the ’338 Patent ................................................................................... 3
`“transistor array substrate” (claim 1) ............................................................................... 3
`1.
`“project from a surface of the transistor array substrate” (claim 1) ............................... 12
`2.
`“the pixel electrodes being arrayed along the interconnections between the
`3.
`interconnections on the surface of the transistor array substrate” (claim 1) ......................... 17
`4.
`“write current” (claim 1) ................................................................................................ 21
`Background of the ’311 Patent ....................................................................................... 27
`Disputed Term of the ’311 Patent .................................................................................. 27
`“configured to wrap around one or more edges of a display” (claims 1 and 7) ............. 27
`CONCLUSION .................................................................................................................. 30
`
`C.
`D.
`1.
`
`IV.
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`I.
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`INTRODUCTION
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`The constructions proposed by Defendants Samsung Display Co., Ltd., Samsung
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`Electronics Co., Ltd., and Samsung Electronics America, Inc. reflect the meaning of the technical
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`terms at issue to a person of ordinary skill in the art at the time of the invention based on the
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`intrinsic evidence and, where applicable, extrinsic evidence showing a customary meaning. The
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`parties have not disputed any term of U.S. Patent No. 6,072,450. As to U.S. Patent No. 7,446,338
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`(“the ’338 patent”), Defendants’ proposals represent the meaning of the terms in the context of the
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`patent. Not only are Plaintiff Solas’s constructions inconsistent with the intrinsic record, they
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`contradict interpretations Solas itself advanced in its licensing efforts—a fact Solas neglects to
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`mention. The intrinsic evidence has not changed, and Solas’s unexplained about-face belies many
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`of its criticisms. Finally, as to U.S. Patent No. 9,256,311 (“the ’311 patent”), the parties dispute a
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`single term, with their dispute centering on the meaning of “edge.” Defendants’ proposal for this
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`term represents the standard technical meaning of that term, as reflected in dictionaries.
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`II.
`
`LEGAL STANDARD
`
`“It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the invention to
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`which the patentee is entitled the right to exclude.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312
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`(Fed. Cir. 2005) (en banc) (citation omitted). A person of ordinary skill “is deemed to read the
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`claim term not only in the context of the particular claim . . ., but in the context of the entire patent,
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`including the specification.” Id. at 1313.
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`“The words of a claim are generally given their ordinary and customary meaning as
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`understood by a person of ordinary skill in the art when read in the context of the specification and
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`prosecution history.” Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir.
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`2012) (citing Phillips, 415 F.3d at 1313). A “term’s ordinary meaning must be considered in the
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`context of all the intrinsic evidence, including the claims, specification, and prosecution history.”
`1
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`Biogen Idec, Inc. v. GlaxoSmithKline LLC, 713 F.3d 1090, 1094 (Fed. Cir. 2013). When a patentee
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`acts as his own lexicographer, or when a patentee disavows the full scope of a claim term in the
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`specification or during prosecution, then the customary meaning does not apply. See Trustees of
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`Columbia v. Symantec Corp., 811 F.3d 1359, 1363-64 (Fed. Cir. 2016).
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`“[T]he specification ‘is always highly relevant to the claim construction analysis. Usually,
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`it is dispositive; it is the single best guide to the meaning of a disputed term.’” Phillips, 415 F.3d
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`at 1315 (internal quotation marks omitted). Although extrinsic evidence can also be useful, it is
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`“less significant than the intrinsic record.” Id. at 1317 (internal quotation marks omitted). Courts
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`have “especially noted the help that technical dictionaries may provide . . . to better understand the
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`underlying technology and the way in which one of skill in the art might use the claim terms.” Id.
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`at 1318 (internal quotation marks omitted). Expert testimony may aid a court in understanding the
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`underlying technology, but an expert’s unsupported assertions as to a term’s definition are not
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`helpful to a court. See id.
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`III.
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`ARGUMENT
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`A.
`
`Background of the ’338 Patent
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`The ’338 patent is directed to active-matrix organic electroluminescent (AMOLED)
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`display panels. See, e.g., Ex. 1 (’338 patent) at 1:17-21, 8:18-23. These are many-layered devices
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`that consist of organic electroluminescent pixels and circuitry that drives the pixels to produce
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`particular colors and brightness. Figure 6 is a cross-section illustrating the layered structure of an
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`exemplary display panel of the ’338 patent, consisting of these two main structures: (1) the red,
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`green, and blue OLED pixels (Pr, Pg, and Pb), each made up of a pixel electrode 20a, an
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`electroluminescent layer 20b, and a counter electrode 20c; and (2) the layers making up the
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`“transistor array substrate” 50, id. at 10:42-47, which includes the transistors 21 and 23 that make
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`up the active-matrix circuit for each pixel:
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`2
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`In the original patent application, original claim 1 was directed to the arrangement of
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`elements in the layered structure, as exemplified by Figure 6. That claim, however, was rejected
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`as anticipated by prior art. To overcome the rejection, the applicants amended claim 1, limiting it
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`to a display having the particular three-transistor pixel circuit structure that had been recited in a
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`dependent claim (original claim 2), illustrated in Figure 2 of the ’338 patent. Ex. 2 at 2-3, 12. This
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`circuit uses a current, called a write current, to set the brightness of each individual pixel. This
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`current-controlled structure differed from circuits that used particular voltage signal levels applied
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`to the gate of the driving transistor, rather than current, to control pixel brightness. See Ex. 1 (’338
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`patent) at 1:21-41 (describing that in a prior art reference, “a voltage of level representing the
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`luminance is applied to the gate of the driving transistor through a signal line.”). After the addition
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`of this three-transistor circuit structure limitation, the claims of the ’338 patent were allowed.
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`B.
`
`Disputed Terms of the ’338 Patent1
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`1. “transistor array substrate” (claim 1)
`
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`1 A person of ordinary skill in the art of the ’338 patent would have had a relevant technical
`degree in electrical engineering, computer engineering, physics, or the like, and 2–3 years of
`experience in active matrix display design and/or manufacturing.
`3
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`Defendants’ Proposal
`“a layered structure composed of a bottom
`insulating layer through a topmost layer on
`whose upper surface [pixel] electrodes are
`formed, which contains an array of transistors”
`
`Plaintiff’s Proposal
`“layered structure upon which or within which
`a transistor array is fabricated”
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`The term “transistor array substrate” does not have a customary meaning in the art. It is a
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`term specific to the ’338 patent, and one which, as discussed below, the ’338 patent defines as a
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`layered structure composed of a bottom insulating layer through a topmost layer on whose upper
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`surface electrodes are formed, which contains an array of transistors. Both the language of claim
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`1 and the specification support Defendants’ proposal. Solas, in contrast, proposes a construction
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`inconsistent with the claim language and the specification—and inconsistent with Solas’s own
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`prior position on the term. Solas’s vague proposal would also take a term clearly described in the
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`claims and specification and render it indefinite.
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`The parties have two main disputes concerning this term: (1) whether the transistors are
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`within the transistor array substrate; and (2) which of the many layers of a display panel constitute
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`the transistor array substrate.
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`a. The transistors are contained in the transistor array substrate
`Defendants’ construction states that the transistor array substrate contains an array of
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`transistors. In contrast, Solas proposes that the “transistor array substrate” need not contain an
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`array of transistors. Solas’s construction is contrary to the claim language and the specification.
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`The claim language recites “a transistor array substrate which includes a plurality of
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`pixels and comprises a plurality of transistors for each pixel, each of the transistors including a
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`gate, a gate insulating film, a source, and a drain.” Ex. 1 (’338 patent) at 24:15-18 (emphasis
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`added). The term “comprises” means “including but not limited to.” See, e.g., Genentech, Inc. v.
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`Chiron Corp., 112 F.3d 495, 501 (Fed. Cir. 1997). Thus, by the plain terms of the claim, the
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`transistor array substrate must contain a plurality of transistors for each pixel (i.e., an array of
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`transistors). Moreover, the specification explains that the transistors are contained within the
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`transistor array substrate. See, e.g., Ex. 1 (’338 patent) at 10:45-47. Indeed, Solas’s expert admits
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`in his declaration that “[t]he transistor array substrate is a structure containing a transistor array.”
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`Dkt. 74-2 (Flasck Decl.) at ¶ 30.
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`Despite the clear requirement of the claim language, Solas’s proposal (“layered structure
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`upon which or within which a transistor array is fabricated”) would permit the transistor array
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`substrate to contain no transistors. Solas’s expert admitted this in deposition:
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`Q: . . . For the construction that you have offered for “transistor array substrate,”
`which in paragraph 27 says, “layered structure upon which or within which a
`transistor array is fabricated,” does that encompass . . . a layered structure in which
`none of the transistors are located within the transistor array?
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`A: If there is a structure, a layered structure, and upon that layered structure there
`is a transistor array, then it would fall under this construction.
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`Q: Even though none of the transistors were within the layered structure that [] is
`called the “transistor array substrate”?
`
`A: That’s correct. . . .
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`Ex. 3 (Flasck Depo.) at 64:17-65:14 (objection omitted). This is contrary to the intrinsic evidence.
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`As stated in Defendants’ proposal, the transistor array substrate is a “layered structure
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`composed of a bottom insulating layer through a topmost layer on whose upper surface [pixel]
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`electrodes are formed, which contains an array of transistors.” Solas’s contrary proposal is plainly
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`inconsistent with the claim language and specification, and cannot be correct.
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`b. Solas’s expert concedes that “transistor array substrate” does
`not have a customary meaning outside the ’338 patent.
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`Having advanced a construction inconsistent with the clear intrinsic evidence, Solas
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`attempts to support its proposal by claiming it represents an “ordinary and customary meaning” of
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`“transistor array substrate,” and arguing that departure from that purported plain meaning requires
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`clear and unmistakable evidence. Dkt. 74 at 7-9. Solas’s argument is meritless. First, although
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`Solas’s brief attempts to portray its proposal as the plain and ordinary meaning of “transistor array
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`substrate,” Solas’s expert conceded in deposition that the term does not have a customary meaning
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`in the art. On the contrary, he testified that “transistor array substrate” may mean different things
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`in different usages. Ex. 3 (Flasck Depo.) at 104:4-105:3 (“In one context this whole thing would
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`be a transistor array substrate . . . in some contexts people would refer to a transistor array substrate
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`as something less than this and generally would not include the electro-optical element. In this
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`case it would not include the EL film . . . so I’ve seen it used both ways”), 57:5-7, 69:3-11.
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`Second, Solas does not cite any definition of the term “transistor array substrate.” This
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`belies its assertion that the term has an ordinary and customary meaning. Solas relies on an IEEE
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`dictionary definition of a different term, “substrate.” Ex. 3 (Flasck Depo.) at 69:17-19 (“Q. There
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`is no IEEE definition for ‘transistor array substrate,” is there? A. I believe that is correct.”).
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`Solas’s reliance on definitions of “substrate” is particularly inapt because the ’338 patent
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`distinguishes a “substrate” from “a transistor array substrate.” See, e.g., Ex. 1 (’338 patent) at
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`10:42-47 (“[T]he layered structure from the insulating substrate 2 to the planarization film 33 is
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`called a transistor array substrate 50”) (emphases added). The patent teaches that an insulating
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`substrate is just one portion of a transistor array substrate, which includes numerous other layers
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`as well. See id.
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`Third, Solas’s construction does not even match its dictionary definition, which says
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`nothing of a structure being “layered.” Ex. 3 (Flasck Depo.) at 73:11-74:10.
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`Thus, Solas cannot claim that its proposal represents the plain and ordinary meaning of
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`“transistor array substrate.” Rather, the language of the claims and the disclosures of the
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`specification demonstrate that the meaning of that term is as Defendants propose—a proposal that
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`matches Solas’s own prior interpretation of that term (as discussed below).
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`6
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
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`c. The ’338 patent defines which layers of an OLED display panel
`constitute the “transistor array substrate”
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`The claim language and the specification make clear that the “transistor array substrate” is
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`a layered structure composed of a bottom insulating layer through a topmost layer on whose upper
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`surface [pixel] electrodes are formed, as Defendants propose.2
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`First, the claim language supports Defendants’ proposal. After reciting “a transistor array
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`substrate,” claim 1 proceeds to recite (1) that the interconnections “project from a surface of the
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`transistor array substrate” and (2) “the pixel electrodes being arrayed along the interconnections
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`between the interconnections on the surface of the transistor array substrate.” Thus, according to
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`the claim language, the pixel electrodes are “on the surface of the transistor array substrate,”
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`meaning that the “transistor array substrate” constitutes the layers up to but not including the pixel
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`electrodes, as Defendants propose.
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`Second, consistent with the claim language, the specification discloses that the transistor
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`array substrate constitutes the layers up to (but not including) the pixel electrode. The specification
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`expressly states that “[t]he layered structure from the insulating substrate 2 to the planarization
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`film 33 is called a transistor array substrate 50.” Ex. 1 (’338 patent) at 10:45-47 (emphasis added).
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`See, e.g., Sinorgchem Co., Shandong v. Int'l Trade Comm’n, 511 F.3d 1132, 1136 (Fed. Cir. 2007)
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`(“[T]he word ‘is’ ... may signify that a patentee is serving as its own lexicographer.”) (citation and
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`internal quotation marks omitted); Medimmune, LLC v. PDL Biopharma, Inc., No. C 08–05590,
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`2010 WL 653546, at *6 (N.D. Cal. Feb. 22, 2010) (“It is undisputed that the specification expressly
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`defines acceptor: ‘the human immunoglobulin providing the framework is called the ‘acceptor.’”);
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`2 Defendants believed that their construction was clear that the “electrodes” referred to in it are the
`pixel electrodes, as illustrated by element 20a in Fig. 6 of the ’338 patent. Because Solas professes
`confusion in its brief, Dkt. 74 at 11-2, Defendants clarify that the topmost layer of the transistor
`array substrate is the layer on which the pixel electrodes are formed.
`7
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`TriStrata, Inc. v. Microsoft Corp., 594 Fed. App’x 653 (Fed. Cir. Dec. 4, 2014) (unpublished);
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`Alacritech, Inc. v. Century Link Comm’ns LLC, 271 F. Supp. 3d 850, 868 (E.D. Tex. 2017).
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`Next, the specification explains that “[t]he plurality of sub-pixel electrodes 20a are arrayed
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`in a matrix on the upper surface of the planarization film 33, i.e., the upper surface of the
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`transistor array substrate 50.” Ex. 1 (’338 patent) at 11:50-53 (emphasis added). See Edwards
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`Lifesciences LLC v. Cook Inc., 582 F.3d 1322, 1334 (Fed. Cir. 2009) (“the specification’s use of
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`‘i.e.’ signals an intent to define the word to which it refers”). This passage again conveys that the
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`surface on which the pixel electrodes are formed consitutes the upper surface of the transistor array
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`substrate. Indeed, the phrasing of this passage parallels the claim language stating that the pixel
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`electrodes are arrayed on the surface of the transistor array substrate, reinforcing that this passage
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`is describing the claimed invention.
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`Thus, the claim language and specification both define the top layer of the transistor array
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`substrate as the layer on whose upper surface the pixel electrodes are formed. The specification is
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`clear that all of the layers beneath that layer are also part of the transistor array substrate, as
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`illustrated in annotated Figure 6 of the patent below. See, e.g., Ex. 1 (’338 patent) at 10:45-47
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`(“The layered structure from the insulating substrate 2 to the planarization film 33 is called a
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`transistor array substrate 50.”) (emphasis added).
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`8
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`Defendants’ proposal clarifies that the bottom-most layer is the insulating substrate,
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`consistent with the disclosures of the ’338 patent. E.g., id. at 8:21-23 (“The display panel 1 is
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`formed by stacking various kinds of layers on the insulating substrate 2 which is optically
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`transparent.”). Solas’s contention that the bottom layer need not be insulating, Dkt. 74 at 11, is
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`unsupported (including by its own expert) and at odds with the specification. In any event, the key
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`point is that the “transistor array substrate” constitutes the bottom-most layer of the display panel
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`through the layer on the surface of which pixel electrodes are formed; while that bottom-most layer
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`will be an insulating layer, identifying it as such is not central to the claim construction dispute.
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`Solas also neglects to mention in its brief that, just one year ago, when explaining the claims
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`to third parties, Solas interpreted “transistor array substrate” consistent with Defendants’ proposal,
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`and relied on the same passage—column 10, lines 45-47 of the ’338 patent—to define it:
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`Ex. 4 at 94 (SOLAS_SAMSUNG_0003936). The intrinsic evidence has not changed, only Solas’s
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`position has. Solas’s new position is inconsistent with both the language of claim 1 and the
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`specification. The transistor array substrate includes all layers beneath the pixel electrodes.
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`9
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`Solas attempts to argue that Defendants’ construction would exclude a disclosed
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`embodiment, but that is incorrect. Dkt. 74 at 11. Solas refers to an alternative embodiment having
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`a “reflecting film” between the pixel electrode and planarization film. Id. (citing Ex. 1 at 11:66-
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`12:5). Solas disregards, however, that the reflecting film would constitute a portion of the
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`transistor array substrate, as it is the layer on which pixel electrodes are formed in that design.
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`Thus, Defendants’ construction encompasses this alternative, illustrating that it comports with all
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`embodiments and disclosures of the specification, and does not exclude any disclosed
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`embodiments. In contrast, under Solas’s proposal there would be no way to determine whether
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`such a reflecting film is part of the transistor array substrate or not.
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`Solas also asserts that the boundary of the “transistor array substrate” cannot be defined by
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`the pixel electrodes because the specification also describes an insulating line 61 as being formed
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`on the suface of the planarization film 33 (in a region where the pixel electrodes are not present).
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`Dkt. 74 at 10. This is a non-sequitur. The fact that an optional insulating line 61 may also be on
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`another portion of the surface of the transistor array substrate does not take away from the fact that
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`the specification defines the upper surface of the transistor array substrate as the layer on which
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`the pixel electrodes are formed. The claim language itself identifies the pixel electrodes as being
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`formed on the surface of the transistor array substrate, while not mentioning an insulating line.
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`Indeed, the pixel electrodes—unlike insulating line 61—are essential to the display’s operation.
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`In contrast to the clarity provided by Defendants’ construction, Solas’s construction—
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`“layered structure upon which or within which a transistor array is fabricated”—fails to indicate
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`which layers are part of that structure and which are not, and would render the claims indefinite.
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`Indeed, Solas’s expert acknowledged in deposition that, under Solas’s proposal, multiple different
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`combinations of layers in a single device could alternatively be considered to be a “transistor array
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`10
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`substrate.” Ex. 3 (Flasck Depo.) at 69:3-11 (“I have seen people consider this whole assembly
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`from the bottom of 2 to the top of – whatever it is; 55, 53 – to be a transistor array substrate, and
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`that – that whole thing could fall within the construction that we have here”), 104:4-105:3.
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`Moreover, Solas’s expert’s testimony demonstrates that Solas’s construction contradicts
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`the specification’s disclosures. Solas’s expert testified that, under Solas’s proposal, in a device
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`having the structure shown in Figure 6 of the ’338 patent, the transistor array substrate “could” be
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`considered to be layers 2 through 32. Ex. 3 (Flasck Depo.) at 105:4-21 (“I believe the bottom of
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`layer 2 to the top of layer 32 could be considered a transistor array substrate as [Solas’s] proposed
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`construction states”). In other words, applying Solas’s construction, the transistor array substrate
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`may not include planarization film 33. The specification, however, explicitly identifies
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`planarization film 33—which is on top of layer 32—as being within the transistor array substrate.
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`See Ex. 1 (’338 patent) at 10: 45-47, 11:50-53. This is a crucial failing in Solas’s construction,
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`particularly given that the patent claims define other structures by reference to the surface of the
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`transistor array substrate: the interconnections “project from” a surface of the transistor array
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`substrate, and the pixel electrodes are “on the surface of the transistor array substrate.”
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`Under Solas’s proposal, there is not even a basis to include within the transistor array
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`substrate numerous layers that the specification expressly identifies as portions of the transistor
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`array substrate. For instance, planarization layer 33 is neither beneath the array of transistors nor
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`a layer that contains transistors. Yet, the ’338 patent is explicit that planarization layer 33 is part
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`of the claimed “transistor array substrate.” Ex. 1 at 11:50-53.
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`Notably, Solas criticizes Defendants’ proposal on the ground that it would create ambiguity
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`in what layers constitute the transistor array substrate, based on the incorrect premise that the
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`“electrode” in Defendants’ proposal could be any electrode, and not the pixel electrode (as
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`11
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
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`Defendants had intended and thought was clear). Dkt. 74 at 11-12. Solas is wrong, because
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`Defendants’ proposal refers to the pixel electrode. See supra at n.2. Yet Solas’s argument
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`highlights a fundamental failing in Solas’s construction: it provides no basis to determine whether
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`particular layers of a device are within or outside the “transistor array substrate,” and as a result
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`the scope of the claim could not be ascertained with reasonable certainty. A factfinder would have
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`no way of determining under Solas’s construction whether a given set of layers are properly
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`considered to be part of the transistor array substrate or not.
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`Thus, consistent with all of the intrinsic evidence, “transistor array substrate” should be
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`construed as “a layered structure composed of a bottom insulating layer through a topmost layer
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`on whose upper surface [pixel] electrodes are formed, which contains an array of transistors.”
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`2. “project from a surface of the transistor array substrate” (claim 1)
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`Defendants’ Proposal
`“extend above the upper surface of the
`transistor array substrate”
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`Plaintiff’s Proposal
`“extend from a surface of the transistor array
`substrate”
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`Claim 1 states that the claimed display panel comprises “a plurality of interconnections
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`which are formed to project from a surface of the transistor array substrate, and which are arrayed
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`in parallel to each other.” The parties’ dispute centers on whether this means that the
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`interconnections extend beyond the boundary of the transistor array substrate, as Defendants
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`propose and the ’338 patent describes, or whether the interconnections may be fully embedded
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`within the transistor array substrate, as Solas proposes. The plain meaning of the claim language
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`and the disclosures of the specification all support Defendants’ proposal.
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`Although Solas’s brief obscures the true dispute between the parties, Solas’s expert
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`revealed it in his deposition. He testified that materials that are fully embedded within the
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`transistor array substrate—that do not in any way extend outside the transistor array substrate—
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`would, under Solas’s proposal, be said to “project from” a surface of the transistor array substrate.
`12
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
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`See, e.g., Ex. 3 (Flasck Depo.) at 35:17-22 (“Various parts of [transistor] 23 do project from a
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`surface of the transistor array substrate”); 37:21-38:4 (“[Gate insulating] [l]ayer 31 does project
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`from a surface of the transistor array substrate”); 45:15-20; 53:12-54:19; 55:1-10; 74:2-25.
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`Solas takes this position, which flies in the face of the claim language, by (1) incorrectly
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`treating interfaces between sublayers inside the transistor array substrate as being “a surface” of
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`the transistor array substrate, and then (2) positing that an interconnection extending in any
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`direction beyond any such interface purportedly “projects from” the “surface.” In other words,
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`Solas takes the position that the top, bottom, and sides of any sublayer of the transistor array
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`substrate constitutes a “surface” of the transistor array substrate, and an interconnection that
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`extends in any way above or below or to the side “projects from” a “surface” of the transistor array
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`substrate. What this means is that, under Solas’s proposal, any interconnection would necessarily
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`project from a surface of the transistor array substrate. It would be impossible, under Solas’s
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`proposal, for there to exist an interconnection that did not “project from” some “surface” of the
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`transistor array substrate. Solas’s construction effectively reads the “projects from” limitation out
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`of the claim through its use of the term “a surface.” This is improper. Bicon, Inc. v. Straumann
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`Co., 441 F.3d 945, 950 (Fed. Cir. 2006) (“claims are interpreted with an eye toward giving effect
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`to all terms in the claim”).
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`Solas identifies no support in the written description or figures of the ’338 patent for its
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`position that an interconnection that “projects from a surface of the transistor array substrate” but
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`is fully embedded inside the transistor array substrate. There is no such support. On the contrary,
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`Solas’s construction is belied by the claim language and the specification.
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`The plain meaning of the claim language “interconnections which are formed to project
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`from a surface of the transistor array substrate” is that the interconnections extend outside the
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`13
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
`
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`transistor array substrate. The plain meaning alone requires rejection of Solas’s position that the
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`interconnections can be entirely embedded within the transistor array substrate.
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`Further, the specification strongly supports Defendants’ construction. Consistent with the
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`plain meaning of “projects from,” the specification explains that the interconnections extend
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`beyond the upper surface of the transistor array substrate. The specification explains “[t]he
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`common interconnection 91 is formed by electroplating and is therefore formed to be much thicker
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`than the signal line Y, scan line X, and supply line Z and project upward from the surface of the
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`planarization film 33.” Ex. 1 (’338 patent) at 10:54-58 (emphasis added). The specification then
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`explains that “[t]he thickness of the select interconnection 89 and feed interconnection 90 is larger
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`than the total thickness of the protective insulating film 32 and planarization film 33 so that the
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`select interconnection 89 and feed interconnection 90 project upward from the upper surface of
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`the planarization film 33.” Id. at 11:36-41 (emphasis added). The specification also makes clear
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`that the upper surface of the planarization film is the upper surface of the transistor array substrate.
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`See, e.g., id. at 10:49-50 (“the upper surface of the planarization film 33, i.e., the upper surface of
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`the transistor array substrate 50”) (emphasis added); 11:50-52 (same); 10:45-47.
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`Defendants’ proposal also aligns with the purpose of the interconnections projecting from
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`a surface of the transistor array substrate. The ’338 patent repeatedly explains that the projecting
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`interconnections “serve as partition walls to prevent leakage of an organic compound-containing
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`solution.” Ex. 1 (’338 patent) at 6:24-30; see also id. at 6:38-42. To serve as these partition walls,
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`the interconnections must extend past the upper surface of the transistor array substrate. This is
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`precisely what the specification of the ’338 patent describes and its Figures illustrate: all
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`interconnections (89, 90, and 91 in Figure 6) extend above the upper surface (33) of the transistor
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`array substrate:
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`14
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`Samsung Display Co., Ltd., v Solas OLED Ltd.
`Exhibit 2002
`IPR2020-00320
`
`

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`In fact, in language that parallels the claim language, the specification explains that
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`projecting interconnections extend above the upper surface of the transistor array substrate to
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`prevent leakage of the organic electroluminescent compound: “[t]he thick sele