SAMSUNG DISPLAY CO., LTD.
`v.
`SOLAS OLED LTD.
`
`IPR2020-00320
`U.S. Patent No. 7,446,338
`Petitioner’s Demonstratives
`March 25, 2021 Oral Hearing
`
`Filed March 18, 2021
`
`Demonstrative Exhibit – Not Evidence
`
`1
`
`SAMSUNG EX. 1029
`
`
`v.
`SOLAS OLED LTD.
`
`IPR2020-00320
`U.S. Patent No. 7,446,338
`Petitioner’s Demonstratives
`March 25, 2021 Oral Hearing
`
`Filed March 18, 2021
`
`Demonstrative Exhibit – Not Evidence
`
`1
`
`SAMSUNG EX. 1029
`
`
`
`Grounds of unpatentability
`
` Trial instituted on two obviousness grounds:
`
`Ground 1
`
`Kobayashi and Shirasaki (claims 1, 2, 5, 6, 9–11)
`
`Ground 2
`
`Childs and Shirasaki (claims 1–3, 5–13)
`
`Institution Decision (Paper 9) at 8, 32
`
`Demonstrative Exhibit – Not Evidence
`
`2
`
`
`
`Disputed issues
`
` Ground 1: Kobayashi and Shirasaki
` Motivation to combine
` Reasonable expectation of success
` Limitation 1[b] (interconnections … formed to project from a surface of the
`transistor array substrate)
` Limitation 1[c] (pixel electrodes being arrayed along the interconnections …)
` Ground 2: Childs and Shirasaki
` Motivation to combine
` Reasonable expectation of success
` Limitation 1[c] (pixel electrodes being arrayed along the interconnections …)
` No disputes about any other limitations of independent claim 1,
`nor about any dependent claims
`
`See generally POR (Paper 18); Pet. Reply (Paper 23); P.O. Sur-Reply (Paper 25)
`
`Demonstrative Exhibit – Not Evidence
`
`3
`
`
`
`Independent claim 1
`
` 1[pre]
`
`A display panel comprising:
`
` 1[a]
`
` 1[b]
`
` 1[c]
`
` 1[d]
`
` 1[e]
`
` 1[f]
`
`a transistor array substrate which includes a plurality of pixels and comprises a plurality of
`transistors for each pixel, each of the transistors including a gate, a gate insulating film, a source,
`and a drain;
`
`a plurality of interconnections which are formed to project from a surface of the transistor array
`substrate, and which are arrayed in parallel to each other;
`
`a plurality of pixel electrodes for the plurality of pixels, respectively, the pixel electrodes being
`arrayed along the interconnections between the interconnections on the surface of the transistor
`array substrate;
`
`a plurality of light emitting layers formed on the pixel electrodes, respectively and
`
`a counter electrode which is stacked on the light-emitting layers,
`
`wherein said plurality of transistors for each pixel include [1] a driving transistor, one of the source
`and the drain of which is connected to the pixel electrode, [2] a switch transistor which makes a
`write current flow between the drain and the source of the driving transistor, and [3] a holding
`transistor which holds a voltage between the gate and source of the driving transistor in a light
`emission period.
`
`Pet. (Paper 1) at 12–13; ’338 patent (Ex. 1001)
`
`Demonstrative Exhibit – Not Evidence
`
`4
`
`
`
`Claim constructions
`
`Term
`
`transistor array substrate
`
`write current
`project from a surface of the
`transistor array substrate
`
`the pixel electrodes being
`arrayed along the
`interconnections between
`the interconnections on the
`surface of the transistor
`array substrate
`
`Constructions proposed in
`Petition
`a layered structure including a
`bottom insulating substrate through
`a topmost insulating layer on whose
`surface the pixel electrodes are
`formed*
`
`N/A
`extend above the upper surface of
`the topmost layer of the transistor
`array substrate
`pixel electrodes: (1) are arrayed
`along the interconnections between
`the interconnections; and (2) are
`arrayed on the surface of the
`transistor array substrate
`
`*Agreed to in Patent Owner Preliminary Response
`
`District Court constructions
`(“applied in [the] POR”)
`layered structure upon which or within
`which a transistor array is fabricated
`
`pull-out current
`extend beyond an outer surface of the
`transistor array substrate
`
`the pixel electrodes are arrayed along
`the interconnections and located
`between the interconnections, and the
`pixel electrodes are on the surface of
`the transistor array substrate
`
`Pet. (Paper 1) at 21–25; POPR (Paper 3) at 28; POR (Paper 18) at 12–13
`
`Demonstrative Exhibit – Not Evidence
`
`5
`
`
`
`GROUND 1: KOBAYASHI AND SHIRASAKI
`
`Demonstrative Exhibit – Not Evidence
`
`6
`
`
`
`Kobayashi teaches a display with interconnections formed to
`project from the surface of its transistor array substrate
`
`interconnections
`(“auxiliary wiring elements 118”)
`
`insulating “partition
`walls 120”
`
`pixel electrodes
`(“first electrode 117
`display element P”)
`
`transistor array substrate
`(“insulative support
`substrate 101” through
`“insulating layer 116”)
`
`Kobayashi (Ex. 1003) at Fig. 7 (annotated)
`
`Pet. (Paper 1) at 29–32, 39–50; Pet. Reply (Paper 23) at 14–15
`
`Demonstrative Exhibit – Not Evidence
`
`7
`
`
`
`The Shirasaki reference discloses the same transistor
`structure as claimed in the Shirasaki ’338 patent
`
`Shirasaki (Ex. 1004) at Fig. 5A (annotated)
`
`’338 Patent (Ex. 1001) at Fig. 2 (annotated)
`
`See Pet. Reply (Paper 23) at 13 (explaining that Shirasaki’ s “memory current” α, which flows
`when “transistor 11” (switch transistor) is turned on, is the same as ’338 patent’s “pull-out current”
`A)
`Pet. (Paper 1) at 32–34, 52–53; Pet. Reply (Paper 23) at 12–14
`
`Demonstrative Exhibit – Not Evidence
`
`8
`
`
`
`The experts agree that Shirasaki discloses the same
`transistor structure as claimed in the ’338 patent
`
`Shirasaki (Ex. 1004) at Fig. 5A (annotated)
`
`Q And do you recognize Figure 5 of
`Shirasaki as showing the same three-
`transistor, one-capacitor structure that's
`disclosed in the ’338 patent?
`
`A In terms of the use of three
`transistors and a capacitor, it's similar.
`* * *
`Q But otherwise, with respect to how
`the transistors and the capacitor are
`connected to one another, the circuits
`are the same. Correct?
`
`A In terms of how the transistors and
`capacitors connect to one another,
`they’re the same.
`
`Fontecchio Decl. (Ex. 1018) at ¶ 53
`
`Flasck Deposition (Ex. 1025) at 43:6–44:5
`
`Pet. (Paper 1) at 27–28; Pet. Reply (Paper 23) at 12–14
`
`Demonstrative Exhibit – Not Evidence
`
`9
`
`
`
`Shirasaki presents its circuit as improving on conventional
`two-transistor voltage-controlled circuits (as in Kobayashi)
`
`Pet. (Paper 1) at 34, 53–56; Pet. Reply (Paper 23) at 5–7
`
`Demonstrative Exhibit – Not Evidence
`
`10
`
`
`
`Shirasaki identifies drawbacks of conventional two-
`transistor voltage-controlled circuits (as in Kobayashi)
`
`Shirasaki (Ex. 1004) at [0007].
`
`Pet. (Paper 1) at 53–54; Pet. Reply (Paper 23) at 5–7
`
`Demonstrative Exhibit – Not Evidence
`
`11
`
`
`
`Shirasaki explains benefits of replacing conventional two-
`transistor voltage-controlled circuits (as in Kobayashi) with its
`three-transistor current-controlled circuit
`
`Shirasaki (Ex. 1004) at [0011].
`
`Shirasaki (Ex. 1004) at [0018].
`
`Shirasaki (Ex. 1004) at Fig. 5A.
`
`Pet. (Paper 1) at 53–54; Pet. Reply (Paper 23) at 5–7
`
`Demonstrative Exhibit – Not Evidence
`
`12
`
`
`
`It would have been straightforward to replace Kobayashi’s
`two-transistor voltage-controlled circuit with Shirasaki’s three-
`transistor current-controlled circuit
`Shirasaki explains how to connect the three transistors to one another and associated signal lines
`
`Q So in Paragraph 68 Shirasaki actually describes how
`the transistors we were just looking at are connected to
`one another and to the various signal lines. Correct?
`
`A Generally, yes.
`
`Flasck Deposition (Ex. 1025) at 44:10–14
`
`Shirasaki (Ex. 1004) at [0068]
`
`Shirasaki (Ex. 1004) at [0042]
`
`Shirasaki (Ex. 1004) at Fig. 5A
`
`Pet. Reply (Paper 23) at 9–10
`
`Demonstrative Exhibit – Not Evidence
`
`13
`
`
`
`It would have been straightforward to replace Kobayashi’s
`two-transistor voltage-controlled circuit with Shirasaki’s three-
`transistor current-controlled circuit
`Shirasaki teaches that well-known drive circuitry can be used
`and provides an illustrative timing diagram (Fig. 7)
`
`Q And to be clear, Shirasaki didn't invent shift
`registers. Right?
`
`A No. Shift registers have been around for close
`to a hundred years.
`
`* * *
`Q There were current sink drivers known in the
`prior art prior to Shirasaki. Right?
`
`A Yes.
`
`Flasck Deposition Tr. (Ex. 1025) at 50:14–17, 53:8–10
`
`Shirasaki (Ex. 1004) at [0069], [0070], [0072]
`
`Pet. Reply (Paper 23) at 10–11
`
`Demonstrative Exhibit – Not Evidence
`
`14
`
`
`
`1[b]: “a plurality of interconnections which are formed to
`project from a surface of the transistor array substrate, and
`which are arrayed in parallel to each other”
`Kobayashi includes projecting “auxiliary wiring elements 118,” which extend beyond an outer
`surface of the transistor array substrate, and are arrayed in parallel
`
`interconnections
`(“auxiliary wiring
`elements 118”)
`
`transistor array substrate
`(“insulative support substrate 101”
`through “insulating layer 116”)
`
`Kobayashi (Ex. 1003) at Fig. 7 (annotated)
`
`Kobayashi (Ex. 1003) at Fig. 1 (annotated)
`
`Pet. (Paper 1) at 44–46; Pet. Reply (Paper 23) at 14–19
`
`Demonstrative Exhibit – Not Evidence
`
`15
`
`
`
`Kobayashi’s interconnections project from its transistor
`array substrate in the same way as the ’338 patent’s
`projecting “common interconnection 91”
`
`interconnections
`(“auxiliary wiring
`elements 118”)
`
`insulating “partition
`walls 120”
`
`“common
`interconnection 91”
`
`“insulating line 61”
`
`transistor array substrate
`(“insulative support substrate 101”
`through “insulating layer 116”)
`
`“transistor array substrate 50”
`(“The layered structure from the
`insulating substrate 2 to the
`planarization film 33”)
`
`Kobayashi (Ex. 1003) at Fig. 7 (annotated)
`
`’338 Patent (Ex. 1001) at Fig. 6 (annotated)
`
`Pet. Reply (Paper 23) at 17–19
`
`Demonstrative Exhibit – Not Evidence
`
`16
`
`
`
`The ’338 patent describes “common interconnection 91” as
`“project[ing] upward” from the transistor array substrate despite the
`presence of insulating line 61
`
`“common
`interconnection 91”
`
`“insulating line
`61”
`
`“transistor array
`substrate 50”
`(“The layered structure
`from the insulating
`substrate 2 to the
`planarization film 33”)
`
`’338 Patent (Ex. 1001) at
`Fig. 6 (annotated)
`
`’338 Patent (Ex. 1001) at 10:54–58
`
`’338 Patent (Ex. 1001) at 12:62–67
`
`Pet. (Paper 1) at 23–24; Pet. Reply (Paper 23) at 17–19
`
`Demonstrative Exhibit – Not Evidence
`
`17
`
`
`
`Kobayashi’s “auxiliary wiring elements” decrease resistance to
`improve uniformity, just like the ’338 patent’s “common
`interconnections”
`
`Kobayashi (Ex. 1003) at ¶ [0083]
`
`Pet. (Paper 1) at 44–45
`
`Demonstrative Exhibit – Not Evidence
`
`18
`
`’338 Patent (Ex. 1001) at 14:8–19
`
`
`
`Solas’s belated “starting point” theory is inconsistent with
`the ’338 patent’s disclosure and the claim construction
`
`Term
`
`project from a
`surface of the
`transistor array
`substrate
`
`District Court construction
`(“applied in [the] POR”)
`extend beyond an outer
`surface of the transistor
`array substrate
`
`Thus, the claim term “from”
`introduces an obvious
`additional spatial requirement
`beyond just being located
`above a surface. Specifically,
`the surface must also be a
`“starting point” from which
`the interconnection projects.
`
`P.O. Sur-Reply (Paper 25) at 5
`(citing newly identified web dictionaries)
`
`“common
`interconnection 91”
`
`“insulating
`line 61”
`
`“transistor
`array
`substrate 50”
`
`’338 Patent (Ex. 1001) at Fig. 6 (annotated)
`
`’338 Patent (Ex. 1001) at 10:54–58
`
`Pet. Reply (Paper 23) at 17–18; P.O. Sur-Reply (Paper 25) at 5; POR (Paper 18) at 12–13
`
`Demonstrative Exhibit – Not Evidence
`
`19
`
`
`
`Solas’s arguments about distances in figures are
`misplaced
`
`“[I]t is well established that patent
`drawings do not define the precise
`proportions of the elements and may not be
`relied on to show particular sizes if the
`specification is completely silent on the
`issue.”
`
`Hockerson-Halberstadt, Inc. v. Avia Grp. Int’l, Inc., 222 F.3d
`951, 956 (Fed. Cir. 2000)
`
`The common interconnections 91 . . . begin near that
`surface and extend a significant distance away from the
`surface, both relative to their distance from the surface
`and relative to their overall dimensions. (Id.) The
`auxiliary wiring elements 118 in Kobayashi, on the
`other hand, do not “project from a surface” of the
`yellow layers. (Id.) They are far above the surface,
`relative to their own dimensions, and their extent in the
`vertical direction (the direction they would need to be
`“projecting” or “protruding” is small relative to the
`other relevant dimensions. (Id.)
`
`POR (Paper 18) at 29–30
`
`POR (Paper 18) 29–30; Pet. Reply (Paper 23) at 18–19
`
`Demonstrative Exhibit – Not Evidence
`
`20
`
`
`
`Solas’s IPR expert (Mr. Flasck) makes the same
`argument as Solas’s district court expert (Mr. Credelle)
`
`Flasck Declaration (Ex. 2005) at ¶ 95
`(Oct. 21, 2020)
`
`Credelle Expert Report (Ex. 1024) at ¶ 221
`(June 22, 2020)
`
`Pet. Reply (Paper 23) at 16–17
`
`Demonstrative Exhibit – Not Evidence
`
`21
`
`
`
`The district court correctly struck Solas’s argument as
`inconsistent with the court’s construction (the same
`construction that Solas purports to apply in its POR)
`
`9/8/2020 Pretrial Heating Tr. (Ex. 1026) at 88:8–17
`
`Credelle Expert Report (Ex. 1024) at ¶ 221
`(June 22, 2020)
`
`Pet. Reply (Paper 23) at 16–17
`
`Demonstrative Exhibit – Not Evidence
`
`22
`
`
`
`Solas’s expert, Mr. Flasck, was unaware of the district
`court’s ruling and conceded it “may change” his opinion
`
`Q Now, I will represent to you that the court in the
`district court litigation struck Paragraph 221 of Mr.
`Credelle’s report. With that understanding, does that
`change your opinion as to whether the court's
`construction requires that there, quote, be some
`connection or relationship between the thing projecting
`and the surface it is projecting from, end quote?
`
`A I would -- I would have to read and consider the
`relevant documents. It -- it may change my opinion,
`depending on what the documents say.
`
`Flasck Deposition Tr. (Ex. 1025) at 85:12–86:2
`(Nov. 16, 2020)
`
`Pet. Reply (Paper 23) at 16–17
`
`Demonstrative Exhibit – Not Evidence
`
`23
`
`
`
`Mr. Flasck’s declaration deserves little, if any, weight
`
`Q But in writing your declaration for this IPR matter, you didn’t
`discuss your opinions with Mr. Credelle. Correct?
`
`A That's correct.
`
`Flasck Deposition Tr.
`(Ex. 1025) at 11:12–15
`
`Flasck Declaration (Ex. 2005) at ¶ 127
`(Oct. 21, 2020)
`
`Pet. Reply (Paper 23) 16–17
`
`Credelle Expert Report (Ex. 1024) at ¶ 237
`(June 22, 2020)
`
`Demonstrative Exhibit – Not Evidence
`
`24
`
`
`
`Mr. Flasck’s declaration deserves little, if any, weight
`
`Q But in writing your declaration for this IPR matter, you didn’t
`discuss your opinions with Mr. Credelle. Correct?
`
`A That's correct.
`
`Flasck Deposition Tr.
`(Ex. 1025) at 11:12–15
`
`Flasck Declaration (Ex. 2005) at ¶ 104
`(Oct. 21, 2020)
`
`Credelle Expert Report (Ex. 1024) at ¶ 228
`(June 22, 2020)
`
`Pet. Reply (Paper 23) 16–17
`
`Demonstrative Exhibit – Not Evidence
`
`25
`
`
`
`Mr. Flasck’s declaration deserves little, if any, weight
`
`Flasck Declaration (Ex. 2005) at ¶ 84
`(Oct. 21, 2020)
`
`POR (Paper 18) at 30–31
`(Oct. 2, 2020)
`
`Pet. Reply (Paper 23) 16–17
`
`Demonstrative Exhibit – Not Evidence
`
`26
`
`
`
`1[c]: “a plurality of pixel electrodes . . . arrayed along . . .
`the interconnections . . . between the interconnections”
`
`Kobayashi discloses a plurality of first electrodes 117,
`arrayed along and between the auxiliary wiring elements 118
`
`interconnections
`(“auxiliary wiring
`elements 118”)
`
`pixel electrodes
`(“first electrode 117
`display element P”)
`
`Kobayashi (Ex. 1003) at Fig. 7 (annotated)
`
`Pet. (Paper 1) at 46–49; Pet. Reply (Paper 23) at 19–20
`
`Demonstrative Exhibit – Not Evidence
`
`27
`
`
`
`Solas appears to argue that Kobayashi’s first electrodes are not
`arrayed along and between the interconnections because they are
`not coplanar
`
`But such a requirement would be inconsistent with the disclosures of the ’338
`patent, which describe and show an arrangement nearly identical to Kobayashi’s
`
`interconnections
`(“auxiliary wiring
`elements 118”)
`
`pixel electrodes
`(“first electrode 117
`display element P”)
`
`“feed
`interconnections
`90”
`
`“common
`interconnection 91”
`
`“select
`interconnections
`89”
`
`Kobayashi (Ex. 1003) at Fig. 7 (annotated)
`
`“sub-pixel electrodes 20a”
`
`’338 Patent (Ex. 1001) at Fig. 6 (annotated)
`
`Pet. Reply (Paper 23) at 19–21
`
`Demonstrative Exhibit – Not Evidence
`
`28
`
`
`
`The ’338 patent explains electrodes 20a are “arrayed . . .
`between” common interconnection 91 and the other
`interconnections
`The ’338 patent depicts an arrangement of electrodes 20a nearly identical to
`Kobayashi’s, in which pixel electrodes are on a lower plane than interconnections 91
`
`“feed
`interconnections
`90”
`
`“common
`interconnection 91”
`
`“select
`interconnections 89”
`
`“sub-pixel electrodes 20a”
`
`’338 Patent (Ex. 1001) at Fig. 6 (annotated)
`
`’338 Patent (Ex. 1001) at 12:33–54
`
`Pet. (Paper 1) at 25–26; Pet. Reply (Paper 23) at 21
`
`Demonstrative Exhibit – Not Evidence
`
`29
`
`
`
`GROUND 2: CHILDS AND SHIRASAKI
`
`Demonstrative Exhibit – Not Evidence
`
`30
`
`
`
`Childs teaches a display with interconnections formed to
`project from the surface of its transistor array substrate
`
`interconnections (“conductive
`barrier material 240 that is used
`as an interconnection”)
`
`pixel electrode
`(“lower electrode 21”)
`
`transistor array substrate
`(“circuit substrate 100”)
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`Pet. (Paper 1) at 34–37; 63–76; Pet. Reply (Paper 23) at 28–29
`
`Demonstrative Exhibit – Not Evidence
`
`31
`
`
`
`Childs’s “conductive barrier material” decreases resistance, just
`like the ’338 patent’s “common interconnections”
`
`Childs (Ex. 1005) at 3:17–25
`
`Fontecchio Decl. (Ex. 1018) at ¶ 96
`
`Pet. (Paper 1) at 35–37, 69
`
`Demonstrative Exhibit – Not Evidence
`
`32
`
`
`
`Childs confirms that its interconnections can be used
`with alternative circuit structures
`
`interconnections (“conductive barrier material
`240 that is used as an interconnection”)
`
`Childs (Ex. 1005) at 7:6–9
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`Pet. (Paper 1) at 81–82; Pet. Reply (Paper 23) at 24
`
`Demonstrative Exhibit – Not Evidence
`
`33
`
`
`
`Shirasaki presents its circuit as improving on conventional
`two-transistor voltage-controlled circuits (as in Childs)
`
`Childs 2-Transistor Circuit
`Ex. 1005, Fig. 1 (annotated excerpt)
`
`Pet. (Paper 1) at 34, 77–81; Pet. Reply (Paper 23) at 22–23
`
`Demonstrative Exhibit – Not Evidence
`
`34
`
`
`
`Shirasaki identifies drawbacks of conventional two-
`transistor voltage-controlled circuits (as in Childs)
`
`Shirasaki (Ex. 1004) at [0007]
`
`Pet. (Paper 1) at 79–80; Pet. Reply (Paper 23) at 22–23
`
`Demonstrative Exhibit – Not Evidence
`
`35
`
`
`
`Shirasaki explains benefits of replacing conventional two-
`transistor voltage-controlled circuits (as in Childs) with its three-
`transistor current-controlled circuit
`
`Shirasaki (Ex. 1004) at [0011]
`
`Shirasaki (Ex. 1004) at [0018]
`
`Shirasaki (Ex. 1004) at Fig. 5A
`
`Pet. (Paper 1) at 79–80; Pet. Reply (Paper 23) at 22–23
`
`Demonstrative Exhibit – Not Evidence
`
`36
`
`
`
`A POSA would have reasonably expected success in
`applying Shirasaki’s teachings to Childs
`
`Childs explains that the photolithographic, masking, and etching techniques needed
`to modify the pixel circuit were “known” prior to the ’338 patent
`
`Childs (Ex. 1005) at 14:29–15:2; see also Fontecchio Decl. (Ex. 1018) ¶ 215
`
`See also slides 13-14 (Shirasaki’s explanations of the requisite
`connections, operation, and drive circuitry for its three-transistor circuit)
`
`Pet. (Paper 1) at 81–82; Pet. Reply (Paper 23) at 24–25
`
`Demonstrative Exhibit – Not Evidence
`
`37
`
`
`
`1[c]: “a plurality of pixel electrodes . . . arrayed along . . .
`the interconnections . . . between the interconnections”
`
`Childs discloses a plurality of lower electrodes 21, arrayed along and
`between the conductive barriers 240
`
`interconnections (“conductive
`barrier material 240 that is used
`as an interconnection”)
`
`pixel electrodes
`(“lower electrodes 21”)
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`Pet. (Paper 1) at 69–70; Pet. Reply (Paper 23) at 28
`
`Demonstrative Exhibit – Not Evidence
`
`38
`
`
`
`Solas appears to argue that Childs’s lower electrodes are not
`arrayed along and between the interconnections because they are
`not coplanar
`
`But such a requirement would be inconsistent with the disclosures of the ’338
`patent, which describe and show an arrangement nearly identical to Childs’s
`
`interconnections (“conductive
`barrier material 240”)
`
`pixel electrodes
`(“lower electrodes 21”)
`
`“feed
`interconnections
`90”
`
`“common
`interconnection 91”
`
`“select
`interconnections
`89”
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`’338 Patent (Ex. 1001) at Fig. 6 (annotated)
`
`Pet. Reply (Paper 23) at 28
`
`Demonstrative Exhibit – Not Evidence
`
`39
`
`“sub-pixel electrodes 20a”
`
`
`
`The ’338 patent describes electrodes 20a as “arrayed . . .
`between” common interconnection 91 and the other
`projecting interconnections
`The ’338 patent depicts an arrangement of electrodes 20a nearly identical to
`Kobayashi’s, in which pixel electrodes are on a lower plane than interconnections 91
`
`“feed
`interconnections
`90”
`
`“common
`interconnection 91”
`
`“select
`interconnections
`89”
`
`’338 Patent (Ex. 1001) at
`Fig. 6 (annotated)
`
`“sub-pixel electrodes 20a”
`
`See also ’338 Patent (Ex. 1001) at 5:61–64 (“[T[he plurality of subpixel
`electrodes 20a are arrayed in the horizontal direction between the feed
`interconnection 90 and the adjacent common interconnection 91.”).
`
`’338 Patent (Ex. 1001) at 12:33–54
`
`Pet. (Paper 1) at 25–26; Pet. Reply (Paper 23) at 28
`
`Demonstrative Exhibit – Not Evidence
`
`40
`
`
`
`1[c]: “a plurality of pixel electrodes . . . on the surface of the
`transistor array substrate”
`
`Childs discloses a plurality of lower electrodes 21 formed on the
`surface of the transistor array substrate
`
`“window 12a in a planar insulating layer 12 …
`that extends over the thin-film structure”
`
`pixel electrodes
`(“lower electrode 21”)
`
`transistor array
`substrate
`(“circuit substrate
`100”)
`
`Childs (Ex. 1005) at
`8:22-24 (emphasis
`added)
`
`Pet. (Paper 1) at 71; Pet. Reply (Paper 23) at 29
`
`Demonstrative Exhibit – Not Evidence
`
`41
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`
`
`1[c]: “a plurality of pixel electrodes . . . on the surface of the
`transistor array substrate”
`
`To the extent there is any question that Childs’s lower electrodes are “on
`the surface,” it would have been obvious to form lower electrodes 21 on
`the surface of an insulating layer to simplify manufacturing
`
`Pet. (Paper 1) at 71–75; Pet. Reply (Paper 23) at 29–32
`
`Demonstrative Exhibit – Not Evidence
`
`42
`
`Fontecchio Decl. (Ex. 1018) at ¶ 180
`
`
`
`1[c]: “a plurality of pixel electrodes . . . on the surface of the
`transistor array substrate”
`
`Obvious modification of forming electrodes on
`surface of insulating layer 12:
`
`Childs (Ex. 1005) at
`8:22-24 (emphasis
`added)
`
`Childs (Ex. 1005) at Fig. 2 (annotated)
`
`As Dr. Fontecchio explained, it
`would have been obvious to a POSA
`to extend planar insulating layer 12
`(eliminating the “windows”) and
`form the lower electrode atop this
`surface, which would protect
`aluminum electrodes 3 and 4 from
`additional etching or oxygen
`contamination and simplify the
`manufacturing process. Ex. 1018, ¶¶
`[0188]–[0191].7 A POSA would
`recognize this modification would
`reduce the number of overall
`manufacturing steps by eliminating
`steps otherwise necessary to protect
`the aluminum electrodes and by
`eliminating etching of planar
`insulating layer 12 to form
`“windows.” See id.
`
`Pet. Reply (Paper 23) at 29–30
`(emphasis added)
`
`Pet. (Paper 1) at 71–75; Pet. Reply (Paper 23) at 29–32
`
`Demonstrative Exhibit – Not Evidence
`
`43
`
`
`
`1[c]: “a plurality of pixel electrodes . . . on the surface of the
`transistor array substrate”
`
`The modifications Dr. Fontecchio identified were obvious design
`choices that would simplify the manufacturing process
`
`Pet. (Paper 1) at 74–75; Pet. Reply (Paper 23) at 29–30
`
`Demonstrative Exhibit – Not Evidence
`
`44
`
`Fontecchio Decl. (Ex. 1018) at ¶ 188
`
`
`
`The alleged drawbacks Solas asserts are speculative,
`and also wrongly assume that Childs’s device must be
`bottom-emitting
`
`* * *
`
`* * *
`
`* * *
`
`Childs (Ex. 1005) at 9:1–17
`
`Pet. Reply (Paper 23) at 30–31
`
`Demonstrative Exhibit – Not Evidence
`
`45
`
`POR (Paper 18) at 46–48
`
`
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