(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`I IIIII IIIIIIII II IIIIII IIIII IIII I II Ill lllll lllll lllll lllll lllll llll 1111111111111111111
`
`(43) International Publication Date
`25 September 2003 (25.09.2003)
`
`PCT
`
`(10) International Publication Number
`WO 03/079449 Al
`
`(51) International Patent Classification 7:
`51/20
`
`BOIL 27/15,
`
`(21) International Application Number:
`
`PCT/IB03/01000
`
`(22) International Filing Date: 19 March 2003 (19.03.2003)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`(30) Priority Data:
`0206551.4
`0209562.8
`0216055.4
`
`20 March 2002 (20.03.2002) GB
`26 April 2002 (26.04.2002) GB
`11 July 2002 (11.07.2002) GB
`
`(71) Applicant (]or all designated States except US): KONIN(cid:173)
`KLIJKE PHILIPS ELECTRONICS N.V. [NL/NL];
`Groenewoudseweg 1, NL-5621 BA Eindhoven (NL).
`
`(72) Inventors; and
`(75) Inventors/Applicants (]or US only): YOUNG, Nigel, D.
`[GB/GB]; Prof . Holstlaan 6, NL-5656 AA Eindhoven
`
`--
`
`(NL). CHILDS, Mark, J. [GB/GB]; Prof. Holstlaan 6,
`NL-5656 AA Eindhoven (NL). FISH, David, A. [GB/GB];
`Prof. Holstlaan 6, NL-5656 AA Eindhoven (NL). HEC(cid:173)
`TOR, Jason, R. [GB/GB]; Prof. Holstlaan 6, NL-5656
`AA Eindhoven (NL).
`
`(74) Agent: WHITE, Andrew, G.; Internationaal Octrooibu(cid:173)
`reau B.V., Prof. Holstlaan 6, NL-5656 AA Eindhoven
`(NL).
`
`(81) Designated States (national): AE, AG, AL, AM, AT, AU,
`AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU,
`CZ, DE, DK, DM, DZ, EC, EE, ES, Fl, GB, GD, GE, GH,
`GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC,
`LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW,
`MX, MZ, NI, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD,
`SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US,
`UZ, VC, VN, YU, ZA, ZM, ZW.
`
`(84) Designated States (regional): ARIPO patent (GH, GM,
`KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW),
`Eurasian patent (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM),
`European patent (AT, BE, BG, CH, CY, CZ, DE, DK, EE,
`ES, Fl, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO,
`
`[Continued on next page]
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`--;;;;;;;;;;;;;;
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`--------------------------------------------
`(54) Title: ACTIVE MATRIX ELECTROLUMINESCENT DISPLAY DEVICES, AND THEIR MANUFACTURE
`
`500
`
`400s
`
`n r ---.4,-.40---t-_ _ l------,
`
`°" "'1'
`"'1' °"
`
`4,160
`21 22 23
`~
`25(LED)
`
`4,160
`
`~ (57) Abstract: Physical barriers (210) are present between neighbouring pixels (200) on a circuit substrate (100) of an active-matrix
`-..... electroluminescent display device, particularly with LEDs (25) of organic semiconductor materials. The invention forms these bar(cid:173)
`~ riers (210) with metal or other electrically-conductive material (240) that serves as an interconnection between a first circuit element
`(21, 4, 5, 6, 140, 150, 160, Tl, T2, Tm, Tg, Ch) of the circuit substrate and a second circuit element (400, 400s, 23), for example, a
`0 sensor ( 400s) of a sensor array supported over the pixel array. The conductive barrier material (240) is insulated ( 40) at the sides of
`> the barriers adjacent to the LEDs and has an un-insulated top connection area (240t) at which the second circuit element is connected
`
`;;, to the conductive barrier material (240).
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`I IIIII IIIIIIII II IIIIII IIIII IIII I II Ill lllll lllll lllll lllll lllll llll 1111111111111111111
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`SE, SI, SK, TR), OAPI patent (BF, BJ, CF, CG, CI, CM, For two-letter codes and other abbreviations, refer to the "Guid(cid:173)
`ance Notes on Codes and Abbreviations" appearing at the begin(cid:173)
`GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
`ning of each regular issue of the PCT Gazette.
`
`Published:
`with international search report
`before the expiration of the time limit for amending the
`claims and to be republished in the event of receipt of
`amendments
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`DESCRIPTION
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`10
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`ACTIVE MATRIX ELECTROLUMINESCENT DISPLAY DEVICES, AND
`
`THEIR MANUFACTURE.
`
`This
`
`invention relates
`
`to active-matrix electroluminescent display
`
`light-emitting diodes of
`devices, particularly but not exclusively using
`semiconducting conjugated polymer or other organic semiconductor materials.
`
`The invention also relates to methods of manufacturing such devices.
`
`Such active-matrix electroluminescent display devices are known,
`comprising an array of pixels present on a circuit substrate, wherein each pixel
`
`comprises an electroluminescent element, typically of organic semiconductor
`
`material. The electroluminescent elements are connected to circuitry in the
`
`substrate, for example drive circuitry that includes supply lines and matrix
`addressing circuitry that includes addressing (row) and signal (column) lines.
`These lines are generally formed by thin-film conductor layers in the substrate.
`The circuit substrate also includes addressing and drive elements (typically
`
`thin-film transistors, hereafter termed 11TFT 11s} for each pixel.
`
`20
`
`In many such arrays, physical barriers of insulating material are present
`
`between neighbouring pixels in at least one direction of the array. Examples
`
`of such barriers are given in published United Kingdom patent application
`
`GB-A-2 347 017, published PCT patent application WO-A 1-99/43031,
`published European patent applications EP-A-0 895 219, EP-A-1 096 568, and
`EP-A-1 102 317, the whole contents of which are hereby incorporated herein
`
`25
`
`as reference material.
`
`Such barriers are sometimes termed "walls", "partitions", "banks", "ribs",
`"separators", or "dams", for example. As can be seen from the cited
`
`in
`They may be used
`they may serve several functions.
`references,
`30 manufacture to define electroluminescent layers and/or electrode layers of the
`
`individual pixels and/or of columns of pixels. Thus, for example, the barriers
`prevent pixel overflow of conjugate polymer materials that may be ink-jet
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`CONFIRMATION COPY
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`printed for red, green and blue pixels of a colour display or spin-coated for a
`monochrome display. The barriers in the manufactured device can provide a
`well-defined optical separation of pixels. They may also carry or comprise
`as
`upper electrode material
`of
`the
`conductive material
`(such
`electroluminescent element), as auxiliary wiring for reducing the resistance of
`(and hence the voltage drops across) the common upper electrode of the
`
`electroluminescent elements.
`
`It is an aim of the present invention to enhance the capabilities and/or
`performance of active-matrix electroluminescent display devices, in a manner
`that is compatible with the basic device structure, its layout and its electronics.
`
`According to one aspect of the present invention, there is provided an
`active-matrix electroluminescent display device having the features set out in
`Claim 1.
`In accordance with the invention, the physical barriers between pixels
`are used to provide interconnections between a first circuit element of the
`circuit substrate .and a second circuit element that is connected at the top of
`the barrier. Thus, these pixel barriers are partly (possibly even predominantly)
`
`the
`(typically metal) which provides
`of electrically-conductive material
`interconnection, while also being insulated at least at the sides of the barriers
`adjacent to the electroluminescent elements.
`Much versatility is possible in accordance with the invention. Various
`layout features can be adopted for the pixel barriers, depending on the circuit
`elements being interconnected. Thus, the conductive barrier material may.
`provide interconnections that are localised to, for example, individual pixels or
`
`groups of pixels, or interconnections that may be located outside the pixel
`array. Thus, each un-insulated top connection area may itself be localised as
`part of a connection pattern along the top of the barriers, and/or the
`interconnecting conductive barrier material may be localised in, for example,
`separately insulated lengths of the barriers.
`The first and second circuit elements may take a variety of forms,
`depending on the particular improvement or enhancement or adaptation being
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`made. Typically, the first circuit element of the circuit substrate may be one or
`
`more thin-film elements of the group comprising: a conductor layer; an
`
`electrode connection; a supply line; an addressing line; a signal line; a thin-film
`
`t_ransistor; a thin-film capacitor. The second circuit element may be another
`
`5
`
`such thin-film element in the circuit substrate and/or, for example, an electrode
`
`connection of the electroluminescent element of a respective pixel or an added
`
`component such as a sensor.
`
`The last possibility permits various forms of sensor array to be
`
`integrated together with the array of pixels. The sensor array may be
`
`10
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`integrated within the circuit substrate. However, the sensor array may be
`
`supported on top of the barriers and over the pixel array. This provides a
`
`compact layout and
`
`is particularly suitable for direct pen input and/or
`
`finger-print sensing. The sensor array may even share matrix addressing
`
`circuitry of the pixel array in the circuit substrate. This simplifies the integration
`
`15
`
`of the sensor array with the pixel array. Sharing may be achieved in a manner
`
`similar to that disclosed in, for example, United States patents US-A-5,386,543
`
`and US-A-5,838,308 (Philips refs: PHB33816 and PHB33715). The whole
`
`contents of US-A-5,386,543 and US-A-5,838,308 are hereby incorporated
`
`herein as reference material.
`
`20
`
`As well as using the barriers to provide interconnections in accordance
`
`with the present invention, the barriers (or at least other separately insulated
`
`lengths of the barriers) may serve different functions. They may be used to
`
`form, for example, a component such as a capacitor or inductor or transformer
`
`and/or to back-up or replace thin-film conductor lines of the circuit substrate.
`
`25
`
`These back-up or replacement lines may be, for example an address line, a
`
`signal line or a supply line.
`
`According to another aspect of the present invention, there are also
`
`provided advantageous methods of manufacturing such an active-matrix
`
`electroluminescent display device.
`
`30
`
`Various
`
`advantageous
`
`features
`
`and
`
`feature-combinations
`
`in
`
`accordance with the present invention are set out in the appended Claims.
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`These and others are illustrated in embodiments of the invention that are now
`reference
`to
`the accompanying
`described, by way of example, with
`diagrammatic drawings, in which:
`Figure 1 is a circuit diagram for four pixel areas of an active-matrix
`electroluminescent display device which can be provided with interconnections
`in accordance with the invention;
`
`Figure 2 is a cross-sectional view of part of the pixel array and circuit
`substrate of one embodiment of such a device, showing one example of a
`conductive barrier construction for forming interconnections to a TFT source or
`drain line in accordance with the invention;
`
`Figure 3 is a cross-sectional view of part of the pixel array and circuit
`substrate of a similar embodiment of such a device, showing another example
`of a conductive barrier construction for forming interconnections to a TFT gate
`line in accordance with the invention;
`
`Figure 4 is a cross-sectional view of the interconnection part of such an
`embodiment as that of Figure 2 or Figure 3, showing an example of a modified
`conductive barrier construction
`that uses a metal coating for forming
`interconnections in accordance with the invention;
`Figure 5 is a cross-sectional view of part of such a device such as that
`of Figure 2 or Figure 3, showing interconnections in accordance with the
`
`invention for a pressure sensor integrated with the electroluminescent device;
`Figure 6 is a cross-sectional view of part of such a device such as that
`of Figure 2 or Figure 3, showing interconnections in accordance · with the
`invention for a capacitance sensor integrated with the electroluminescent
`device;
`Figure 7 is a cross-sectional view of part of such a device such as that
`of Figure 2 or Figure 3, showing interconnections in accordance with the
`invention for a direct input sensor integrated with the electroluminescent
`device;
`Figure 8 is a cross-sectional view of part of such a device such as that
`
`of Figure 2 or Figure 3, showing interconnections in accordance with the
`invention between upper and lower electrodes of adjacent pixels or sub-pixels;
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`Figure 9 is a plan view of four pixel areas showing a specific example of
`layout features for a particular embodiment of a device in accordance with the
`
`invention, with side-by-side conductive barriers;
`
`Figure 1 O is a cross-sectional view through the side-by-side barriers of
`Figure 9, taken on the line X-X of Figure 9;
`
`5
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`Figure 11 is a plan view of another example of layout features for a
`
`particular embodiment of a device in accordance with the invention, with
`transverse conductive barriers;
`
`Figure 12 is a sectional view of a device part with yet another example
`of a conductive barrier construction for forming interconnections in accordance
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`10
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`with the invention;
`
`Figures 13 to 16 are sectional views of a device part such as that of
`
`its manufacture with one particular
`Figure 2 or Figure 3 at stages in
`embodiment in accordance with the invention; and
`
`15
`
`Figure 17 is a sectional view a device part at the insulation stage,
`illustrating a modification
`in
`the
`insulation of
`the conductive barrier
`interconnections that is also in accordance with the present invention.
`
`It should be noted that all the Figures are diagrammatic. Relative
`
`dimensions and proportions of parts of these Figures have been shown
`
`20
`
`exaggerated or reduced in size, for the sake of clarity and convenience in the
`
`The same reference signs are generally used to refer to
`drawings.
`corresponding or similar features in modified and different embodiments.
`
`Embodiments of Figures 1 to 4
`
`25
`
`The active-matrix electroluminescent display device of each of the
`
`Figures 1 to 4 embodiments comprises an array of pixels 200 on a circuit
`
`substrate 100 with matrix addressing circuitry. Physical barriers 21 O are
`present between at least some of the neighbouring pixels in at least one
`direction of the array. At least some of these barriers 21 Oare constructed with
`
`30
`
`conductive barrier material 240 that is used as an
`
`interconnection
`
`in
`
`accordance with the present invention. Apart from this special construction
`and use of the barriers 21 O in accordance with the present invention, the
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`display may be constructed using known device technologies and circuit
`technologies, for example as in the background references cited hereinbefore.
`The matrix addressing circuitry comprises transverse sets of addressing
`(row) and signal (column) lines 150 and 160, respectively, as illustrated in
`Figure 1. An addressing element T2 (typically a thin-film transistor, hereafter
`termed "TFT") is incorporated at each interception of these lines 150 and 160.
`It should be understood that Figure 1 depicts, by way of example, one specific
`pixel circuit configuration. Other pixel circuit configurations are known for
`It should readily be
`active matrix electroluminescent display devices.
`understood that the present invention may be applied to the pixel barriers of
`
`such a device regardless of the specific pixel circuit configuration of the device.
`Each pixel 200 comprises a current-driven electroluminescent element
`25 (21,22,23), typically a light-emitting diode (LED) of organic semiconductor
`material. The LED 25 is connected in series with a drive element T1 (typically
`a TFT) between two voltage supply lines 140 and 230 of the array. These two
`supply lines are typically a power supply line 140 (with voltage Vdd) and a
`ground line 230 (also termed "return line"). Light emission from the LED 25 is
`controlled by the current flow through the LED 25, as altered by its respective
`drive TFT T1.
`Each row of pixels is addressed in turn in a frame period by means of a
`
`selection signal that is applied to the relevant row conductor 150 (and hence to
`the gate of the addressing TFTs T2 of the pixels of that row). This signal turns
`on the addressing TFT T2, so loading the pixels of that row with respective
`data signals from the column conductors 160. These data signals are applied
`to the gate of the individual drive TFT T1 of the respective pixel.
`In order to
`hold the resulting conductive state of the drive TFT T1 , this data signal is
`maintained on its gate 5 by a holding capacitor Ch that is coupled between this
`gate 5 and the drive line 140,240. Thus, the drive current through the LED 25
`of each pixel 200 is controlled by the driving TFT T1 based on a drive signal
`applied during the preceding address period and stored as a voltage on the
`
`associated capacitor Ch. In the specific exampl~ of Figure 1, T1 is shown as a
`P-channel TFT, whereas T2 is shown as an N-channel TFT.
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`5
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`This circuitry can be constructed with known thin-film technology. The
`substrate 100 may have an insulating glass base 10 on which an insulating
`surface-buffer layer 11, for example, of silicon dioxide is deposited. The
`thin-film circuitry is built up on the layer 11 in known manner.
`Figures 2 and 3 show TFT examples Tm and Tg, each comprising: an
`active semiconductor layer 1 (typically of polysilicon); a gate dielectric layer 2
`(typically of silicon dioxide); a gate electrode 5 (typically of aluminium or
`polysilicon); and metal electrodes 3 and 4 (typically of aluminium) which
`contact doped source and drain regions of the semiconductor layer 1 through
`10 windows (vias) in the over-lying insulating layer(s) 2 and 8. Extensions of the
`
`electrodes 3, 4 and 5 may form, for example, interconnections between the
`elements T1, T2, Ch and LED 25, and/or at least part of the conductor lines
`140, 150 and 160, depending on the circuit function provided by the particular
`TFT (for example, the drive element T1 or the addressing element T2 or
`another TFT of the circuit substrate). The holding capacitor Ch may be formed
`similarly, in known manner, as a thin-film structure inside the circuit substrate
`
`100.
`
`The LED 25 typically comprises a light-emitting organic semiconductor
`In a
`material 22 between a lower electrode 21 and an upper electrode 23.
`preferred particular embodiment, semiconducting conjugated polymers may be
`
`used for the electroluminescent material 22. For a LED that emits its light 250
`through the substrate 100, the lower electrode 21 may be an anode of indium
`tin oxide (ITO), and the upper electrode 23 may be a cathode comprising, for
`Figures 2 and 3 illustrate a LED
`example, calcium and aluminium.
`construction in which the lower electrode 21 is formed as a thin film in the
`circuit substrate 100. The subsequently-deposited organic semiconductor
`material 22 contacts this thin-film electrode layer 21 at a window 12a in a
`planar insulating layer 12 (for example of silicon nitride) that extends over the
`thin-film structure of the substrate 100.
`As in known devices, the devices of Figures 1 to 4 in accordance with
`
`the present invention include physical barriers 210, between at least some of
`the neighbouring pixels in at least one direction of the array. These barriers
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`21 O may also be termed "walls", "partitions", "banks", "ribs", "separators", or
`
`"dams", for example. Depending on the particular device embodiment and its
`
`manufacture, they may be used in known manner, for example:
`
`•
`
`to separate and prevent overflow of a polymer solution between the
`
`5
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`respective areas of the individual pixels 200 and/or columns of pixels
`
`200, during the provision of semiconducting polymer layers 22;
`
`•
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`to provide a self-patterning ability on the substrate surface in the
`
`definition of the semiconducting polymer or other electroluminescent
`
`layers 22 for the individual pixels 200 and/or for columns of pixels
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`200 (and possibly even a self-separation of individual electrodes for
`
`the pixels, for example an individual bottom layer of the upper
`
`electrodes 23);
`
`•
`
`to act as a spacer for a mask over the substrate surface during the
`
`deposition of at least an organic semiconductor material 22 and/or
`
`15
`
`electrode material;
`
`•
`
`to form opaque barriers 21 O for a well-defined optical separation of
`
`the pixels 200 in the array, when light 250 is emitted through the top
`
`(instead of, or as well as, the bottom substrate 100).
`
`Whatever their specific use in these known ways, at least some
`
`20
`
`insulated portions of the physical barriers 21 O in embodiments of the present
`
`invention are constructed and used in a special manner. Thus, the pixel
`
`barriers 21 O of Figures 2 to 4 comprise metal 240 (or other electrically(cid:173)
`
`conductive material 240) that is insulated from the LEDs 25 and that provides
`
`an interconnection between a first circuit element of the circuit substrate 100
`
`25
`
`and a second circuit element of the device. These circuit elements are
`
`connected at un-insulated bottom and top connection areas 240b, 240t of the
`
`conductive barrier material 240.
`The first and. second circuit elements may take a variety of forms,
`
`depending on the particular improvement or enhancement or adaptation being
`
`30 made. Typically, the first circuit element of the circuit substrate 100 may be
`
`one or more thin-film elements of the group comprising: a conductor layer
`
`and/or an electrode connection 4, 5, 6; a supply line 140; an addressing line
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`150; a signal line 160; a thin-film transistor T1, T2, Tm, Tg; a thin-film capacitor
`
`Ch. The second circuit element may be another such thin-film element in the
`
`circuit substrate 100 and/or, for example, an electrode connection of the LED
`
`25 of a respective pixel or an added component such as a sensor.
`
`5
`
`Figures 2 to 4 show the un-insulated top connection area 240t, but
`
`without any specific second circuit element (upper circuit element 400)
`
`connected thereto. Particular examples of a second circuit element are
`
`described below with reference to Figures 5 to 8. However, it should readily
`
`be understood that the present invention can be applied to the interconnection
`
`10
`
`of a wide variety of upper circuit elements 400 to circuitry in the circuit
`
`substrate 100 by means of such pixel barriers 21 O in accordance with the
`
`invention.
`
`In the embodiment of Figure 2, the first circuit element is an extension
`
`of the source and/or drain electrode of TFT Tm. It may form a signal (column)
`
`15
`
`line 160, for example, of the substrate circuitry when Tm is T2, or a drive line
`
`140 when Tm is T1.
`
`In the embodiment of Figure 3, the first circuit element is
`
`an extension of the gate electrode 5 of TFT Tg.
`
`It may form an addressing
`
`(row) line 150, for example, of the substrate circuitry when Tg is T2.
`
`Figures 2 and 3 show the bottom connection of the conductive barrier
`
`20 material 240 to the first circuit element 4,5 at connection windows 12b in the
`
`intermediate insulating layer 12. However, it should be understood that these
`
`windows 12b may often not be in the same plane as the TFT Tm, Tg.
`
`In
`
`particular, there is generally insufficient space between the source and drain
`
`electrodes 3 and 4 of TFT Tg to accommodate a window 12b. Thus, the
`
`25 window 12b is depicted in broken outline in Figure 3 to indicate its location
`
`outside the plane of the drawing paper.
`
`The pixel barriers 21 O in the embodiments of Figures 2 to 4 are
`
`predominantly of electrically-conductive material 240, 240x, preferably metal
`
`for very low resistivity (for example aluminium or copper or nickel or silver).
`
`30
`
`The barriers 21 O of Figures 2 and 3 comprise a bulk or core of the conductive
`
`material that provides the interconnection 240 and that has an insulating
`
`coating 40 on its sides and on its top (except where the top connection area
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`240t is exposed). The barrier 21 O of Figure 4 comprises a bulk or core of
`conductive material 240x that has an insulating coating 40x on its sides and on
`its top. The conductive material that provides the interconnection 240 in
`Figure 4 is a metal coating that extends on the insulating coating 40x. An
`insulating coating 40 extends on the sides and on the top of the metal coating
`240, except where the top connection area 240t is exposed. This structure of
`Figure 4 is more versatile than that of Figures 2 and 3.
`It permits the metal
`core 240x to be used for another purpose, for example, to back-up or even
`replace the lines 140, 150 or 160, so reducing their line resistance. The
`interconnection metal coating 240 may even be localised to specific locations
`
`along the barrier 21 O where these interconnections are required, for example
`at individual pixels or sub-pixels.
`
`Embodiments of Figures 5 to 7 with Sensor Arrays
`In each of the embodiments of Figures 5 to 7, an array of sensors 400s
`is integrated together with the array of pixels 200. The sensors 400s provide
`the second circuit elements 400 that are connected by the conductive barrier
`material 240 to the first circuit element of the circuit substrate 100. A variety
`of sensor arrays may be integrated with the display in accordance with the
`invention. Thus, the sensing array may have, for example, a short-circuit
`touch input, or a pressure input, or a capacitance input, or a light-pen input.
`For individual interconnections from a two-dimensional sensor array, the
`conductive barrier material 240 is generally split up into respective insulated
`lengths in the barriers 210, corresponding to the individual sensors 400s.
`In this integrated sensor situation, the first circuit element may be, for
`example, a source/drain 4 or gate 5 of a TFT in the substrate 100. Preferably,
`the first circuit element is part of matrix addressing circuitry for both the array
`of pixels 200 and the array of sensors 200s. Thus, the first circuit element may
`be the source/drain line 4, 160 of TFT T2 for pixel addressing.
`In each of the embodiments of Figures 5 to 7, the sensing capability is
`
`provided at the front of the display, through which the light 250 is emitted. The·
`sensor array is supported on top of the barriers 21 O and over the pixel array.
`
`5
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`10
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`15
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`20
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`25
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`30
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`11
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`An insulating planarising layer 412 is present over the pixel array, with a
`thickness that extends to the top of the barriers 21 O to support the sensor
`
`array over the pixel array. Although Figures 5 to 8 illustrate an interconnecting
`
`metal-core structure as in Figures 2 and 3, modifications are possible using,
`for example, an interconnecting metal-coating structure as in Figure 4.
`
`5
`
`The Figure 5 embodiment illustrates a pressure sensor structure
`
`comprising a compressible layer 422 of dielectric or highly resistive material.
`
`This compressible layer is stacked between a transparent upper electrode
`layer 423 of, for example, ITO and the underlying conductive barrier material
`
`10
`
`240 and insulating planarising layer 412. The upper electrode layer 423 is
`
`coated with a protective layer 440. When pressure 500 is applied to this stack,
`
`the spacing between the electrode 1ayer 423 and the conductive barrier
`
`material changes causing either a measurable change in capacitance across
`the dielectric or, a reduction in resistance across the highly resistive material.
`
`15
`
`This is a most advantageous embodiment, in that the electrode layer 423 also
`provides ESD protection for the circuit inputs.
`
`Figure 6 illustrates a capacitive sensor, for example a finger-print
`sensor. An array of electrode pads 421 of ITO or metal are connected at the
`
`top of the corresponding array of conductive barrier material 240 to form one
`
`20
`
`plate of a respective capacitor having thereon a capacitor dielectric layer 430.
`
`The other plate of the capacitor is formed by a finger or other object to be
`sensed, when placed on the dielectric layer 430.
`
`Figure 7 illustrates a direct input sensor having electrode pads 424 of
`
`ITO that are connected at the top of the corresponding array of conductive
`
`25
`
`barrier material 240. The direct input may be a current or voltage input from,
`for example, a wired pen that touches the pads 424. Alternatively, the direct
`input may simply be a short-circuit by an (un-wired) conductive pen between
`neighbouring pads 424, for example between a pad 424 connected to a row
`
`conductor 150 and a pad 424 connected to a column conductor 160. Current
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`30
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`flow resulting from such a short-circuit can be measured at the periphery of the
`
`display to determine which pixel was shorted.
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`Embodiment of Figure 8 with Pixel or Sub-Pixel Interconnect
`
`The second circuit element in the embodiment of Figure 8 is an upper
`
`electrode 23 of the LED 25, which is connected by the conductive barrier
`
`material 240 to a thin-film element of the circuit substrate 100. Such an
`
`5
`
`interconnection permits the integration of circuitry to both electrodes 21 and 23
`
`of the given LED 25.
`
`However, in the particular embodiment depicted in Figure 8, the bottom
`connection of the conductive barrier material 240 is to a thin-film element that
`
`forms the lower electrode of a neighbouring LED 25. Such a construction can
`
`10
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`be adopted for a display each pixel of which comprises, for example,
`
`side-by-side sub-pixels with the barriers 21 O there-between.
`conductive barrier material 240 connects the upper electrode 23 of one
`
`In this case, the
`
`sub-pixel 200b to the lower electrode 21 of an adjacent sub-pixel 200a.
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`15
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`Layout Embodiments of Figures 9 and 1 O and of Figure 11
`
`A wide variety of layout configurations are possible for the interconnect
`
`in devices
`in accordance with
`the
`invention.
`barrier material 240
`Advantageously, the interconnect barrier material 240 may be combined in a
`
`composite layout with other sections of barrier 21 Ox between the pixels.
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`20
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`Figures 9 and 1 O illustrate one composite layout in which the conductive
`
`barrier material 240x of the additional barrier sections 21 Ox may back up or
`
`even replace the drive supply lines 140 of the substrate 100. The matrix
`In this particular
`thin-film circuit area is designated as 120 in Figure 9.
`
`example, the insulated lengths of the interconnect barrier material 240 extend
`
`25
`
`parallel to the additional barrier lines 21 Ox, 140.
`Figure 11 illustrates another composite layout in which the additional
`
`barrier sections 21 Ox (240x, 40x) are transverse to the interconnect barrier
`material 240.
`
`In this case, the conductive barrier material 240x of the
`
`additional barrier sections 21 Ox may back up or even replace the lines 140 or
`
`30
`
`150 or 160 of the substrate 100. Alternatively, the conductive barrier material
`
`240x of the additional barrier sections 21 Ox may form transverse interconnects
`for a direct-input sensor array such as that of Figure 7.
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`Modified Barrier Embodiment of Figure 12
`
`In the embodiments of Figures 2 to 8 and Figure 10, barriers 21 O and
`21 Ox are shown as being predominantly of conductive material 240 and 240x.
`Figure 12 shows a modified embodiment wherein
`the barrier 21 O is
`predominantly of insulating material 244. In this case, vias 244b are etched or
`milled through the insulating material 244 to the circuit element 4, 5 in the
`circuit substrate 100. A metal coating 240 provides the conductive barrier
`material that extends on top of the insulating barrier 21 O and in the vias 244b
`therethrough.
`
`The metal coating 240 of the barrier 21 O may be formed