(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0165003 A1
`Shirasaki
`(43) Pub. Date:
`Aug. 26, 2004
`
`US 2004O165003A1
`
`(54) DISPLAY APPARATUS AND DRIVING
`METHOD FOR DISPLAY APPARATUS
`
`(75) Inventor: Tomoyuki Shirasaki, Tokyo (JP)
`Correspondence Address:
`ERISHAU, HOLTZ, GOODMAN & CHICK,
`767 THIRDAVENUE
`25TH FLOOR
`NEW YORK, NY 10017-2023 (US)
`
`: C Computer Co., Ltd., Tokvo (JP
`73) AS
`(73)
`Signee: Uasio uomputer u0.,
`, Tokyo (JP)
`(21) Appl. No.:
`10/782,071
`
`(22) Filed:
`(30)
`
`Feb. 18, 2004
`Foreign Application Priority Data
`
`Feb. 25, 2003 (JP)...................................... 2003-0471.90
`
`Publication Classification
`(51) Int. Cl." ....................................................... G09G 5/10
`(52) U.S. Cl. .............................................................. 345/690
`(57)
`ABSTRACT
`A display apparatus includes light-emitting elements each of
`with is arranged R. re SR and exit light at
`luminance corresponding to a driving current. IO a SIgna
`line through the pixel circuit, is Supplied a gray level
`designation current having a current value larger than that of
`the driving current during a Selection period to Store a
`luminance gray level in the pixel circuit. A first voltage is
`outputted to the pixel circuit So that the gray level designa
`tion current is Supplied to the Signal line through the pixel
`circuit during the Selection period, and a Second Voltage is
`outputted to the pixel circuit during a nonselection period,
`thereby modulating a current output from the pixel circuit on
`the basis of the luminance gray level Stored in the pixel
`circuit to Supply the driving current to the pixel circuit.
`
`EXTERNAL CIRCUIT
`
`3
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`DATA DRIVER
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`
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`Patent Application Publication Aug. 26, 2004 Sheet 1 of 7
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`US 2004/0165003 A1
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`Patent Application Publication Aug. 26, 2004 Sheet 2 of 7
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`US 2004/0165003 A1
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`Patent Application Publication Aug. 26, 2004 Sheet 3 of 7
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`US 2004/0165003 A1
`
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`Patent Application Publication Aug. 26, 2004 Sheet 4 of 7
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`US 2004/0165003 A1
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`Patent Application Publication Aug. 26, 2004 Sheet 5 of 7
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`US 2004/0165003 A1
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`
`
`POTENTIAL OF
`SELECTION
`SCANNING LINE X1
`OF FIRST ROW
`POTENTIAL OF
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`
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`Patent Application Publication Aug. 26, 2004 Sheet 6 of 7
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`US 2004/0165003 A1
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`Patent Application Publication Aug. 26, 2004 Sheet 7 of 7
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`US 2004/0165003 A1
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`FIG.7
`(RELATED ART)
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`US 2004/O165003 A1
`
`Aug. 26, 2004
`
`DISPLAY APPARATUS AND DRIVING METHOD
`FOR DISPLAY APPARATUS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`0001. This application is based upon and claims the
`benefit of priority from prior Japanese Patent Application
`No. 2003-047190, filed Feb. 25, 2003, the entire contents of
`which are incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`0002) 1. Field of the Invention
`0003. The present invention relates to a display apparatus
`having a display panel on which a light-emitting element is
`formed for each pixel and a driving method for the display
`apparatuS.
`0004 2. Description of the Related Art
`0005 Examples of conventionally known light-emitting
`element type display apparatuses, in which light-emitting
`elements are arrayed in a matrix and caused to emit light to
`execute display, are an organic EL (ElectroLuminescent)
`device, inorganic EL and LED (Light Emitting Diode).
`Especially, active matrix driving light-emitting element type
`display apparatuses have advantages Such as high lumi
`nance, high contrast, high accuracy, low power consump
`tion, low profile, and wide View angle. Especially, organic
`EL elements have received a great deal of attention.
`0006.
`In Such a display apparatus, a plurality of Scanning
`lines are formed on a transparent Substrate. A plurality of
`Signal lines are also formed on the Substrate to run perpen
`dicularly to the Scanning lines.
`0007. A plurality of transistors are formed in each region
`Surrounded by the Scanning lines and Signal lines. In addi
`tion, one light-emitting element is formed in each region.
`0008. In recent years, the light emission efficiency and
`color characteristic of an organic EL element have greatly
`increased to the degree that the light emission luminance is
`almost proportional to the current density. For this reason, an
`organic EL display apparatus having a high gray level can be
`designed on the basis of a predetermined Standard. Accord
`ing to this Standard, a current value necessary for an organic
`EL element to emit light is about Several ten na (nanoam
`pere) to Several uA (microampere) per gray level. For an
`organic EL element, the driving frequency must be increased
`as the number of pixels increases. However, when the gray
`level current that flows in the organic EL element is Such a
`Small current, the time constant increases due to the parasitic
`capacitance in the display apparatuS panel. Since it is
`time-consuming to Supply a current having a value corre
`sponding to a desired luminance to the organic EL element,
`no high-Speed operation can be performed. Especially, in
`displaying a moving image, the image quality greatly
`degrades. Recently, an organic EL display apparatus that
`controls the gray level by a current mirror has been proposed
`(e.g., Jpn. Pat. Appln. KOKAI Publication No. 2001
`147659).
`0009. The organic EL display apparatus described in this
`reference comprises an equivalent circuit 102 with current
`mirror shown in FIG. 7 as an equivalent circuit of a pixel.
`A Signal current flowing in a signal line 704 is Set in
`
`accordance with the size ratio of transistors 705 and 706 that
`constitute the current mirror, and is therefore Set to be larger
`than a current value necessary for the organic EL element to
`emit light.
`0010 More specifically, in the equivalent circuit 102 with
`current mirror, an organic EL element 701, transistors 702
`and 707, the transistors 705 and 706 that constitute the
`current mirror, and a capacitor 709 are arranged for each
`pixel. The equivalent circuit 102 with current mirror com
`prises a first Scanning driver (not shown) that sequentially
`selects a first scanning line 703 of each row and a second
`Scanning driver (not shown) that sequentially selects a
`Second Scanning line 708 of each row. First, a Scanning
`Signal that changes from low level to high level is input to
`the second scanning line 708 by the second scanning driver
`to enable a write in the n-channel transistor 707. Subse
`quently, a Scanning Signal that changes from high level to
`low level is input to the first scanning line 703 by the first
`Scanning driver to enable a write in the p-channel transistor
`702. A current flows to the transistor 705 and organic EL
`element 701 in accordance with the current flowing to the
`signal line 704.
`0011. The equivalent circuit 102 with current mirror
`described in the above reference has the following problems.
`0012 One transistor 707 is an n-channel transistor, and
`the other transistor 702 is a p-channel transistor. For this
`reason, the manufacturing process becomes complex as
`compared to the manufacture of Single-channel transistors.
`In addition, Since no p-channel material that effectively
`operates with currently used amorphous Silicon has been
`established yet, a polysilicon must be Selected.
`0013 Furthermore, in the equivalent circuit 102 with
`current mirror, five transistors are formed for each pixel. For
`this reason, the power consumption and manufacturing cost
`may increase, and the yield may decrease.
`0014. The equivalent circuit 102 with current mirror
`requires two Scanning drivers. For this reason, the manu
`facturing cost of the equivalent circuit 102 with current
`mirror is high, and the Scanning driver mounting area is
`large.
`
`BRIEF SUMMARY OF THE INVENTION
`0015. It is an object of the present invention to provide a
`display apparatus that realizes low power consumption and
`manufacturing cost and high yield, and a driving method for
`the display apparatus.
`0016. In order to solve the above problems, the present
`invention has the following characteristic features. In the
`following description of means, components corresponding
`to the embodiment are exemplified in parentheses. Symbols
`and the like are reference Symbols and numerals in the
`drawing (to be described later).
`0017. A display apparatus according to the present inven
`tion comprises:
`0018 a plurality of pixel circuits (e.g., pixel circuits
`D, to Dn);
`0019 a plurality of light-emitting elements (e.g.,
`organic EL elements E to E.) each of which is
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`US 2004/O165003 A1
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`Aug. 26, 2004
`
`arranged for a corresponding one of the pixel circuits
`and emits light at a luminance corresponding to a
`driving current;
`0020 luminance gray level designation means (e.g.,
`data driver 3) for Supplying, to a signal line through
`the pixel circuit, a gray level designation current
`having a current value larger than that of the driving
`current during a Selection period to Store aluminance
`gray level of the light-emitting element in the pixel
`circuit; and
`0021 current value Switching voltage output means
`(e.g., power Supply Scanning driver 6) for outputting
`a first Voltage (e.g., potential Vict) to the pixel
`circuit to cause the luminance gray level designation
`means to Supply the gray level designation current to
`the Signal line through the pixel circuit during the
`Selection period and outputting a Second Voltage
`(e.g., potential VLow) having a potential different
`from that of the first voltage to the pixel circuit
`during a nonselection period to modulate a current
`output from the pixel circuit on the basis of the
`luminance gray level Stored in the pixel circuit to
`Supply the driving current to the pixel circuit.
`0022. A display apparatus driving method according to
`the present invention is a driving method for a display
`apparatus which comprises a plurality of pixel circuits (e.g.,
`pixel circuits D to D.) and causes light-emitting ele
`ments (e.g., organic EL elements E, to E.) each of which
`is arranged for a corresponding one of the pixel circuits to
`emit light in accordance with a predetermined driving cur
`rent to execute display, comprising Steps of:
`0023 outputting a first voltage (e.g., potential
`Vict) to the pixel circuit to Supply a gray level
`designation current having a current value larger
`than that of the driving current to a signal line
`through the pixel circuit during a Selection period
`and Store, in the pixel circuit, a luminance gray level
`of the light-emitting element corresponding to the
`current value of the gray level designation current;
`and
`0024 outputting a second Voltage (e.g., potential
`Vow) having a potential different from that of the
`first voltage to the pixel circuit during a nonselection
`period to modulate the driving current output from
`the pixel circuit on the basis of the luminance gray
`level Stored in the pixel circuit.
`0025 A driving current having a current value (e.g., low
`level of several ten nA to several uA) sufficient for a
`light-emitting element to emit light can be Supplied to the
`light-emitting element without complicating the arrange
`ment of the display apparatus. Hence, a display apparatus
`that realizes low power consumption and manufacturing cost
`and high yield, and a driving method for the display appa
`ratus can be provided.
`0026. Additional objects and advantages of the invention
`will be set forth in the description which follows, and in part
`will be obvious from the description, or may be learned by
`practice of the invention. The objects and advantages of the
`invention may be realized and obtained by means of the
`instrumentalities and combinations particularly pointed out
`hereinafter.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`0027. The accompanying drawings, which are incorpo
`rated in and constitute a part of the Specification, illustrate
`embodiments of the invention, and together with the general
`description given above and the detailed description of the
`embodiments given below, Serve to explain the principles of
`the invention.
`0028 FIG. 1 is a block diagram showing the internal
`arrangement of an organic EL display apparatus to which the
`present invention is applied;
`0029 FIG. 2 is a plan view schematically showing one
`pixel of the organic EL display apparatus shown in FIG. 1;
`0030 FIG. 3 is a circuit diagram showing an equivalent
`circuit corresponding to pixels of the organic EL display
`apparatus shown in FIG. 1;
`0031
`FIG. 4 is a graph showing the current vs. voltage
`characteristic of an n-channel transistor;
`0032 FIG. 5 is a timing chart of signal levels in the
`organic EL display apparatus shown in FIG. 1;
`0033 FIG. 6A is a circuit diagram showing an equivalent
`circuit corresponding to one pixel of another organic EL
`display apparatus,
`0034 FIG. 6B is a circuit diagram showing an equivalent
`circuit having four Switching elements in one pixel; and
`0035 FIG. 7 is a view showing an equivalent circuit with
`current mirror corresponding to one pixel of an organic EL
`display apparatus related to the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`0036) An embodiment to which the present invention is
`applied will be described below with reference to the
`accompanying drawing.
`0037 FIG. 1 shows the internal arrangement of an
`organic EL display apparatus 1 to which the present inven
`tion is applied. As shown in FIG. 1, the organic EL display
`apparatus 1 comprises, as basic components, an organic EL
`display panel 2, a data driver 3 which forcibly Supplies a
`gray level designation current having a current value corre
`sponding to a gray level in accordance with a control Signal
`group D including a clock signal CK1 and luminance gray
`level Signal SC which are input from an external circuit 11,
`a Selection Scanning driver 5 which receives a control Signal
`group G including a clock signal CK2 from the external
`circuit 11, and a power Supply Scanning driver 6.
`0038. The organic EL display panel 2 is constituted by
`forming, on a transparent Substrate 8, a display Section 4 that
`actually displays an image. The Selection Scanning driver 5,
`data driver 3, and power Supply Scanning driver 6 are
`arranged around the display Section 4 on the transparent
`Substrate 8.
`0039 The organic EL display panel 2 is designed on the
`basis of a Standard corresponding to the characteristic of
`organic EL elements E to E, in the display section 4. For
`example, assume that in the organic EL elements E to E.
`of the full-color organic EL display panel 2, the light
`emission area of one pixel is set to 0.001 to 0.01 mm, the
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`average value of maximum luminances of each of R, G, and
`B is 400 cd/cm’, and the current density at this time is 10 to
`150 A/cm. In this case, the displacement current per gray
`level is a Small current of Several nA to Several uA.
`0040. In the display section 4, (mxn) pixels P, to P,
`are formed in a matrix on the transparent substrate 8. More
`specifically, m pixels P, are arrayed in the vertical direction
`(column direction), and n pixels P, are arrayed in the
`horizontal direction (row direction). In this case, m and n are
`natural numbers, i is a natural number (1sism), and j is a
`natural number (1sjsn). A pixel that is ith from the upper
`end (i.e., ith row) and jth from the left end (i.e., jth column)
`is expressed as a pixel P.
`0041. In the display section 4, m selection scanning lines
`X to X, m power Supply Scanning lines Z to Z, and in
`Signal lines Y to Y are formed on the transparent Substrate
`8 to be insulated from each other.
`0042. The selection scanning lines X to X run in the
`horizontal direction parallel to each other. The power Supply
`Scanning lines Z to Z, and Selection Scanning lines X to
`X, alternate.
`0043. The signal lines Y to Y run in the vertical direc
`tion parallel to each other and perpendicular to the Selection
`Scanning lines X to X. The Selection Scanning lines X to
`X, power Supply Scanning lines Z to Z, and Signal lines
`Y to Y are insulated from each other by an interlayer
`dielectric film (not shown).
`0044) The data driver 3, selection scanning driver 5, and
`power Supply Scanning driver 6 may be formed either
`directly on the transparent Substrate 8 or on a film Substrate
`(not shown) arranged at the peripheral portion of the trans
`parent Substrate 8. In this embodiment, the Selection Scan
`ning driver 5 and power Supply Scanning driver 6 are
`arranged outside two opposing Sides of the display Section 4
`on the transparent Substrate 8. The Selection Scanning lines
`X to X are connected to the output terminals of the
`Selection Scanning driver 5. The power Supply Scanning lines
`Z to Z are connected to the output terminals of the power
`Supply Scanning driver 6.
`0045 N pixels P, to P, arrayed in the horizontal direc
`tion are connected to the Selection Scanning line X
`(1sism) and power Supply scanning line Z, M pixels P,
`to Parrayed in the vertical direction are connected to the
`signal line Y (1sjsn). The pixel P, is arranged at the
`interSection between the Selection Scanning line X and the
`signal line Y:
`0046) The pixel P. will be described next with reference
`to FIGS. 2 and 3. FIG. 2 is a plan view schematically
`showing the pixel P. FIG. 3 is a circuit diagram showing
`an equivalent circuit corresponding to pixels Pi, P.I.,
`P.1, and P1. The gate insulating films of transistors 21,
`22, and 23 (to be described later) and the upper electrode
`(corresponding to a cathode electrode in this embodiment)
`of each organic EL element are not illustrated.
`0047) The pixel P. is formed from an organic EL element
`E, which emits light at a luminance corresponding to the
`level of the driving current and a pixel circuit D, arranged
`around the organic EL element E.
`0048. The organic EL element E has a multilayered
`Structure in which an anode 51, organic EL layer 52, and
`cathode (not shown) are sequentially formed on the trans
`parent substrate 8.
`
`0049) The anode 51 is patterned for each of the pixels P.
`to P, and formed in each of regions Surrounded by the
`Signal lines Y to Y and Selection Scanning lines X to X.
`At each intersection between the signal lines Y to Y and
`the Selection Scanning lines X to X, a Semiconductor layer
`28 obtained by patterning the same layerS as patterned
`Semiconductor layerS 21c, 22c, and 23c of the transistorS 21,
`22, and 23, and their gate insulating films are Stacked.
`Similarly, at each intersection between the Signal lines Y to
`Y and the power Supply Scanning lines Z to Z, a Semi
`conductor layer 29 obtained by patterning the same layerS as
`the patterned Semiconductor layerS 21c, 22c, and 23c of the
`transistorS 21, 22, and 23, and their gate insulating films are
`Stacked.
`0050. The anode 51 is conductive and transparent to
`visible light. The anode 51 is preferably made of a material
`having a relatively high work function and efficiently injects
`holes into the organic EL layer 52. The anode 51 is mainly
`made of, e.g., indium tin oxide (ITO), indium Zinc oxide
`(IZO), indium oxide (In-O), tin oxide (SnO2), or Zinc oxide
`(ZnO).
`0051. The organic EL layer 52 made of an organic
`compound is formed on the anode 51. The organic EL layer
`52 is also patterned for each of the pixels P, to P, The
`organic EL layer 52 may have, e.g., a three-layered Structure
`including a hole transport layer, a light-emitting layer of
`narrow Sense, and an electron transport layer Sequentially
`from the anode 51. Alternately, the organic EL layer 52 may
`have a two-layered structure including a hole transport layer
`and a light-emitting layer of narrow Sense Sequentially from
`the anode 51, or a single-layered Structure including only a
`light-emitting layer of narrow Sense. Alternatively, the
`organic EL layer 52 may have a multilayered Structure in
`which an electron or hole injection layer is inserted between
`appropriate layers in one of the above layer Structures. The
`organic EL layer 52 may have any other layer Structure.
`0052 The organic EL layer 52 is a light-emitting layer of
`broad Sense, which has a function of injecting holes and
`electrons, a function of transporting holes and electrons, and
`a function of generating excitons by recombination of holes
`and electrons and emitting red, green, or blue light. More
`specifically, when the pixel P. is used for red, the organic
`EL layer 52 of the pixel P. emits red light. When the pixel
`P, is green, the organic EL layer 52 of the pixel P. emits
`green light. When the pixel P. is blue, the organic EL layer
`52 of the pixel Pii emits blue light.
`0053. The organic EL layer 52 preferably contains an
`electronically neutral organic compound. Accordingly, holes
`and electrons are injected and transported by the organic EL
`layer 52 in good balance. An electron transport Substance
`may appropriately be mixed into the light-emitting layer of
`narrow Sense. A hole transport Substance may appropriately
`be mixed into the light-emitting layer of narrow Sense. Both
`an electron transport Substance and a hole transport Sub
`stance may appropriately be mixed into the light-emitting
`layer of narrow Sense.
`0054. A cathode is formed on the organic EL layer 52.
`The cathode may be a common electrode Serving as a
`conductive layer connected to all the pixels P, to P,
`Alternately, the cathode may be patterned for each of the
`pixels P, to P. In either case, the cathode is electrically
`insulated from the Selection Scanning lines X to X, Signal
`lines Y to Y, and power Supply Scanning lines Z to Z.
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`0.055 The cathode is made of a material having a rela
`tively low work function. The cathode is made of, e.g.,
`indium, magnesium, calcium, lithium, or barium, or an alloy
`or mixture containing at least one of them. The cathode may
`have a multilayered Structure in which layers of various
`materials described above are Stacked or a multilayered
`Structure in which a metal layer is formed in addition to the
`layers of various materials described above. More specifi
`cally, the cathode may have a multilayered Structure in
`which a metal layer Such as an aluminum or chromium layer
`having a high work function and low resistance is formed on
`the layers of various materials described above. The cathode
`preferably has a light Shielding effect and high reflectivity to
`Visible light and functions as a mirror Surface.
`0056. At least one of the anode 51 and cathode may be
`transparent. More preferably, one electrode is transparent,
`and the other electrode has a high reflectivity.
`0057. As described above, in the organic EL element E,
`having the multilayered Structure, when a forward bias
`voltage (the anode 51 has a higher potential than the
`cathode) is applied between the anode 51 and the cathode,
`holes are injected from the anode 51 to the organic EL layer
`52, and electrons are injected from the cathode to the organic
`EL layer 52.
`0.058. The holes and electrons are transported in the
`organic EL layer 52 and recombine in it. Accordingly,
`excitons are generated to excite the phosphor in the organic
`EL layer 52 so that light is emitted in the organic EL layer
`52.
`0059. The light emission luminance of the organic EL
`element E depends on the level of the driving current
`flowing to it. AS the current level increases, the light
`emission luminance also increases. That is, when the level of
`the driving current flowing to the organic EL element E is
`determined, its luminance is uniquely determined.
`0060) The pixel circuit D, drives the organic EL element
`E on the basis of signals output from the data driver 3,
`Selection Scanning driver 5, and power Supply Scanning
`driver 6. Each pixel circuit D, comprises the transistors 21,
`22, and 23 and a capacitor 24.
`0061 Each of the transistors 21, 22, and 23 is an MOS
`FET having a gate electrode, drain electrode, Source elec
`trode, Semiconductor layer, impurity Semiconductor layer,
`and gate insulating film and, more particularly, a transistor
`that uses amorphous Silicon for the Semiconductor layer
`(channel region). The transistor may use polysilicon for the
`Semiconductor layer. The transistorS 21, 22, and 23 may
`have an inverted Staggered Structure or a coplanar Structure.
`0062) The gate electrode, drain electrode, source elec
`trode, Semiconductor layer, impurity Semiconductor layer,
`and gate insulating film of the transistorS 21, 22, and 23 have
`the Same compositions. The transistorS 21, 22, and 23 are
`simultaneously formed in the same step but have different
`shapes, sizes, dimensions, channel widths, and channel
`lengths.
`0.063. In this embodiment, the transistors 21, 22, and 23
`will be described as n-channel amorphous silicon field effect
`transistors.
`0064. The semiconductor layer 21c is arranged between
`a Source electrode 21S and a drain electrode 21d of the
`
`transistor 21 via an impurity Semiconductor layer. The
`Semiconductor layer 22c is arranged between a Source
`electrode 22s and a drain electrode 22d of the transistor 22
`via an impurity Semiconductor layer. The Semiconductor
`layer 23C is arranged between a Source electrode 23S and a
`drain electrode 23d of the transistor 23 via impurity semi
`conductor layers. One electrode of the capacitor 24 is
`connected to a gate electrode 23g of the transistor 23. The
`other electrode is connected to the Source electrode 23S of
`the transistor 23. A dielectric body is inserted between one
`electrode and the other electrode. This dielectric body may
`be the gate insulating film of the transistor 21, 22, or 23. The
`dielectric body may be the semiconductor layer 23c or
`impurity Semiconductor layer of the transistor 23. Alterna
`tively, the dielectric body may contain at least two of the
`above members.
`0065. A gate electrode 22g of each transistor 22 is
`connected to one of the Selection Scanning lines X to X.
`The drain electrode 22d is connected to one of the power
`Supply Scanning lines Z to Z, and the drain electrode 23d
`of the transistor 23. The Source electrode 22s is connected to
`the gate electrode 23g of the transistor 23 through a contact
`hole 25 formed in the gate insulating film and to one
`electrode of the capacitor 24.
`0066. The source electrode 23s of the transistor 23 is
`connected to the other electrode of the capacitor 24 and the
`drain electrode 21d of the transistor 21. The drain electrode
`23d of the transistor 23 is connected to one of the power
`Supply Scanning lines Z to Z through a contact hole 26
`formed in the gate insulating film.
`0067. A gate electrode 21g of the transistor 21 is con
`nected to the Selection Scanning line X. The Source elec
`trode 21s is connected to the signal line Yi. The Source
`electrode 23s of the transistor 23, the other electrode of the
`capacitor 24, and the drain electrode 21d of the transistor 21
`are connected to the anode 51 of the organic EL element E,
`0068. The cathode of the organic EL element E is held
`at a predetermined reference potential Vss. In this embodi
`ment, the cathode of the organic EL element E is grounded
`so that the reference potential Vss is 0 V (volt).
`0069. The current vs. voltage characteristic of an n-chan
`nel transistor (e.g., the transistor 23, though it may be the
`transistor 21 or 22) will be described here with reference to
`FIG. 4. The ordinate represents the drain-to-source current
`value, and the abscissa represents the drain-to-Source Volt
`age Value.
`0070. As shown in FIG. 4, in the transistor 23, the
`correlation between a drain-to-Source Voltage level Vs and
`a drain-to-Source current level Is is uniquely determined
`for each gate-to-Source Voltage level Vos (e.g., Vos 1 to
`Vos4).
`0.071) The gate-to-source voltage levels Vis1 to Vs."
`correspond to four different gray levels corresponding to the
`organic EL elements E to E.
`The number of gray levels
`is to limited to four and may be more or less.
`0072. In a saturation region where the drain-to-source
`Voltage level Vs is higher than a drain Saturation threshold
`Voltage level V, the drain-to-Source current level Is
`indicates a Saturation current which is uniquely determined
`by the gate-to-Source Voltage level Vs.
`
`SAMSUNG EX. 1007 - 12/17
`
`

`

`US 2004/O165003 A1
`
`Aug. 26, 2004
`
`0073. In a nonsaturation region where the drain-to-source
`Voltage level Vs is lower than the drain Saturation threshold
`Voltage level V, the drain-to-Source current level Is
`indicates a nonsaturation current which increases/decreases
`almost in proportion to the drain-to-Source Voltage level Vs
`(i.e., almost linearly) under the predetermined gate-to
`Source Voltage level Voss.
`0.074
`Hence, to increase/decrease the drain-to-source
`current level Is under the predetermined gate-to-Source
`voltage level Vs., the drain-to-Source Voltage level Vs is
`Set to a value Sufficiently Smaller than the drain Saturation
`threshold Voltage level V. More specifically, the drain
`to-Source current level Is that flows in the drain-to-Source
`path of the transistor 23 is increased. In this State, the
`gate-to-source Voltage level Vs is held at a predetermined
`level. Then, the drain-to-Source Voltage level Vs is
`uniquely decreased by a predetermined level. With this
`operation, the drain-to-Source current level Is that flows
`between the Source and the drain of the transistor 23 can
`uniquely be decreased.
`0075 AS described above, in the organic EL display
`apparatus 1, by Setting the drain-to-Source Voltage level Vs
`of the transistor 23 to a sufficiently smaller value than the
`drain Saturation threshold voltage level V, the drain-to
`Source current level Is that flows in the drain-to-Source path
`of the transistor 23 can be increased during a Selection
`period Ts (to be described later) and decreased during a
`nonselection period TNs (to be described later). Accord
`ingly, even when the parasitic capacitance of the Signal lines
`Y to Y is large, the time constant that Sets the drain-to
`Source current level Is of the transistor 23 in a steady State
`during the Selection period Ts can be made Smaller. In
`addition, the drain-to-source current level Is of Small
`current level Suitable for light emission of the organic EL
`elements E to E, can be obtained during the nonselec
`tion period TNse.
`0.076 The data driver 3, selection scanning driver 5, and
`power Supply Scanning driver 6 will be described next.
`0077. The selection scanning driver 5 is a so-called shift
`register in which m flip-flop circuits are connected in Series.
`The Selection Scanning driver 5 applies a Selection signal to
`the Selection Scanning lines X to X for a predetermined
`time at a predetermined period, as shown in FIGS. 1 and 3.
`More Specifically, on the basis of the clock Signal CK2 input
`from the external circuit 11, the Selection Scanning driver 5
`Sequentially applies an ON potential V as a Selection
`Signal of high level to the Selection Scanning lines X to X.
`in this order (especially, the Selection Scanning line X next
`to the Selection Scanning line X), thereby sequentially
`Selecting the Selec