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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG DISPLAY CO., LTD.,
`Petitioner,
`
`v.
`
`SOLAS OLED, LTD.,
`Patent Owner.
`
`Case No. IPR2020-00320
`U.S. Patent No. 7,446,338
`
`PETITIONER’S REPLY TO PATENT OWNER RESPONSE
`
`
`
`

`

`
`
`LIST OF EXHIBITS
`
`
`Description
`U.S. Patent No. 7,446,338 (the “’338 patent”)
`File History for U.S. Patent No. 7,446,338
`U.S. Patent Application Pub. No. 2002/0158835 (“Kobayashi”)
`U.S. Patent Application Pub. No. 2004/0113873 (“Shirasaki”)
`International Publication No. WO 03/079441 (“Childs”)
`European Patent Application No. EP 1331666 (“Yamazaki”)
`U.S. Patent Application Pub. No. 2004/0165003 (“Shirasaki II”)
`Japanese Patent Publication No. 2004-258172
`U.S. Patent Application Pub. No. 2003/0151637 (“Nakamura”)
`International Publication No. WO 03/079442 (“Hector”)
`International Publication No. WO 03/079449 (“Young”)
`Tsujimura, Takatoshi. OLED Display Fundamentals and
`Applications: Fundamentals and Applications, John Wiley &
`Sons, Incorporated, 2012. (“Tsujimura”)
`Crawford, Gregory P. Flexible flat panel display technology.
`Vol. 3. West Sussex: Wiley, 2005. (“Crawford”)
`U.S. Patent Application Pub. No. 2003/0127657 (“Park”)
`U.S. Patent No. 7,498,733 (“Shimoda”)
`U.S. Patent Application Pub. No. 2002/0000576 (“Inukai”)
`U.S. Patent Application Pub. No. 2002/0009538 (“Arai”)
`Declaration of Dr. Adam Fontecchio
`Curriculum Vitae of Adam Fontecchio
`Claim Construction Memorandum & Order, Solas OLED Ltd. v.
`Samsung Display Co., Ltd. et al., 2:19-cv-00152-JRG (E.D.
`Tex. Apr. 17, 2020)
`Declaration of Jared R. Frisch in Support of Petitioner’s Motion
`for Admission Pro Hac Vice (“Frisch Decl.”)
`Declaration of Jeffrey H. Lerner in Support of Petitioner’s
`Motion for Admission Pro Hac Vice (“Lerner Decl.”)
`Declaration of Robert T. Haslam in Support of Petitioner’s
`Motion for Admission Pro Hac Vice (“Haslam Decl.”)
`Rebuttal Expert Report of Thomas L. Credelle regarding Validity
`of U.S. patent Nos. 6,072,450, 7,446,338, and 9,256,311, dated
`June 22, 2020 (Public Redacted Version)
`Richard Flasck Deposition Transcript dated Nov. 16, 2020
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`
`1013
`
`1014
`1015
`1016
`1017
`1018
`1019
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`
`
`- i -
`
`

`

`
`
`Exhibit
`1026
`
`1027
`
`1028
`
`Description
`Pretrial Hearing Transcript in Solas OLED Ltd. v. Samsung
`Display Co., Ltd. et al., 2:19-cv-00152-JRG (E.D. Tex. Sept. 8,
`2020)
`Pretrial Motion Order, in Solas OLED Ltd. v. Samsung Display
`Co., Ltd. et al., 2:19-cv-00152-JRG, Dkt. 279 (E.D. Tex. Sept.
`30, 2020)
`Claim Construction Order, Solas OLED Ltd. v. Dell Inc., et al.,
`6:19-CV-00514, -00515, -00537 (W.D. Tex. Aug. 30, 2020)
`
`
`
`
`- ii -
`
`

`

`Table of Contents
`
`
`
`I.
`II.
`
`Introduction ...................................................................................................... 1
`Claim Construction .......................................................................................... 1
`A.
`“transistor array substrate” .................................................................... 1
`B.
`“the pixel electrodes being arrayed along the interconnections
`between the interconnections on the surface of the transistor
`array substrate” ...................................................................................... 2
`“write current” ....................................................................................... 2
`C.
`“project from a surface of the transistor array substrate” ..................... 2
`D.
`III. Ground I: Obviousness Over Kobayashi and Shirasaki .................................. 4
`A. Motivation to Combine ......................................................................... 5
`B.
`Reasonable Expectation of Success ...................................................... 9
`C.
`Limitation 1[b], “a plurality of interconnections which are
`formed to project from a surface of the transistor array
`substrate, and which are arrayed in parallel to each other” ................14
`Limitation 1[c]: “a plurality of pixel electrodes for the plurality
`of pixels, respectively, the pixel electrodes being arrayed along
`the interconnections between the interconnections on the
`surface of the transistor array substrate” .............................................19
`IV. Ground II: Obviousness Over Childs and Shirasaki .....................................21
`A. Motivation to Combine .......................................................................22
`B.
`Reasonable Expectation of Success ....................................................23
`C.
`Limitation 1[c]: “a plurality of pixel electrodes for the plurality
`of pixels, respectively, the pixel electrodes being arrayed along
`the interconnections between the interconnections on the
`surface of the transistor array substrate” .............................................27
`
`D.
`
`
`
`- iii -
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`

`

`
`
`I.
`
`INTRODUCTION
`The Challenged Claims are unpatentable as explained in the Petition (Paper 1,
`
`“Pet.”). The arguments in Patent Owner Solas OLED, Ltd. (“Solas”)’s Response
`
`(Paper 18, “POR”) are unavailing.
`
`II. CLAIM CONSTRUCTION
`Solas has declined to offer any claim construction arguments. Its Response
`
`purports to apply certain district court claim constructions, but it does not explain
`
`whether or why the Board should adopt those constructions here. POR, 12–13.
`
` “transistor array substrate”
`A.
`Petitioner contends “transistor array substrate” should be construed as “a
`
`layered structure including a bottom insulating substrate through a topmost
`
`insulating layer on whose surface the pixel electrodes are formed,” which contains
`
`an array of transistors. Pet., 21–23. Solas agreed with this construction in its
`
`preliminary response and the district court litigation. Paper 6, 27–28; Ex. 2004, 1.
`
`In district court, “transistor array substrate” was construed more broadly than
`
`Petitioner’s proposal, as a “layered structure upon which or within which a transistor
`
`array is fabricated.” Ex. 1020, 15.1 Although Solas previously agreed to Petitioner’s
`
`
`1 In subsequent litigation, the district court in the Western District of Texas
`
`adopted the same construction for each term as the Eastern District of Texas. Ex.
`
`1028.
`
`
`
`- 1 -
`
`

`

`
`
`construction, its POR applies the district court’s broader construction. Solas does not
`
`dispute that the prior art satisfies both constructions. As discussed below, the
`
`Petition’s arguments are, if anything, strengthened under the district court’s
`
`construction.
`
`B.
`
`“the pixel electrodes being arrayed along the interconnections
`between the interconnections on the surface of the transistor
`array substrate”
`Consistent with the Petition (Pet., 25), the parties have agreed that this term
`
`should be construed as “the pixel electrodes are arrayed along the interconnections
`
`and located between the interconnections, and the pixel electrodes are on the surface
`
`of the transistor array substrate.” Ex. 2004, 1. The district court adopted this as an
`
`agreed construction. Ex. 1020, 8.
`
`“write current”
`C.
`In district court, “write current” was construed as “pull-out current.” Ex. 1020,
`
`23. While neither party has asked the Board to construe this term, the Petition is fully
`
`consistent with the district court’s construction. Solas does not dispute the existence
`
`of the “write current” in the prior art, including in the Shirasaki reference.
`
`“project from a surface of the transistor array substrate”
`D.
`The Petition explained that interconnections formed to “project from a surface
`
`of the transistor array substrate” should be interpreted to encompass interconnections
`
`which are formed to extend above the upper surface of the topmost layer of the
`
`transistor array substrate, consistent with the specification. Pet., 23–24. This phrase
`
`
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`- 2 -
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`

`

`
`
`was construed more broadly in the district court litigation to mean “extend beyond
`
`an outer surface of the transistor array substrate.” Ex. 1020, 18. The Petition is fully
`
`consistent with the district court’s construction.
`
`Although Solas does not ask for construction, its POR attempts to import an
`
`additional limitation in an effort to distinguish the Kobayashi reference. Solas asserts,
`
`without support from the ’338 patent, that the interconnections must “begin near th[e]
`
`surface” of the transistor array substrate. POR, 29. Solas neglects to mention that its
`
`same argument was ordered stricken in district court for being inconsistent with the
`
`court’s construction. Ex. 1026, 88:8–17. The ’338 patent’s preferred embodiment
`
`refutes Solas’s argument: “common interconnection 91”—which is formed on an
`
`“insulating line 61” that sits above the transistor array substrate 50—is said to
`
`“project upward from the surface of” the transistor array substrate. Ex. 1001, 10:54–
`
`58. This is shown in Figure 6:
`
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`- 3 -
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`
`
`
`III. GROUND I: OBVIOUSNESS OVER KOBAYASHI AND SHIRASAKI
`It would have been obvious to modify Kobayashi by replacing its two-
`
`transistor circuit with the three-transistor circuit that Shirasaki taught as an
`
`improvement, resulting in a display that satisfies claims 1–2, 5–6, and 9–11 of
`
`the ’338 patent. Pet., 53–56. Ex. 1018, ¶¶ 136, 143, 145–146; Ex. 1004, ¶¶ [0003]-
`
`[0004], [0009], [0018]. This simple combination applies a known improvement
`
`(Shirasaki’s three-transistor circuit) to achieve a predictable result. Shirasaki, which
`
`is prior art by the same lead inventor as the ’338 patent, not only disclosed the same
`
`three-transistor circuit that served as the ’338 patent’s purported point of novelty in
`
`prosecution, but also detailed how to implement it, and explained how it provided
`
`improvements over two-transistor circuit structures. See, e.g., Ex. 1004, ¶¶ [0018],
`
`
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`- 4 -
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`

`

`
`
`[0068]–[0088]. Indeed, Solas does not dispute that Shirasaki meets the circuit
`
`structure recited in element 1[f].
`
`Solas disputes only (1) motivation to combine Kobayashi with Shirasaki, (2)
`
`reasonable expectation of success in the combination, and (3) Kobayashi’s
`
`disclosure of limitations 1[b] and 1[c]. Solas does not contest the Petition’s showings
`
`for the other limitations of claim 1, or for dependent claims 2, 5–6, and 9–11.
`
`A. Motivation to Combine
`Shirasaki provided express motivation to replace Kobayashi’s two-transistor
`
`voltage-driven pixel circuit (Fig 1, below left) with Shirasaki’s three-transistor
`
`current-driven pixel circuit (Fig. 5B, below right). Pet., 53–56.
`
`
`
`Kobayashi’s 2-Transistor Circuit
`Ex. 1003, Fig. 1 (annotated excerpt)
`
`
`Shirasaki’s 3-Transistor Circuit
`Ex. 1004, Fig. 5B (annotated)
`
`
`Shirasaki explains that replacing a two-transistor voltage-driven circuit (as in
`
`Kobayashi) with Shirasaki’s
`
`three-transistor current-driven circuit confers
`
`advantages including “suppress[ing] the influence of variations in the voltage current
`
`
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`- 5 -
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`

`
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`characteristic of the control system and allow[ing] the optical element to stably
`
`display images with desired luminance.” Ex. 1004, ¶ [0018]; id., ¶ [0011]; Ex. 1018,
`
`¶¶ [0138]–[0139]. As Solas’s expert conceded, Shirasaki motivates a POSA “away
`
`from using two-transistor[] circuits using polysilicon transistors, and toward the
`
`three-transistor structure that [Shirasaki] provided.” Ex. 1025, 39:22–40:4.
`
`Solas’s argument (POR, 17–19) that Kobayashi and Shirasaki are “directed to
`
`different problems” is legally misplaced, as “the motivation to combine inquiry
`
`focuses on whether one of ordinary skill would have been motivated to combine the
`
`teachings of both references as a whole, not whether the problems solved by the prior
`
`art are the same.” Google LLC v. Virentem Ventures, LLC, IPR2019-01247, 2020
`
`WL 1140494, *12 (PTAB March 9, 2020). It is also factually flawed: Shirasaki and
`
`Kobayashi are both directed to improving image characteristics in active matrix
`
`OLED displays, lowering power consumption, and extending their useful life, e.g.,
`
`Ex. 1003, ¶¶ [0104], [0083]–[0084]; Ex. 1004, ¶¶ [0019], [0094]. Solas cites no legal
`
`support for its “directed to different problems” proposition.
`
`Further, Solas does not dispute that Kobayashi and Shirasaki are in the same
`
`field of endeavor as the ’338 patent. The references unquestionably are analogous
`
`art. Donner Tech., LLC v. Pro Stage Gear, LLC, 979 F.3d 1353, *1359 (Fed. Cir.
`
`2020) (“analogous art” includes art “from the same field of endeavor, regardless of
`
`the problem addressed” (citation omitted)).
`
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`- 6 -
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`

`

`
`
`There is also no merit to Solas’s arguments about Shirasaki’s teachings.
`
`Contrary to Solas’s assertion (POR, 22), Shirasaki teaches benefits of replacing a
`
`two-transistor voltage-driven circuit with a three-transistor current-driven circuit.
`
`Shirasaki presents its circuit as improving upon “conventional” two-transistor
`
`circuits that are described as using a “voltage driving method” (Ex. 1004, ¶¶ [0004]–
`
`[0006]), like the two-transistor voltage-driven circuit of Kobayashi (below left).
`
`Shirasaki provides Figure 11 (below right) as an example.
`
`
`
`Kobayashi 2-Transistor Circuit
`Ex. 1003, Fig. 1 (annotated excerpt)
`
`
`“Conventional” 2-Transistor Circuit
`Described in Shirasaki
`Ex. 1004, Fig. 11, ¶¶ [0004]–[0006]
`
`
`As Solas notes, POR, 21–22, Shirasaki also discourages using “four or more
`
`transistors” per circuit, which would decrease the emission area of the pixel. Ex.
`
`1004, ¶ [0009]. Shirasaki thus specifically encourages the POSA to replace a two-
`
`transistor voltage-driven circuit with Shirasaki’s three-transistor current-driven
`
`circuit.
`
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`- 7 -
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`

`

`
`
`Similarly, Solas’s assertions about amorphous versus polysilicon transistors
`
`lack support and are contradicted by Shirasaki. Shirasaki describes its circuit
`
`structure as overcoming problems with two-transistor polysilicon transistor circuits.
`
`Ex. 1004, ¶ [0007] (describing problems “if the channel layers of the transistors 103
`
`and 104 are made of polysilicon” that “result[] in variations in the display
`
`characteristics of the individual pixels in a single panel”). And Solas’s expert admits
`
`that Shirasaki expressly “warn[s] about the use of polysilicon as opposed to
`
`amorphous silicon transistors,” Ex. 1025, 38:3–8.
`
`Solas is also wrong in asserting that in Shirasaki there “is no suggestion to use
`
`a three-transistor circuit that uses amorphous silicon transistors.” POR, 22. Shirasaki
`
`expressly teaches that either amorphous silicon or polysilicon transistors may be
`
`used. Ex. 1004, ¶ [0112]. (“[T]he transistors . . . are thin film transistors having
`
`amorphous silicon as a semiconductor layer . . . . However, a thin film transistor
`
`using a polysilicon semiconductor layer can also be used.”); Ex. 1025, 41:10–42:18.
`
`Finally, Solas’s comment that Kobayashi, like Shirasaki, describes use of a
`
`capacitor in each pixel to store data is of no moment. POR, 22–23. If anything, the
`
`fact that Kobayashi’s circuit included a capacitor to store data reinforces the
`
`expectation of success in replacing Kobayashi’s circuit with Shirasaki’s three-
`
`transistor circuit, which uses a capacitor for the same reason.
`
`
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`- 8 -
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`

`

`
`
`B. Reasonable Expectation of Success
`A POSA would have had a reasonable expectation of success in replacing
`
`Kobayashi’s two-transistor circuit with Shirasaki’s three-transistor circuit. Solas
`
`does not dispute that this substitution could be performed without altering any of the
`
`layers above Kobayashi’s transistor array substrate. Pet., 56–57. It would simply
`
`require changing the photomasks used to fabricate the transistor array and relocating
`
`certain contact holes. Pet., 57 & n.6; Ex. 1018, ¶ [0146]. These were routine and
`
`predictable manufacturing steps, see id., which Solas does not dispute.
`
`Nevertheless, Solas contends—without evidentiary support2—that a POSA
`
`would be unable to make this substitution because it would require changing “[t]he
`
`way that the existing transistors and other elements are connected, operate, and are
`
`driven.” POR, 23. Solas ignores that Shirasaki expressly teaches a POSA to replace
`
`
`2 Solas cites only the declaration of its expert, which repeats the POR’s conclusory
`
`assertions near-verbatim with no factual analysis or citation to evidence (compare,
`
`e.g., POR at 24–26 with Ex. 2005, ¶¶ 86–92), and deserves little or no weight.
`
`Solas does not even provide citations for specific points; it provides only blanket
`
`citations, via footnote from the section heading, to a series of paragraphs in its
`
`expert declaration repeating the POR’s assertions—something it does throughout
`
`its Response.
`
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`

`
`
`“conventional” two-transistor voltage-controlled circuits like in Kobayashi with
`
`Shirasaki’s three-transistor current-controlled circuit (see above page 7), and
`
`explains how to connect, operate, and drive this circuit:
`
`• Connection: Shirasaki details how to connect the transistors to one
`another and associated signal lines, as shown in Figure 5A below. Ex.
`1025, 44:10–14; e.g., Ex. 1004, ¶ [0068] (“The circuit configuration of
`the pixel driving circuit Di,j will be described in detail below.”).
`
`
`
`• Operation: Shirasaki details how to operate the circuit. Ex. 1004,
`¶¶ [0069]–[0088]. Figure 7, “a timing chart showing an operation of a
`driving circuit” Ex. 1004, ¶ [0034], illustrates voltages and currents on
`the signal lines of Shirasaki’s circuit, both during the selection period
`(“TSE”) and non-selection period (“TNSE”). Ex. 1025, 57:3–59:15; see
`Ex. 1004, ¶¶ [0069]–[0088].
`
`
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`- 10 -
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`

`

`
`
`
`• Driving circuitry: Shirasaki details the driving circuitry: selection scan
`drive 3 and voltage scan driver 4 are “shift-register[s],” Ex. 1004, ¶¶
`[0069]–[0070], and data driver 5 is a “current sink,” id., ¶ [0072].3
`
`Solas also argues the voltage- and current-controlled circuit structures of
`
`Kobayashi and Shirasaki are “fundamentally different.” POR, 24–25. This again
`
`
`3 A POSA would have been familiar with such circuitry and how to implement it.
`
`Ex. 1025, 50:14–17 (“Shift registers have been around for close to a hundred
`
`years”); id., 53:8–10 (“There were current sink drivers known in the prior art prior
`
`to Shirasaki.”).
`
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`- 11 -
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`

`

`
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`disregards that Shirasaki specifically encourages replacing conventional voltage-
`
`controlled circuits (like Kobayashi’s) with its three-transistor current-controlled
`
`circuit and details how to do so. See supra.
`
`Solas’s arguments that “there are significant additional requirements on the
`
`design of the switch transistor and the data line (such as very low resistance) not
`
`present in the Kobayashi voltage written (programmed) design,” POR, 24, also lack
`
`merit. Shirasaki explicitly teaches the very “requirement” Solas identifies: use of
`
`low resistance materials. See Ex. 1004, [0042] (teaching the selection lines, current
`
`lines, and emission voltage scan lines should be “made of chromium, chromium
`
`alloy, aluminum, aluminum alloy, titanium, titanium alloy, or a low resistance
`
`material selected from at least one of these materials.”) (emphasis added). Moreover,
`
`Solas’s expert admits that “in this type of manufacturing process, there are only a
`
`limited number of metals or conductors that--that generally can be used. And these
`
`are--what [Shirasaki’s] listed are some of the more common ones.” Ex. 1025, 63:17–
`
`21. Similarly, Solas’s assertion that “the scan line drivers Ydr of Kobayashi” are
`
`“unsuitable to drive the pixel circuit of Shirasaki” (POR, 24) disregards that
`
`Shirasaki expressly taught the appropriate driving circuity, as discussed in the bullets
`
`above.
`
`Finally, Solas argues “independently” that the “Petition does not address a
`
`‘write current’ in the context of the proposed combination,” and contends that using
`
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`- 12 -
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`

`

`
`
`Shirasaki’s pixel circuit while “leaving the alleged ‘write current’ from Kobayashi
`
`unmodified” would result in a non-functioning device. POR, 25–26. This
`
`misunderstands the combination. As the Petition explained, a POSA would be
`
`“motivat[ed] to replace Kobayashi’s two-transistor pixel circuit with Shirasaki’s
`
`three transistor pixel circuit.” Pet., 55. And in Shirasaki’s circuit, the write current
`
`is the memory current α, as Petitioner stressed in its supplemental brief:
`
`[The write current] limitation is met by the Shirasaki circuit as
`advanced in the Petition. As illustrated by annotated Fig. 5A of
`Shirasaki below, the “memory current” α that flows in Shirasaki’s
`three-transistor circuit when “transistor 11” (the claimed “switch
`transistor”) “is turned on,” Ex. 1004, ¶ [0072], [0084], is the same as
`“pull-out current” A shown in annotated Fig. 2 of the ’338 patent, Ex.
`1001, 15:34–37:
`
`Shirasaki, Fig. 5A (annotated)
`
`
`
`
`
`’338 Patent, Fig. 2
`(annotated)
`
`- 13 -
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`

`

`
`
`Paper 7 at 3. As the Board recognized, “the circuit in Figure 5B of Shirasaki is
`
`substantially identical to the circuit disclosed in Figure 2 of the ’338 patent.” Paper
`
`9, 31; see Ex. 1025, 43:22–44:5. Accordingly, in the proposed combination, the
`
`“switch transistor [transistor 11] . . . makes a write current [α] flow between the drain
`
`and the source of the driving transistor [23],” as recited in claim 1.
`
`C. Limitation 1[b], “a plurality of interconnections which are formed
`to project from a surface of the transistor array substrate, and
`which are arrayed in parallel to each other”
`Kobayashi discloses limitation 1[b]. Pet., 45–46. Solas does not dispute that
`
`“auxiliary wiring elements 118” are interconnections arrayed in parallel to each
`
`other. Solas solely disputes whether the auxiliary elements are “formed to project
`
`from a surface of the transistor array substrate.” Kobayashi discloses that they are.
`
`Solas purports to base its argument on the district court’s construction of
`
`“project from a surface of the transistor array substrate” to mean “extend beyond an
`
`outer surface of the transistor array substrate.” Ex. 1020, 18. Yet as shown in Figure
`
`7, the auxiliary wiring elements 118 (red) “extend beyond an outer surface” of the
`
`transistor array substrate (orange) and thus meet that construction.
`
`
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`- 14 -
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`

`

`
`
`
`
`Solas attempts to impose further limitations, arguing that “[t]he Court’s
`
`construction . . . requires that there be some connection or relationship between the
`
`thing ‘projecting’ and the surface it is projecting from,” and that “[t]his is true of the
`
`plain meaning of term as well.” POR, 27. There is, of course, a relationship between
`
`auxiliary wiring elements 118 and the transistor array substrate: they are separated
`
`by an insulating film, just as common interconnections 91 are in the ’338 patent’s
`
`preferred embodiment.
`
`If Solas means that interconnections must physically contact the transistor
`
`array substrate or be “near” its surface, Solas is improperly importing a limitation
`
`that is inconsistent with the district court construction. In fact, the court previously
`
`struck the same argument as inconsistent with its construction, when it was
`
`attempted by Solas’s district court expert, Mr. Credelle. See Ex. 1024, ¶ 221 (Mr.
`
`Credelle arguing “the plain meaning of ‘project from a surface’ and the Court’s
`
`construction ‘extend beyond an outer surface’ require that there be some connection
`
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`- 15 -
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`

`

`
`
`or relationship between the thin[g] ‘projecting’ and the surface it is projecting from”);
`
`Ex. 1026, 88:8–17 (“[W]ith regard to the claim construction testimony of Mr.
`
`Credelle, particularly as located in Paragraph 221 of his report, I find that that is
`
`improper . . . . And I’m going to strike Paragraph 221 . . . .”). The district court did
`
`so prior to Solas filing its POR. Ex. 1027, 9, 12 (ordered Sept. 30, 2020).
`
`Remarkably, Solas’s expert in this proceeding—much of whose declaration
`
`copies near-verbatim from an earlier report of Mr. Credelle4—submitted opinions
`
`nearly identical to the ones stricken by the court. Compare Ex. 1024, ¶ 221 with Ex.
`
`2005, ¶ 95. Mr. Flasck testified he was “not aware” of the district court’s opinion,
`
`
`4 Compare, e.g., Ex. 1024, ¶¶ 221, 228, 237 with Ex. 2005, ¶¶ 95, 104, 127. Mr.
`
`Flasck even acknowledged they are “quite similar,” Ex. 1025, 88:22–89:5, despite
`
`the fact that he (i) did not talk to Mr. Credelle, (ii) purportedly did not take his
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`opinions from Mr. Credelle’s report, id., 10:13–15, 82:6–15, 89:6–12, and (iii)
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`testified the writing of his declaration was “independent” from Mr. Credelle, id.,
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`27:2–5. Mr. Flasck’s only explanation for the near-identity between much of his
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`declaration and Mr. Credelle’s report is that his declaration was written through an
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`“iterative process” with Solas’s attorneys. Id., 82:9–15, 90:1–4, 90:18–20. The
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`record calls into question whether Mr. Flasck’s declaration deserves any weight.
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`Ex. 1025, 83:2–12, and admitted if he were to consider it, his opinion “may change,”
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`id., 85:12–86:2.
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`Moreover, Solas’s argument is contradicted by the ’338 patent’s disclosures,
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`including the specification’s preferred embodiment. As shown in annotated Figure
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`6 below, common interconnection 91 is not formed directly on transistor array
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`substrate, i.e., there is no “connection or relationship” between common
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`interconnection 91 and the transistor array substrate; rather, insulating line 61 is
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`formed between the two. Yet as the district court noted, the specification describes
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`common interconnection 91 as projecting from the surface of the transistor array
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`substrate. Ex. 1020, 17 (citing 10:54–58, stating “[t]he common interconnection 91
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`is formed [to] . . . project upward from the surface of the planarization film 33.”).
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`There is no merit to Solas’s assertion that Figure 6 supports its position. POR, 28.
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`Indeed, the same flawed argument was made by Solas’s district court expert, Ex.
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`1024, ¶¶ 223–224, and rejected by the district court.
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`In fact, Kobayashi’s auxiliary wiring elements 118 project from the surface of
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`the
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`transistor array substrate
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`in exactly
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`the same manner as common
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`interconnections 91 of the ’338 patent: as shown in annotated Figure 7 below, they
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`are separated from the transistor array substrate by an insulating layer (“partition
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`walls 120” of Kobayashi).
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`
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`Solas tries to argue that Kobayashi’s auxiliary elements 118 differ from the
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`common interconnections of the ’338 patent because allegedly “[t]hey are far above
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`the surface, relative to their own dimensions, and their extent in the vertical direction
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`(the direction they would be ‘projecting’ or ‘protruding’ is small relative to the other
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`relevant dimensions”). POR, 29–30. This is meritless. Nothing in the ’338 patent’s
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`claims or specification indicates the term “project from” has any relationship to the
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`thickness of the insulating layer between an interconnection and the transistor array
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`substrate. Further, neither the ’338 patent nor Kobayashi indicates its figures are
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`drawn to scale. “[I]t is well established that patent drawings do not define the precise
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`proportions of the elements and may not be relied on to show particular sizes if the
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`specification is completely silent on the issue.” Hockerson-Halberstadt, Inc. v. Avia
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`Group Intern, Inc., 222 F.3d 951, 956 (Fed. Cir. 2000).5
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`D. Limitation 1[c]: “a plurality of pixel electrodes for the plurality of
`pixels, respectively, the pixel electrodes being arrayed along the
`interconnections between the interconnections on the surface of
`the transistor array substrate”
`Kobayashi discloses limitation 1[c]. Pet., 46–48. As shown in annotated
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`Figures 7 and 6a below, Kobayashi discloses a plurality of first electrodes 117,
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`arrayed along and between the auxiliary wiring elements 118.
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`5 In deposition, Mr. Flasck asserted for the first time that Kobayashi requires a
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`partition wall height of 3 µm. Ex. 1025, 71:17–20. In fact, Kobayashi provides a
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`range of thicknesses, including a thickness of 1 µm. Ex. 1003, [0077].
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`While not clearly articulated, Solas’s argument appears to be that Kobayashi’s
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`first electrodes 117 should not be considered to be arrayed along and between the
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`auxiliary elements 118, because they are not coplanar. See POR, 32 (“Indeed,
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`portions of the pixel electrodes are almost directly below the interconnections, as
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`shown in the figure above.”). Solas’s argument is contradicted by the disclosures of
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`the ’338 patent, including Figure 6 which shows a nearly identical arrangement to
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`Kobayashi with respect to the “sub-pixel electrodes 20a” and the “common
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`interconnection 91”:
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`The specification is clear that sub-pixel electrodes 20 are arrayed along and between
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`common interconnection 91. See, e.g., Ex. 1001, 5:61–64 (“[T]he plurality of sub-
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`pixel electrodes 20a are arrayed in the horizontal direction between the feed
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`interconnection 90 and the adjacent common interconnection 91.”); id., 5:64–66.
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`Likewise, Kobayashi’s first electrodes 117 are arrayed along and between the
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`auxiliary wiring elements 118.
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`IV. GROUND II: OBVIOUSNESS OVER CHILDS AND SHIRASAKI
`It would have been obvious to replace Child’s two-transistor circuit with
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`Shirasaki’s three-transistor circuit, resulting in a display that satisfies claims 1–3 and
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`5–13 of the ’338 patent. Pet., 79–81. Solas disputes only (1) motivation to combine,
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`(2) reasonable expectation of success, and (3) whether the combination of Childs
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`and Shirasaki renders obvious limitation 1[c]. Solas does not otherwise dispute that
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`the combination of Childs and Shirasaki renders obvious the remaining limitations
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`of claim 1 and claims 2–3 and 5–13.
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`A. Motivation to Combine
`To contest the motivation to combine Childs with Shirasaki, Solas repeats the
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`same arguments it made with respect to Ground I above, which lack merit as to
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`Childs and Shirasaki as well.
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`Importantly, Solas ignores Childs’ explicit teaching that its improvements to
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`interconnections could be used with alternative circuit structures to the two-
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`transistor circuit structure provided in its example. Ex. 1005, 7:5–9 (“Figure 1
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`depicts, by way of example, one specific pixel circuit configuration…. [I]t should
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`readily be understood that the present invention may be applied to the pixel barriers
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`of such a device [i.e., an active matrix display device] regardless of the specific pixel
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`circuit configuration of the device.” (emphases added)). As the Petition explains,
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`Shirasaki taught an improvement to the circuit structure over the two-transistor
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`circuit used in Childs, and a POSA would be motivated by Shirasaki to apply its
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`improvement to Childs. Pet., 79–81. Contrary to Solas’s assertion (POR, 36), the
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`Petition does not simply rest on Childs and Shirasaki being “similar.”
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`As the Petition explains, Shirasaki provides express motivation to replace
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`Child’s two-transistor pixel circuit with Shirasaki’s three-transistor pixel circuit, to
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`“suppress the influence of variations in the voltage current characteristic of the
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`control system and allow[] the optical element to stably display images with desired
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`luminance.” Ex. 1004, ¶ [0018]; see id., ¶ [0011]; Ex. 1018, ¶¶ [0138]–[0139].
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`Shirasaki taught replacing two-transistor voltage-controlled circuits, like the
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`example in Childs, with its three-transistor current-controlled circuit. See, e.g., Ex.
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`1004, Fig. 11. Solas’s expert concedes that Shirasaki guides “away from using two-
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`transistor[] circuits using polysilicon transistors”—like the example in Childs—
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`“toward the three-transistor structure that [Shirasaki] provided.” Ex. 1025, 39:22–
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`40:4. That both Childs and Shirasaki both used a capacitor to store pixel data, see
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`POR, 39, only strengthens the motivation to combine, underscoring the expectation
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`of success in combining the teachings.
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`Solas does not dispute that Childs and Shirasaki are both directed to improving
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`active matrix OLED panels featuring thin-film transistor arrays. Solas’s assertion
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`that Childs and Shirasaki focus on different problems does not detract from the
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`POSA’s motivation to combine the