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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
`
`
`SAMSUNG DISPLAY CO., LTD.,
`Petitioner
`
`v.
`
`SOLAS OLED, LTD.,
`Patent Owner
`____________
`
`Case IPR2020-00320
`Patent No. 7.446,338
`____________
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`PATENT OWNER RESPONSE
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`IPR2020-00320 (’338 Patent)
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`TABLE OF CONTENTS
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`I.
`II.
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`Summary of Grounds .................................................................................... 1
`The ’338 Patent (Ex. 1001) ........................................................................... 1
`A.
`Summary of ’338 Patent ...................................................................... 1
`B.
`Elements of ’338 Patent ...................................................................... 5
`1. Multi-transistor OLED Circuit ....................................................... 5
`2. Low Resistance Electrodes ............................................................ 5
`3. Color Display ................................................................................. 6
`’338 Patent Claims .............................................................................. 6
`C.
`’338 Patent Prosecution History .......................................................... 9
`D.
`III. Person of Ordinary Skill in The Art ............................................................ 11
`IV. Claim Construction ...................................................................................... 12
`V. Ground I: Obviousness Over Kobayashi and Shirasaki .............................. 13
`A. Overview of Kobayashi (Ex. 1003) .................................................. 13
`B. Overview of Shirasaki (Ex. 1004) ..................................................... 15
`Failure to Show Why One Skilled in the Art Would Be
`C.
`Motivated to Combine Kobayashi with Shirasaski as Proposed
`by Petitioner ...................................................................................... 17
`1. Kobayashi and Shirasaki are directed to different problems, and a
`POSITA with Kobayashi would not be motivated to look to
`Shirasaki as Petitioner proposes .................................................. 17
`2. Petitioner’s arguments that Kobayashi and Shirasaki both disclose
`OLEDs or TFTs are insufficient to show motivation to combine 19
`3. Petitioner’s other arguments fail and mischaracterize what
`Shirasaki actually teaches or suggests. ........................................ 20
`Failure to Show How One Skilled in the Art Would Have
`Combined Kobayashi with Shirasaski as Proposed by Petitioner
`or that One Skilled in the Art Would Have a Reasonable
`Expectation of Success ...................................................................... 23
`Failure to Show that the Combination of Kobayashi in View of
`Shirasaski Satisfies Limitation 1[b]: “a plurality of
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`D.
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`E.
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`F.
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`C.
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`D.
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`interconnections which are formed to project from a surface of
`the transistor array substrate, and which are arrayed in parallel
`to each other” .................................................................................... 26
`Failure to Show that the Combination of Kobayashi in View of
`Shirasaski Satisfies Limitation 1[c]: “a plurality of pixel
`electrodes for the plurality of pixels, respectively, the pixel
`electrodes being arrayed along the interconnections between the
`interconnections on the surface of the transistor array substrate” ..... 31
`VI. Ground II: Obviousness Over Childs and Shirasaki .................................... 33
`A. Overview of Childs (Ex. 1005) ......................................................... 33
`Failure to Show Why One Skilled in the Art Would Be
`B.
`Motivated to Combine Childs with Shirasaski as Proposed by
`Petitioner ........................................................................................... 35
`1. Childs and Shirasaki are directed to different problems, and
`POSITA with Childs would not be motivated to look to Shirasaki
`as Petitioner proposes .................................................................. 35
`2. Petitioner’s arguments that Childs and Shirasaki are similar are
`insufficient to show motivation to combine ................................ 36
`3. Petitioner’s other arguments fail and mischaracterize what
`Shirasaki actually teaches or suggests. ........................................ 37
`Failure to Show How One Skilled in the Art Would Have
`Combined Kobayashi with Shirasaski as Proposed by Petitioner
`or that One Skilled in the Art Would Have a Reasonable
`Expectation of Success ...................................................................... 40
`Failure to Show that the Combination of Kobayashi in View of
`Shirasaski Satisfies Limitation 1[c]: “a plurality of pixel
`electrodes for the plurality of pixels, respectively, the pixel
`electrodes being arrayed along the interconnections between the
`interconnections on the surface of the transistor array substrate” ..... 43
`VII. Conclusion ................................................................................................... 48
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`IPR2020-00320 (’338 Patent)
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`PATENT OWNER’S EXHIBIT LIST
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`Ex. Description
`2001 United States Patent Application Publication 2004/0256617 A1
`2002 Defendants’ Responsive Claim Construction Brief
`2003 Defendants’ Claim Construction Presentation
`2004 Solas’s Notice of Agreement on Previously Disputed Claim Construction
`Terms
`2005 Declaration of Richard A. Flasck
`2006 Curriculum Vitae of Richard A. Flasck
`2007 Transcript of Deposition of Dr. Adam Fontecchio on September 11, 2020
`2008 The New Oxford American Dictionary (2d ed. 2005)
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`I.
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`Summary of Grounds
`Petitioner challenges claims 1–3 and 5–13 of U.S. Patent 7,446,338 (“’338
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`patent,” Exhibit 1001) under two grounds (Pet. at 10–11):
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`• Ground I: Claims 1–2, 5–6, and 9–11 are obvious over the combination of
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`Kobayashi and Shirasaki.
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`• Ground II: Claims 1–3 and 5–13 are obvious over the combination of Childs
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`and Shirasaki.
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`For the reasons below, Petitioner has not shown unpatentability under either ground
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`and the Board should affirm the validity of the challenged claims.
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`II. The ’338 Patent (Ex. 1001)1
`A.
`Summary of ’338 Patent
`The ‘338 patent, titled “Display Panel,” was filed by T. Shirasaki, et al. on
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`Sept. 26, 2005 and issued on Nov. 4, 2008. It claims a priority date of Sept. 29, 2004.
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`Casio, the original assignee of the ‘338 patent was a pioneer in the
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`development of practical and high performing displays utilizing organic light
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`emitting diodes (OLEDs). The ’338 patent concerns display panels with light-
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`emitting elements, such as organic electroluminescent display panels. (Ex. 1001,
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`1 See Ex. 2001, Declaration of Richard A. Flasck (“Flasck Decl.”) ¶¶ 33–63.
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`’338 patent at 1:14–21.) A commonly used organic electroluminescent display
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`technology is the organic light emitting diode, or OLED. OLED display panels are
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`currently used in high-end mobile phones, watches, televisions, and other products
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`from several manufacturers.
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`Displays used in phones, watches, televisions, etc. contain a two-dimensional
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`array of picture elements, commonly called pixels, that are made up of red, green,
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`and blue “subpixels.” By controlling the light emission of the subpixels, a desired
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`image can be displayed. An example of this layout of sub-pixels is shown in the
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`below annotated depiction of Figure 1 of the patent:
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`As the ’338 patent explains, the highest quality OLED displays are “active
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`matrix.” (Ex. 1001, ’338 patent at 1:19–21.) This means that each sub-pixel in the
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`display has active elements and capacitors associated with it, which are responsible
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`for sending the correct amount of current through the electroluminescent element
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`and thus controlling the brightness of the subpixel. The ’338 patent shows an
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`example sub-pixel circuit in Figure 2:
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`In this example circuit, the light-emitting element is shown as the diodes 20.
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`The TFT 23 in this example is called the “driving transistor”, the TFT21 is the
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`“switch transistor”, and TFT22 is the “hold transistor”. The driving method has a
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`“selection period” and an “emission period.” During the selection period, the switch
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`and hold transistors are turned on and current flows through the drive transistor (and
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`not the diode) to set a voltage on the storage capacitor 24 that will determine the
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`amount of current flowing to the diode during the “emission period”. During the
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`emission period, a “driving current” flows through the driving transistor and is
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`supplied to the light emitting diode. (Ex. 1001, ’338 patent at 14:51–16:13.) After a
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`“frame” of data is displayed (a frame time is typically 1/60 sec and represents one
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`image of a video signal), the sub-pixels are selected row by row to be written with
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`new information.
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`This flow of current during the selection period, which is “pulled through
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`(out)” of the driver transistor, causes a corresponding charge to form between the
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`electrodes of the capacitor 24. When the switch and holding transistors are turned
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`off, a current flows through light emitting diode that depends on the charge on the
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`capacitor, and in this example equals the write current. (Ex. 1001,’338 patent at
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`15:54–16:13.) A POSITA in 2004 would understand that the direction of current
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`flow is somewhat arbitrary and depends on the circuit design, e.g. channel type for
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`transistors and orientation of the light emitting diode relative to the driving
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`transistor.
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`The patent specification describes a structure that implements a circuit of this
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`type as a series of thin-film layers in the display panel, and the patent claims aspects
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`of this structure.
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`B.
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`Elements of ’338 Patent
`1. Multi-transistor OLED Circuit
`The basic pixel circuit for active matrix OLED displays uses two transistors
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`and one capacitor to drive each pixel; it is often referred to as “2T-1C”. Additionally,
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`there are scan and data lines as well as a power supply line. In order to compensate
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`for variations in TFT characteristics, the ‘338 patent discloses a third transistor
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`(holding transistor) added to the circuit. In the disclosed operation, the writing step
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`allows current to flow through the driving transistor and switch transistor (and to a
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`lesser extent through the holding transistor) to charge the storage capacitor, thus
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`compensating for variations in TFT characteristics. The write current that flows
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`through the driving transistor and to the driving circuit can be called a “pull out”
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`current since that current flows out of the pixel circuit through the data line to the
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`off-matrix driver during the write period.
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`2.
`Low Resistance Electrodes
`Another inventive element of the ‘338 patent is lower-resistance conductors
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`for various interconnection lines for the active matrix OLED display to suppress
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`voltage drop. By decreasing the resistance of various interconnection lines,
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`performance will
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`improve. (Ex 1001 at 2:34-3:67.) The
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`lower-resistance
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`interconnections may “project from a surface of the transistor array substrate” i.e.
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`they may “extend beyond an outer surface of the layered structure upon which or
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`within which a transistor array is fabricated.” Ex. 1020 (Markman Order) at 15, 18.
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`Pixel electrodes are formed between the interconnection lines on the surface of the
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`transistor array substrate.
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`3.
`Color Display
`The inventive design of the ‘338 patent discloses a color active matrix OLED
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`display with red, green, and blue subpixels.
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`C.
`’338 Patent Claims
`This IPR challenges claims 1–3 and 5–13 of the ’338 patent. Independent
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`claim 1 recites:
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`A display panel comprising:
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`[a] a transistor array substrate which includes a plurality of pixels and
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`comprises a plurality of transistors for each pixel, each of the transistors
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`including a gate, a gate insulating film, a source, and a drain;
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`[b] a plurality of interconnections which are formed to project from a surface
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`of the transistor array substrate, and which are arrayed in parallel to each
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`other;
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`[c] a plurality of pixel electrodes for the plurality of pixels, respectively, the
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`pixel electrodes being arrayed along the interconnections between the
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`interconnections on the surface of the transistor array substrate;
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`[d] a plurality of light-emitting layers formed on the pixel electrodes,
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`respectively; and
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`[e] a counter electrode which is stacked on the light-emitting layers, wherein
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`said plurality of transistors for each pixel include a driving transistor, one of
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`the source and the drain of which is connected to the pixel electrode, a switch
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`transistor which makes a write current flow between the drain and the source
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`of the driving transistor, and a holding transistor which holds a voltage
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`between the gate and source of the driving transistor in a light emission period.
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`Further, claims 2–13 are dependent claims that depend directly or indirectly
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`from claim 1:
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`• Dependent claim 2 depends from claim 1. Claim 2 recites: “A panel according
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`to claim 1, wherein said plurality of interconnections include at least one of a
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`feed interconnection connected to the other of the source and the drain of at
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`least one of the driving transistors, a select interconnection which selects at
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`least one of the switch transistors, and a common interconnection connected
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`to the counter electrode.”
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`• Dependent claim 3 depends from claim 2. Claim 2 recites: “A panel according
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`to claim 2, wherein each of the light-emitting layers is formed between two of
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`the feed interconnection, the select interconnection, and the common
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`interconnection.”
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`• Dependent claim 5 depends from claim 1. Claim 5 recites: “A panel according
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`to claim 1, wherein said plurality of pixels include a red pixel, a green pixel,
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`and a blue pixel.”
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`• Dependent claim 6 depends from claim 5. Claim 6 recites: “A panel according
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`to claim 5, wherein said plurality of pixels comprises a plurality of sets each
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`including the red pixel, the green pixel, and the blue pixel arrayed in an
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`arbitrary order.”
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`• Dependent claim 7 depends from claim 1. Claim 7 recites: “A panel according
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`to claim 1, wherein at least one of the interconnections has a thickness of 1.31
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`to 6.00 μm.”
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`• Dependent claim 8 is a multiple dependent claim which depends in the
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`alternative from any of claims 1 or 2 to 7. Claim 8 recites: “A panel according
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`to any one of claims 1 or 2 to 7, wherein at least one of the interconnections
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`has a width of 7.45 to 44.00 μm.”
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`• Dependent claim 9 depends from claim 1. Claim 9 recites: “A panel according
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`to claim 1, wherein at least one of the interconnections has a resistivity of 2.1
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`to 9.6 μΩcm.”
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`• Dependent claim 10 depends from claim 1. Claim 10 recites: “A panel
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`according to claim 1, wherein said plurality of interconnections are formed
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`from a conductive layer that is different from a layer forming the source and
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`the drain of each of the transistors and a layer forming the gate of the
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`transistors.”
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`• Dependent claim 11 depends from claim 1. Claim 11 recites: “A panel
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`according to claim 1, wherein said plurality of interconnections are formed
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`from a conductive layer different from a layer forming the pixel electrodes.”
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`• Dependent claim 12 depends from claim 1. Claim 12 recites: “A panel
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`according to claim 1, wherein said plurality of interconnections are thicker
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`than a layer forming the source and the drain of each of the transistors and a
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`layer forming the gate of each of the transistors.”
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`• Dependent claim 13 depends from claim 1. Claim 13 recites: “A panel
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`according to claim 1, wherein said plurality of interconnections are thicker
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`than the pixel electrodes.”
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`D.
`’338 Patent Prosecution History
`The application that led to the ’338 patent, Application No. 11/235,579 (“’579
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`application”) was filed on September 26, 2005. The ’579 application claimed
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`priority to a Japanese patent application filed on September 29, 2004.
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`On July 27, 2006, the applicant submitted an Information Disclosure
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`Statement (IDS) disclosing, among other references, WO 2005/019314 (“Yamada
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`I”) and its U.S. national counterpart U.S. 2004/0256617 (“Yamada II”), after
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`Yamada I was cited in the International Search Report for the international
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`application counterpart to the ’338 patent. (Ex. 1002 at 584–488). Both Yamada
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`references were considered by the examiner, and a copy of Yamada I is contained in
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`the official file history of the ’338 patent. (Ex. 1002 at 451, 655–743.)
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`On July 23, 2007, the Patent Office mailed an office action containing a
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`restriction requirement, requiring an election of claims to proceed on. (Ex. 1002 at
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`458–462.) On August 21, 2007, the applicant responded with an election that
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`included pending claims 1–23. (Ex. 1002 at 455–456.)
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`On October 23, 2007, the Patent Office mailed a non-final rejection of certain
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`claims of the ’579 application under 35 U.S.C. §§ 102 and 103. (Ex. 1002 at 444–
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`449.) The examiner found that certain dependent claims including pending claim 2
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`would be allowable.
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`In response, on February 25, 2008, the applicant provided an amendment to
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`address the issues raised in the Patent Office action dated October 23, 2007. (Ex.
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`1002 at 425–437.) The amendment incorporated the limitations of pending claim 2
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`into claim 1 and made other changes “to make some minor grammatical
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`improvements and to correct some minor antecedent basis problems.” (Ex. 1002 at
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`436.)
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`The ’579 application was allowed on May 30, 2008. (Ex. 1002 at 330–333.)
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`Prior to paying the issue fee, on June 16, 2008, the applicant submitted an IDS
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`listing both the “Childs” reference (WO 03/079441) and the corresponding U.S.
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`patent family member (7,358,529) (“Childs II”). (Ex. 1002 at 193.) The reason for
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`submitting an IDS with these references at this time was that a Japanese patent Office
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`Action dated April 30, 2008 had cited Childs. (Ex. 1002 at 194–195.) A copy of
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`Childs is contained in the official file history of the ’338 patent. (Ex. 1002 at 253–
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`289.) The examiner considered both Childs references and the Japanese Office
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`Action that cited Childs. (Ex. 1002 at 193.)
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`On August 5, 2008, the applicant submitted an IDS listing both “Shirasaski
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`II” (Ex. 1007) (U.S. 2004/0165003) and its Japanese counterpart (JP 2004-258172).
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`(Ex. 1002 at 32–36.) The reason for submitting an IDS with these references at this
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`time was that the Japanese counterpart was cited in a Japanese Office Action dated
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`June 10, 2008 in prosecution of a related application. (Ex. 1002 at 34.) Both
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`Shirasaki II and its Japanese counterpart were considered by the examiner, and a
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`copy of the Japanese counterpart to Shirasaki II is contained in the official file
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`history of the ’338 patent. (Ex. 1002 at 30, 167–184.)
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`The issue fee was paid on August 29, 2008, and the ’579 application
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`subsequently issued as the ’338 patent on November 4, 2008.
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`III. Person of Ordinary Skill in The Art
`The earliest priority date for the ‘338 patent is September 29, 2004. Based on
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`the technology disclosed in the ‘338 patents, a person of ordinary skill in the art
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`(“POSITA”) would include someone who, at the time of the invention, had, (i) a
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`Bachelor’s degree in Electrical Engineering and/or Materials Science and
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`Engineering, Physics, or equivalent training, and (ii) approximately two years of
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`experience working in design and development related to active matrix-OLED
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`displays. Flasck Decl. ¶ 29. Lack of work experience could have been remedied by
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`additional education, and vice versa. Id. Such academic and industry experience
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`would be necessary to appreciate what was obvious and/or anticipated in the industry
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`and what a POSITA would have thought and understood at the time. Id.
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`IV. Claim Construction
`I understand that the Board does not construe any claim terms unnecessary to
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`resolve the parties’ dispute. Shenzhen Liown Electronics Co. v. Disney Enterprises,
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`Inc., IPR2015-01656, Paper 7 at 10 (Feb. 8, 2016). The district court provided a
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`construction of certain claim terms in its April 17, 2020 Claim Construction
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`Memorandum and Order (“Markman Order,” Ex. 1020). The district court’s
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`constructions are shown in the following table. These constructions have been
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`applied in this POR and are addressed in the invalidity arguments below. For other
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`terms not construed, this POR applies the plain and ordinary meaning to a POSITA.
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`The construction for “write current” was a construction that was proposed by
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`petitioner, and the construction for “the pixel electrodes being arrayed along the
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`interconnections between the interconnections on the surface of the transistor array
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`substrate” was agreed between the parties. (Ex. 1020 at 8, 18.)
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`Claim Terms
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`Court-Provided Constructions
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`“transistor array substrate”
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`“layered structure upon which or within which
`a transistor array is fabricated”
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`“project from a surface of the
`transistor array substrate”
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`“extend beyond an outer surface of the
`transistor array substrate”
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`“write current”
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`“pull-out current”
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`“the pixel electrodes being
`arrayed along the
`interconnections between the
`interconnections on the surface
`of the transistor array substrate”
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`“the pixel electrodes are arrayed along the
`interconnections and located between the
`interconnections, and the pixel electrodes are
`on the surface of the transistor array substrate”
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`V. Ground I: Obviousness Over Kobayashi and Shirasaki
`A. Overview of Kobayashi (Ex. 1003)2
`Kobayashi is a U.S. patent application publication which was published
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`October 31, 2002 and claims priority to Japanese patent applications filed April 20,
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`2001. (Ex. 1003 at 1.) It describes an active matrix electroluminescent display design
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`utilizing a two-transistor pixel circuit:
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`2 See Flasck Decl. ¶¶ 66–68.
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`The Petition relies on an embodiment of Kobayashi that is shown in Figure 7:
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`In this embodiment, “auxiliary wiring elements” 118 atop “partition walls”
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`120 are electrically connected to and help to provide electrical connection for the
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`transparent electrode 122.
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`B. Overview of Shirasaki (Ex. 1004) 3
`Shirasaski is a U.S. patent application publication which was published June
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`17, 2004 and claims priority to a Japanese patent application filed December 28,
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`2001. (Ex. 1004 at 1.) Like the ’338 patent, it was also assigned to Casio Computer
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`Co., Ltd., and it shares its first named inventor Tomoyuki Shirasaki with the ’338
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`patent. (Ex. 1001; Ex. 1004.)
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`Shirasaki discloses a three-transistor pixel circuit:
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`3 See Flasck Decl. ¶¶ 69–72.
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`This pixel circuit receives a “memory current” during a selection period and
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`then supplies a “display current” with value substantially equal to that memory
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`current during the non-selection period. (Ex. 1004 at 1, Abstract.)
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`This circuit from Shirasaki is cumulative to circuits in both the Yamada II and
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`Shirasaski II references that were disclosed during prosecution of the ’338 patent
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`and considered by the examiner, as explained above. For example, compare
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`Shirasaki, Figure 1 with Yamada II, Figure 1 (Ex. 2001); Shirasaski, Figure 5 with
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`Yamada II, Figure 6 (Ex. 2001); Shirasaki, Figure 1 with Shirasaki II, Figure 1 (Ex.
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`1007); and Shirasaski, Figure 5 with Shirasaki II, Figure 3 (Ex. 1007). Indeed, Dr.
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`Fontecchio acknowledged at his deposition that Yamada disclosed the same three-
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`transistor circuit as petitioner relies on from Shirasaki. (Ex. 2007 at 24:7–24.)
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`C.
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`Failure to Show Why One Skilled in the Art Would Be Motivated
`to Combine Kobayashi with Shirasaski as Proposed by Petitioner4
`Petitioner’s proposed combination is “to replace Kobayashi’s two-transistor
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`pixel circuit with Shirataki’s three-transistor pixel circuit.” (Petition at 53; Petition
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`at 54 (“By replacing a two-transistor pixel circuit (as in Kobayashi) with Shirasaki’s
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`three-transistor pixel circuit . . . .”), 55 (alleging “motivation to replace Kobayashi’s
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`two-transistor pixel circuit with Shirasaki’s three transistor pixel circuit”).) But a
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`POSITA would not be motivated to replace Kobayashi’s two-transistor pixel circuit
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`with Shirasaki’s three-transistor pixel circuit. And Petitioner’s arguments for why a
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`POSITA would be motivated to make this replacement are incorrect and
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`unsupported.
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`1. Kobayashi and Shirasaki are directed to different problems,
`and a POSITA with Kobayashi would not be motivated to
`look to Shirasaki as Petitioner proposes
`Kobayashi uses a two-transistor voltage-written pixel circuit in which voltage
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`signals from off-matrix drivers Ydr are written to the storage capacitors. (Ex. 1003,
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`Fig. 1.) Kobayashi does not need or use a holding transistor. (Ex. 2007 at 27:24–
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`28:2.) The problem Kobayashi identifies and purports to addresses is “non-
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`uniformity in electrode voltage in the screen plane …degrading the display quality.”
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`4 See Flasck Decl. ¶¶ 73–85.
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`(Ex. 1003, ¶ [0006].) Kobayashi teaches that this spatial non-uniformity is caused
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`by the high resistance of the transparent light-emission-side common electrode. This
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`high resistance causes variation in the voltages across the EL pixel elements. (Ex.
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`1003, ¶¶ [0005], [0006].) The common electrode voltage will be higher for pixels
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`near the edge of the display and lower (since the path is longer) towards the middle
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`of the display. Kobayashi asserts that this phenomenon will cause display spatial
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`non-uniformity. (Ex. 1003, ¶ [0006].) Petitioner and Dr. Fontecchio assert that
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`Kobayashi provides a conductive lattice wiring to raise the conductance of the
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`common electrode across the display and increase uniformity (Ex. 1018, Fontecchio
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`Decl. at ¶¶ 118, 122.)
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`The problem addressed by Kobayashi has nothing to do with the transistors in
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`the pixel circuit. Variation in transistor threshold voltage, channel resistance, ageing,
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`and temperature are not mentioned in Kobayashi. The solution Kobayashi supplies
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`to the high resistance of the common electrode is the use of a conductive grid or
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`lattice, as Dr. Fontecchio notes. (Ex. 1018 at ¶¶ 118, 122.) Dr. Fontecchio opines
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`that the Kobayashi solution is a conductive lattice under (not over) the common
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`electrode. (Ex. 1018 at ¶¶ 118, 122.) But a lattice is not a set of parallel conductors.
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`In contrast, the problem Shirasaki identifies and purports to address is aging
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`of the transistor characteristics which makes it “difficult to display images with a
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`desired luminance tone for long time periods.” (Ex. 1004, ¶ [0007].) Shirasaki’s
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`purported solution is to address the variation of the transistor channel resistances and
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`threshold voltages. (Ex. 1004, ¶¶ [0007], ], [0011], [0094].) This is done by using a
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`three-transistor pixel circuit and using current writing signals as opposed to voltage
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`writing signals. Both the purported solution and approach of Shirasaki involves
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`current-written pixel circuits, and not voltage-written circuits as in Kobayashi.
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`Thus, the problems and approaches addressed by Kobayashi and Shirasaki are
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`fundamentally different. Kobayashi addresses the spatial non-uniformity of a display
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`for a voltage-written circuit. Shirasaki addresses the temporal (deterioration over
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`time) of a display for a current-written circuit. Since Kobayashi and Shirasaki are
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`concerned with different problems and approaches, a POSITA would not be
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`motivated to combine.
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`2.
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`Petitioner’s arguments that Kobayashi and Shirasaki both
`disclose OLEDs or TFTs are insufficient to show motivation
`to combine
`Petitioner argues that “Kobayashi and Shirasaki are both directed to
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`improvements in AMOLED display panels and disclose TFT pixel circuits for use
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`in AMOLED display panels.” (Petition at 53.) But that is insufficient to show
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`motivation to combine. That the references disclose common circuitry components
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`like a pixel circuit or transistor, does not show that a POSITA faced with
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`Kobayashi’s two-transistor circuit would be motivated to look to Shirasaki’s three-
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`transistor circuit and perform a wholesale substitution as Petitioner proposes.
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`Petitioner fails to address the differences in proposed solutions between Kobayashi
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`and Shirasaki or the differences between a voltage-written approach versus current-
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`written approach. A POSITA would readily recognize these differences and
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`therefore would not be motivated to pursue Petitioner’s proposed combination.
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`Further, that Kobayashi and Shirasaki disclose similar technology (at a high
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`level of generality) or similar components is not a reason for a POSITA to combine
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`them in the manner Petitioner asserts. That is not an adequate rationale or motivation
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`for a POSITA to replace Kobayashi’s two-transistor pixel circuit with Shirasaki’s
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`three-transistor pixel circuit. 5
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`3.
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`Petitioner’s other arguments fail and mischaracterize what
`Shirasaki actually teaches or suggests.
`Petitioner also asserts that “Shirasaki provides an express teaching,
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`suggestion, or motivation to a POSA to replace Kobayashi’s two-transistor pixel
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`5 See Ossia, Inc. v. Energous Corp., PGR2016-00023, Paper 20 at 26 (PTAB Nov.
`29, 2016) (“The fact that two references disclose similar technology is not sufficient
`to demonstrate a reason why an ordinarily skilled artisan would have combined
`them.”); Ancestry.Com DNA, LLC v. DNA Genotek Inc., IPR2016 01152, Paper 11
`at 8 (PTAB Nov. 23, 2016) (“The mere fact that both Birnboim and O’Donovan are
`in the same field of endeavor falls short of an adequate rationale. The same field of
`endeavor analysis is merely the jumping-off point in reaching the determination of
`whether a claimed invention is obvious.”).
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`circuit with Shirasaki’s three-transistor pixel circuit.” This is incorrect and
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`mischaracterizes what Shirasaki actually teaches or suggests.
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`Shirasaki attempts to improve on the background art, which it describes as a
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`circuit with two TFTs made of amorphous silicon (a-Si). (Ex. 1004, ¶ [0003].)
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`Shirasaki notes that the background art uses “a voltage driving method” in which the
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`luminance is controlled by a signal voltage on the transistor. (Ex. 1004, ¶ [0006].)
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`Shirasaki also notes that for such circuits, it is “impossible to apply amorphous
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`silicon transistors,” which are advantageous because they “can be fabricated at a
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`relatively low cost.” (Ex. 1004, ¶ [0008].)
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`Shirasaki also discloses in the background devices that are not voltage driven.
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`(Ex. 1004, ¶ [0009].) It notes that such devices are made up of four or more
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`transistors in one pixel. (Ex. 1004, ¶ [0009].) Shirasaki describes the drawbacks of
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`adding additional transistors and teaches against doing so. (Ex. 1004, ¶ [0009] (“If
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`these transistors are formed on a substrate, the upper surface is made uneven by the
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`thickness of these transistors.”) (“