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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG DISPLAY CO., LTD.,
`Petitioner,
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`v.
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`SOLAS OLED, LTD.,
`Patent Owner.
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`Case IPR2020-00320
`Patent No. 7,446,338
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`PETITIONER’S SUPPLEMENTAL PRE-INSTITUTION BRIEF
`ADDRESSING DISTRICT COURT CLAIM CONSTRUCTION ORDER
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`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
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`1013
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`1014
`1015
`1016
`1017
`1018
`1019
`1020
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`LIST OF EXHIBITS
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`Description
`U.S. Patent No. 7,446,338 (the “’338 patent”)
`File History for U.S. Patent No. 7,446,338
`U.S. Patent Application Pub. No. 2002/0158835 (“Kobayashi”)
`U.S. Patent Application Pub. No. 2004/0113873 (“Shirasaki”)
`International Publication No. WO 03/079441 (“Childs”)
`European Patent Application No. EP 1331666 (“Yamazaki”)
`U.S. Patent Application Pub. No. 2004/0165003 (“Shirasaki II”)
`Japanese Patent Publication No. 2004-258172
`U.S. Patent Application Pub. No. 2003/0151637 (“Nakamura”)
`International Publication No. WO 03/079442 (“Hector”)
`International Publication No. WO 03/079449 (“Young”)
`Tsujimura, Takatoshi. OLED Display Fundamentals and
`Applications: Fundamentals and Applications, John Wiley &
`Sons, Incorporated, 2012. (“Tsujimura”)
`Crawford, Gregory P. Flexible flat panel display technology. Vol.
`3. West Sussex: Wiley, 2005. (“Crawford”)
`U.S. Patent Application Pub. No. 2003/0127657 (“Park”)
`U.S. Patent No. 7,498,733 (“Shimoda”)
`U.S. Patent Application Pub. No. 2002/0000576 (“Inukai”)
`U.S. Patent Application Pub. No. 2002/0009538 (“Arai”)
`Declaration of Dr. Adam Fontecchio
`Curriculum Vitae of Adam Fontecchio
`Claim Construction Memorandum & Order, Solas OLED Ltd. v.
`Samsung Display Co., Ltd. et al., 2:19-cv-00152-JRG (E.D. Tex.
`Apr. 17, 2020)
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`i
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`Pursuant to the Board’s authorization of April 27, 2020, Petitioner submits
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`this supplemental brief. A district court recently construed certain terms of U.S.
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`Patent No. 7,446,338 (“the ’338 patent”). In accordance with 37 C.F.R. § 42.100 and
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`the November 2019 Consolidated Trial Practice Guide (at 46–48), Petitioner submits
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`the district court’s April 17, 2020 Claim Construction Memorandum and Order as
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`Exhibit 1020. The court’s constructions are consistent with the grounds in the
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`Petition and further support institution of inter partes review of the ’338 patent.
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`I.
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`The Petition establishes obviousness under any construction of “write
`current,” including the district court’s construction.
`The first term addressed in the court’s claim construction order relates to the
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`claimed “switch transistor which makes a write current flow between the drain and
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`the source of the driving transistor.” Ex. 1020, 18–23. The Petition did not request a
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`particular construction for “write current,” because the prior art shows the claimed
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`“switch transistor which makes a write current” under any interpretation—including
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`the district court’s construction of “write current” as “pull-out current.” Id. Both
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`grounds of the Petition rely on Shirasaki, a prior art patent publication by the same
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`lead inventor as the ’338 patent, that had disclosed the exact same three-transistor
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`structure as is described and claimed in the ’338 patent. See, e.g., Pet., 52–53, 78–
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`79. This structure includes the claimed “switch transistor,” as well as the claimed
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`“driving” and “holding” transistors, as illustrated in the figures repeatedly presented
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`in the Petition and explained by Dr. Fontecchio in his expert declaration:
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`1
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`Pet., 52–53, 78–79; see, e.g., Ex. 1018, ¶¶ [0135], [0204]. As Dr. Fontecchio further
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`explained in the cited portions of his declaration (see Pet., 52, 78):
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`Shirasaki’s figures illustrate the same three-transistor pixel circuit that was
`later used by Casio again in the figures for the ’338 patent. I note that
`transistor 11 in Fig. 5B of Shirasaki corresponds to “switch transistor 21”
`in Figure 2 of the ’338 patent, transistor 12 in Figure 5B of Shirasaki
`corresponds to “driving transistor” 23 in Figure 2 of the ’338 patent, and
`transistor 10 in Shirasaki corresponds to “holding transistor” 22 in Figure 2.
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`Ex. 1018, ¶¶ [0135], [0204] (emphasis added).
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`As the Petition explains, Shirasaki specifically teaches replacing a typical
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`two-transistor circuit controlled by voltage (such as those disclosed in Kobayashi
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`and Childs) with the three-transistor circuit taught by Shirasaki, which is controlled
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`by a “memory current.” Pet., 54–55. In Shirasaki’s three-transistor circuit, control
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`of the current flowing to the OLED “is thus performed by the current values, not by
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`voltage values.” Pet., 54–55 (quoting Ex. 1004, ¶ [0018]); Ex. 1018, ¶ 138.
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`2
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`Thus, to the extent that the Board applies the “pull-out current” construction
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`(which Samsung Display advanced in the district court subsequent to filing this IPR),
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`the limitation is met by the Shirasaki pixel circuit as advanced in the Petition. As
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`illustrated by annotated Fig. 5A of Shirasaki below, the “memory current” α that
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`flows in Shirasaki’s three-transistor circuit when “transistor 11” (the claimed
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`“switch transistor”) “is turned on,” Ex. 1004, ¶ [0072], [0084], is the same as “pull-
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`out current” A shown in annotated Fig. 2 of the ’338 patent (Ex. 1001, 15:34–37):
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`Shirasaki, Fig. 5A (annotated)
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`’338 Patent, Fig. 2 (annotated).
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`As Shirasaki confirms, this memory current flows “between the source and drain of
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`the transistor 12” (the claimed “driving transistor”). Ex. 1004, ¶ [0092].
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`Patent Owner’s Preliminary Response (“POPR”) never argues that Shirasaki
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`fails to disclose a “switch transistor” or a “write current” as claimed in the ’338
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`patent—and as construed by Petitioner and the district court. Nor could it plausibly
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`do so, because the circuit disclosed in Shirasaki is identical to the claimed circuit of
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`the ’338 patent. Instead, Patent Owner attempts to argue that: (1) the Petition does
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`not rely on Shirasaki to disclose the claimed “switch transistor which makes a write
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`current flow,” see, e.g., POPR, 23 (“Shirasaki is used … to show only a supposed
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`‘[] holding transistor’”); and (2) “there is nothing new provided by Shirasaki[] . . .
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`that was not timely disclosed to and considered by, the examiner before the
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`challenged claims were allowed,’” id., 13. Neither argument is persuasive.
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`Solas’s first argument is incorrect. The Petition consistently states (over a
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`dozen times) that, in both proposed grounds, Shirasaki is relied upon to replace the
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`two-transistor pixel circuits in Kobayashi or Childs with Shirasaki’s three-transistor
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`pixel circuit, rather than merely to add a third holding transistor:
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`However, this “holding transistor” limitation would have been obvious based
`on Shirasaki, which disclosed replacing a two-transistor pixel circuit (as in
`Childs) with a three-transistor pixel circuit that includes each of the claimed
`“driving transistor,” “switching transistor,” and “holding transistor.”
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`Pet., 78 (emphasis added); see also id., 8, 38, 52, 53, 54, 55, 56, 57, 63, 79, 80, 81.
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`Indeed, the POPR itself elsewhere recognizes this:
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`[T]he obviousness combination that Samsung alleges satisfies the elements of
`claim 1 does not contain this two-transistor pixel circuit. Rather, it
`“replac[es]” that circuit “with Shirasaki’s three-transistor pixel circuit.”
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`POPR, 20–21 (emphasis added) (citing Pet., 54). And this replacement was not only
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`recommended by Shirasaki—Kobayashi and Childs each contemplated replacing
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`their pixel circuit structures with a substitute (such as Shirasaki’s). Pet., 57, 81–82.
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`Regarding the second argument, while Patent Owner is correct that other prior
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`art references illustrating the claimed three-transistor circuit structure were
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`submitted in IDSs (and marked as considered by the Examiner), there was no
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`submission of Shirasaki (and its discussion of a “memory current” and the
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`advantages of three-transistor circuit over two-transistor circuits, as discussed
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`above). Moreover, there is no indication that the Examiner ever substantively
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`considered the circuit structure contained in those other references.
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`II. Each of the Petition’s grounds discloses a “transistor array substrate.”
`The district court construed “transistor array substrate” as a “layered structure
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`upon which or within which a transistor array is fabricated.” Ex. 1020, 15. Initially,
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`Patent Owner is incorrect that the Childs–Shirasaki combination “fails” under
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`Petitioner’s proposed construction, POPR, 27; the Petition addressed in detail how
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`Childs discloses this limitation under Petitioner’s proposed construction, Pet., 71–
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`75. Additionally, under the district court’s construction (which Patent Owner
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`advanced throughout the Markman briefing and hearing 1) there can also be no
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`dispute that Kobayashi’s layers 101–116 (Pet., 39–43) and Childs’s “circuit substrate
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`100” (Pet., 64–67) are each a “transistor array substrate.”
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`1 The district court declined to adopt Patent Owner’s “agreement” to Petitioner’s
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`construction, POPR, 27, in what it termed Patent Owner’s “late-breaking” filing made
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`the same night as the POPR. See Ex. 1020, 8 n.2, n.3.
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`5
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`Date: May 4, 2020
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`COVINGTON & BURLING LLP
`One CityCenter
`850 Tenth Street, NW
`Washington, DC 20001
`(202) 662-6000
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`3000 El Camino Real
`5 Palo Alto Square, 10th Floor
`Palo Alto, CA 94306
`(650) 632-4700
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`Respectfully submitted,
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`By /David A. Garr/
`David A. Garr
`Registration No.: 74,932
`Grant D. Johnson
` Registration No.: 69,915
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`Peter P. Chen
`Registration No.: 39,631
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`Attorneys for Petitioner
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. § 42.6, I hereby certify that on this 4th day of May, 2020, the
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`foregoing Petitioner’s Supplemental Pre-Institution Brief was served via electronic
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`mail, by agreement of the parties, on the following counsel of record for Patent
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`Owner.
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`Russ August & Kabat
`12424 Wilshire Blvd., 12th Fl.
`Los Angeles, CA 90025
`Neil A. Rubin (Reg. No. 67,030)
`Reza Mirzaie (Reg. No. 69,138)
`Kent Shum (Reg. No. 61,117)
`Philip X. Wang (Reg. No. 74,621)
`nrubin@raklaw.com
`rmirzaie@raklaw.com
`kshum@raklaw.com
`pwang@raklaw.com
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`Date: May 4, 2020
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`/David A. Garr/
`David A. Garr, Esq.
`Registration No.: 74,932
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