`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`FLEX LOGIX TECHNOLOGIES, INC.
`Petitioner
`
`v.
`
`VENKAT KONDA
`Patent Owner
`
`____________________
`
`Patent No. 8,269,523
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,269,523
`
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`TABLE OF CONTENTS
`
`
`INTRODUCTION ...............................................................................1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ..............................2
`A. Real Parties-in-Interest ................................................................2
`B. Related Matters ..........................................................................2
`1.
`Litigations and PTAB Proceedings .......................................2
`2.
`Related Applications ..........................................................3
`3.
`Concurrently-filed petition ..................................................3
`C. Counsel and Service Information ..................................................4
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)................................4
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.204(a) ..................4
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED ..................4
`A. Claims for Which Review is Requested .........................................4
`B.
`Statutory Grounds of Challenge ....................................................5
`VI. LEVEL OF ORDINARY SKILL IN THE ART .......................................6
`VII. OVERVIEW OF THE ’523 PATENT ....................................................6
`A.
`Prosecution History.....................................................................8
`VIII. CLAIM CONSTRUCTION ..................................................................9
`IX. DETAILED EXPLANATION OF GROUNDS...................................... 10
`A. Ground 1: Wong Anticipates Claims 1 and 20-22 .......................... 10
`1.
`Claim 1 .......................................................................... 10
`2.
`Claim 20......................................................................... 87
`3.
`Claim 21......................................................................... 88
`4.
`Claim 22......................................................................... 89
`B. Ground 2: Wong Renders Obvious Claims 15-18, 32, and 47 .......... 90
`1.
`Claim 15......................................................................... 90
`
`i
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`Claim 16......................................................................... 93
`2.
`Claim 17......................................................................... 95
`3.
`Claim 18......................................................................... 98
`4.
`Claim 32....................................................................... 101
`5.
`Claim 47....................................................................... 101
`6.
`THE BOARD SHOULD NOT EXERCISE DISCRETION UNDER
`§325(D) TO DENY THE PETITION ................................................. 105
`XI. CONCLUSION ............................................................................... 106
`
`
`X.
`
`
`
`
`
`
`
`ii
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`LIST OF EXHIBITS
`
`
`Ex. 1001 U.S. Patent No. 8,269,523
`Ex. 1002 Declaration of Jacob Baker, Ph.D., P.E.
`Ex. 1003 Curriculum Vitae of Jacob Baker, Ph.D., P.E.
`Ex. 1004 File History of U.S. Patent No. 8,269,523
`Ex. 1005 PCT Publication No. WO2008/147928
`Ex. 1006 U.S. Patent No. 10,003,553
`Ex. 1007 Body of PCT Application No. PCT/US08/64605 As Filed (“the ’605
`PCT”)
`Ex. 1008 U.S. Patent No. 6,940,308 (“Wong”)
`Ex. 1009
`(RESERVED)
`Ex. 1010
`Ex. 1011
`Ex. 1012
`Ex. 1013
`Ex. 1014
`Ex. 1015
`Ex. 1016
`Ex. 1017
`Ex. 1018
`Ex. 1019
`Ex. 1020
`
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`(RESERVED)
`
`iii
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`Ex. 1021
`(RESERVED)
`Ex. 1022
`(RESERVED)
`Ex. 1023
`(RESERVED)
`Ex. 1024
`(RESERVED)
`Ex. 1025
`(RESERVED)
`Ex. 1026 File History of U.S. Provisional Application No. 60/940,394
`Ex. 1027
`(RESERVED)
`Ex. 1028
`(RESERVED)
`Ex. 1029
`(RESERVED)
`Ex. 1030
`(RESERVED)
`Ex. 1031
`(RESERVED)
`Ex. 1032
`(RESERVED)
`Ex. 1033
`(RESERVED)
`Ex. 1034
`(RESERVED)
`Ex. 1035
`(RESERVED)
`Ex. 1036
`(RESERVED)
`Ex. 1037
`(RESERVED)
`Ex. 1038
`(RESERVED)
`Ex. 1039
`(RESERVED)
`Ex. 1040 U.S. Patent No. 3,358,269 (“Benes”)
`Ex. 1041
`(RESERVED)
`
`iv
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`Ex. 1042
`(RESERVED)
`Ex. 1043 U.S. Patent No. 5,847,577 (“Trimberger”)
`Ex. 1044 U.S. Patent No. 7,558,967 (“Wong-967”)
`Ex. 1045 U.S. Patent No. 4,874,971 (“Fletcher”)
`Ex. 1046 U.S. Patent No. 10,050,904
`
`v
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`I.
`
`INTRODUCTION
`Flex Logix Technologies, Inc. (“Petitioner”) requests inter partes review
`
`(“IPR”) of claims 1, 15-18, 20-22, 32, and 47 (“the challenged claims”) of U.S.
`
`Patent No. 8,269,523 (“the ’523 patent”) (Ex. 1001), which, according to PTO
`
`records, is assigned to Venkat Konda (“Patent Owner” or “PO”). For the reasons set
`
`forth in this Petition, the challenged claims should be found unpatentable and
`
`canceled.
`
`As explained below (infra Section VII.B), during prosecution the Examiner
`
`rejected various claims as being anticipated by U.S. Patent No. 6,940,308 to Wong
`
`(“Wong”) (Ex. 1008), PO (then the applicant) amended the claims in response, and
`
`after an interview, the Examiner mailed a Notice of Allowance. While it is not clear
`
`what PO and the Examiner discussed during the interview (because the interview
`
`summary mailed by the Examiner merely reproduces the entirety of amended claim
`
`1), it appears that the Examiner incorrectly relied on a misrepresentation by PO
`
`regarding the limitations added in the amendment. (Infra Section IX.A.1(k)
`
`(discussing PO’s statement that in Wong, “[i]t is clear as [Wong’s routing] network
`
`is scaled up, only columns are increasing” (Ex. 1004, 63 (applicant’s foregoing
`
`statement regarding Wong) (emphasis added).) As explained below regarding
`
`limitation 1(k), Wong is not limited to only adding more columns and explicitly
`
`
`
`
`1
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`discloses scaling up the network by adding both columns and rows (i.e. both
`
`vertical and horizontal scaling). (Infra Section IX.A.1(k); Ex. 1008, 13:33-49.)
`
`In any event, the Examiner’s statement of reasons for allowance indicates that
`
`certain limitations of claim 1 (the ones indicated as limitations 1(j) and 1(k) in this
`
`Petition) are the only possible distinction over Wong. (Infra Section VII.B; Ex.
`
`1004, 28 (Notice of Allowance).) As explained in detail below—and supported by
`
`previously-absent expert testimony that would have helped the Examiner recognize
`
`the inaccuracy of the PO’s misrepresentation—the Examiner simply erred in
`
`allowing the claims over Wong.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. Real Parties-in-Interest
`Petitioner identifies Flex Logix Technologies, Inc. as the real party-in-
`
`interest.
`
`B. Related Matters
`Litigations and PTAB Proceedings
`1.
`PO has asserted the ’523 patent against Petitioner in Konda Technologies Inc.
`
`v. Flex Logix Technologies, Inc., No. 5:18-cv-07581 (N.D. Cal.). PO has also
`
`asserted U.S. Patent Nos. 8,898,611 (“the ’611 patent”), 9,529,958 (“the ’958
`
`patent”), 10,050,904 (“the ’904 patent”), 10,003,553 (“the ’553 patent”) in the
`
`
`
`
`2
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`foregoing district court litigation. The ’553 patent is the subject of pending instituted
`
`post-grant review (PGR) proceedings PGR2019-00037 and PGR2019-00042.
`
`Another PGR petition (in PGR2019-00040) regarding the ’553 patent was
`
`previously denied.
`
`Related Applications
`2.
`The ’523 patent issued from U.S. Application No. 12/601,275 (“the ’275
`
`application”), which is a national stage entry of International Application
`
`PCT/US2008/064605 (“the ’605 PCT”), and claims priority to U.S. Provisional
`
`Application No. 60/940,394 (“the ’394 provisional”) filed May 25, 2007. 1,2 Pending
`
`U.S. Application No. 16/202,067 claims priority to the ’275 application, according
`
`to the PTO PAIR database.
`
`Concurrently-filed petition
`3.
`Petitioner is concurrently filing two additional petitions for IPR of certain
`
`
`
` 1
`
` Petitioner does not concede that the national stage was properly entered or that the
`
`’523 patent properly issued based on such national stage entry. Petitioner reserves
`
`the right to assert such issues in other forums. (See, e.g., Ex. 1004, 1-2, 148-159.)
`
`2 The’605 PCT and the ’394 provisional are submitted as Exhibits 1007 and 1026,
`
`respectively.
`
`
`
`
`3
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`claims of the ’523 patent.
`
`C. Counsel and Service Information
`Lead counsel is Naveen Modi (Reg. No. 46,224), and Backup counsel are (1)
`
`Joseph E. Palys (Reg. No. 46,508), (2) Paul M. Anderson (Reg. No. 39,896), and (3)
`
`Arvind Jairam (Reg. No. 62,759). Service information is Paul Hastings LLP, 875
`
`15th St. N.W., Washington, D.C., 20005, Tel.: 202.551.1700, Fax: 202.551.1705,
`
`email: PH-FlexLogix-Konda-IPR@paulhastings.com. Petitioner consents to
`
`electronic service.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The PTO is authorized to charge all fees due at any time during this
`
`proceeding, including filing fees, to Deposit Account No. 50-2613.
`
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.204(a)
`Petitioner certifies that the ’523 patent is available for review and Petitioner
`
`is not barred or estopped from requesting review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED
`A. Claims for Which Review is Requested
`Petitioner respectfully requests review of claims 1, 15-18, 20-22, 32, and 47
`
`(“challenged claims”) of the ’523 patent, and cancellation of these claims as
`
`unpatentable.
`
`
`
`
`4
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Statutory Grounds of Challenge
`B.
`The challenged claims should be canceled as unpatentable on the following
`
`grounds:
`
`Ground 1: Claims 1 and 20-22 are unpatentable under pre-AIA 35 U.S.C. §
`
`102(b) as being anticipated by Wong.
`
`Ground 2: Claims 15-18, 32, and 47 are unpatentable under pre-AIA 35
`
`U.S.C. § 103 as obvious over Wong.
`
`The ’523 patent issued from the ’275 application, which claims priority to the
`
`’394 provisional filed May 25, 2007 and is a national stage entry of the ’605 PCT,
`
`which was filed May 22, 2008 and published as International Publication No.
`
`WO2008/147928 (Ex. 1005). Wong issued on September 6, 2005. Therefore, even
`
`if the ’523 patent is entitled to the May 25, 2007 priority date of the ’394 provisional,
`
`Wong qualifies as prior art under § 102(b). 3 (See Ex. 1002, ¶¶40-45 (overview of
`
`Wong).)4
`
`
`
` 3
`
` Petitioner demonstrates that the ’523 patent is not entitled to the priority date of the
`
`’394 provisional in the concurrently-filed IPR petitions.
`
`4 Petitioner submits the declaration of Dr. R. Jacob Baker (Ex. 1002), an expert in
`
`the field of the ’523 patent. (Ex. 1002, ¶¶1-19; Ex. 1003.)
`
`
`
`
`5
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) at the time of the alleged
`
`invention of the ’523 patent would have had a master’s degree in electrical
`
`engineering or a similar field, and at least two to three years of experience with
`
`integrated circuits and networks. (Ex. 1002, ¶¶18-19.) More education can
`
`supplement practical experience and vice versa. (Id.)
`
`VII. OVERVIEW OF THE ’523 PATENT
`The ’523 patent is entitled “VLSI Layouts of Fully Connected Generalized
`
`Networks.” (Ex. 1001, Title.) The ’523 patent acknowledges that multi-stage
`
`hierarchical networks were known and used in many applications, including field-
`
`programmable gate arrays (FPGAs). (Id., 2:25-27, 2:62-67; Ex. 1002, ¶¶31-38.)
`
`The ’523 patent contends that prior art network layouts were “inefficient and
`
`complicated” (Ex. 1001. 2:28-30, 3:1-6) and alleges to disclose layouts of networks
`
`that use horizontal and vertical cross links between switches in succeeding stages.
`
`(Id., 3:21-29.)
`
`In addition to inlet and outlet links on the periphery of the network, the ’523
`
`patent discloses middle links that provide connections between the switches in the
`
`different stages of the network. “The middle links which connect switches in the
`
`same row in two successive middle stages are called hereinafter straight middle
`
`
`
`
`6
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`links; and the middle links which connect switches in different rows in two
`
`successive middle stages are called hereinafter cross middle links.” (Ex. 1001,
`
`9:45-49 (emphasis added).) Examples of straight and cross middle links are
`
`highlighted in figure 1B below.
`
`(Id., FIG. 1B (excerpt, annotated); Ex. 1002, ¶38.)
`
`As explained below (infra Section IX), the above features were all known in
`
`the prior art. (See Ex. 1002, ¶¶46-170; see also id., ¶¶20-30 (describing the state of
`
`
`
`the art).)
`
`
`
`
`7
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Prosecution History
`A.
`During prosecution of the ’275 application, the Examiner issued an Office
`
`Action rejecting claim 1 (the only independent claim) and other claims as being
`
`anticipated by Wong. (Ex. 1004, 90-117 (Office Action dated February 7, 2012).)
`
`PO amended claim 1 (and other claims) to add certain limitations. (Id., 60-80
`
`(Amendment dated April 30, 2012).)
`
`PO and the Examiner conducted an interview, but it is unclear what was
`
`discussed as the interview summary merely reproduces the entirety of claim 1 of the
`
`’523 patent. (Id., 57.) After the interview PO filed a supplemental amendment “[t]o
`
`correct mistakes [with the format of the claims and not identifying the cancelled
`
`claim], and the Examiner mailed a Notice of Allowance stating that:
`
`the cited prior arts fail to teach said all straight links are
`connecting from switches in each said sub-integrated circuit
`block are connecting to switches in the same said sub-integrated
`circuit block; and said all cross links are connecting as either
`vertical or horizontal links between switches in two different said
`sub-integrated circuit blocks which are either placed vertically
`above or below, or placed horizontally to the left or to the right,
`each said plurality of sub-integrated circuit blocks comprising
`same number of said [stages] and said switches in each said
`stage, regardless of the size of said two-dimensional grid so that
`
`
`
`
`8
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`each said plurality of sub-integrated circuit block with its
`corresponding said stages and said switches in each stage is
`replicable in both vertical direction or horizontal direction of said
`two-dimensional grid, as required by amended claim 1.
`
`(Id., 28.) The foregoing limitations are referred to as limitations 1(j) and 1(k) in this
`
`Petition, and are discussed below in Sections IX.A.1(j)-(k).
`
`VIII. CLAIM CONSTRUCTION
`In an IPR, claims are construed in accordance with the ordinary and customary
`
`meaning of such claims as understood by one of ordinary skill in the art and the
`
`prosecution history pertaining to the patent. 37 C.F.R. § 42.200(b). In particular,
`
`claim terms are generally given their “ordinary and customary meaning,” that is, “the
`
`meaning that the term would have to a POSITA in question at the time of the
`
`invention, i.e., as the effective filing date of the patent application.” Phillips v. AWH
`
`Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). The Board only construes
`
`the claims when necessary to resolve the underlying controversy. Toyota Motor
`
`Corp. v. Cellport Systems, Inc., IPR2015-00633, Paper 11 at 16 (August 14, 2015).
`
`Petitioner submits that for purposes of this proceeding, no term of the challenged
`
`
`
`
`9
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`claims requires construction. 5 (Ex. 1002, ¶39.)
`
`IX. DETAILED EXPLANATION OF GROUNDS
`A. Ground 1: Wong Anticipates Claims 1 and 20-22
`Claim 1
`1.
`“An integrated circuit device comprising”
`a)
`To the extent the preamble is limiting, Wong discloses the limitations therein.
`
`(Ex. 1002, ¶¶50-52.) For instance, Wong discloses an FPGA (field-programmable
`
`gate array) integrated circuit (“an integrated circuit device”). (Id., ¶50.) Wong
`
`discloses that “[t]he present invention relates to integrated circuit interconnections
`
`and, in particular, to the interconnection architecture of FPGA (Field Programmable
`
`
`
` 5
`
` Petitioner reserves all rights to raise claim construction and other arguments in
`
`district court as relevant and necessary to those proceedings. For example, Petitioner
`
`has not raised all challenges to the ’523 patent in this petition, including invalidity
`
`under 35 U.S.C. § 112, and a comparison of the claims to any accused products in
`
`litigation may raise controversies that need to be resolved through claim construction
`
`that are not presented here given the similarities between the references and the
`
`patent.
`
`
`
`
`
`
`10
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`Gate Array) integrated circuits.” (Ex. 1008, 1:14-17; see also id., 1:18-21, 1:59-61;
`
`Ex. 1002, ¶¶50-51.)
`
`Figures 13A and 13B of Wong illustrate exemplary floorplan layouts of
`
`FPGAs (“integrated circuit devices”). (Ex. 1008, 3:7-10; 13:19-22, 13:36-38, FIGs.
`
`13A, 13B.)
`
`(Ex. 1008, FIG. 13A; Ex. 1002, ¶52.)
`
`
`
`
`11
`
`
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`(Ex. 1008, FIG. 13B; Ex. 1002, ¶52; see also infra Sections IX.A.1(b)-(k) regarding
`
`the remaining elements of this claim.)
`
`b)
`
`“a plurality of sub-integrated circuit blocks and a
`routing network”
`Wong discloses this limitation. (Ex. 1002, ¶¶53-63.) For instance, Wong
`
`discloses an integrated circuit (e.g., an FPGA) that includes a plurality of logic cells
`
`that are coupled to a programmable network. (Ex. 1008, 1:59-61.)
`
`
`
`
`12
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`A POSITA would have understood that a “sub-integrated circuit block” in the
`
`context of the ’523 patent corresponds to a row of switches in a network such as that
`
`illustrated in figure 1B in addition to the configurable logic that is coupled to that
`
`row. (Ex. 1001, 15:22-24 (“Some of the key aspects of the current invention are
`
`discussed. 1) All the switches in one row of the multi-stage network 100B are
`
`implemented in a single block.”), 13:38-42; Ex. 1002, ¶54.) For example, with
`
`respect to figure 1C of the ’523 patent, which shows the “blocks” (i.e. sub-integrated
`
`circuit blocks) of figure 1B, the ’523 patent states that “in each block, in addition to
`
`the switches there may be Configurable Logic Blocks (CLB) or any arbitrary digital
`
`circuit (hereinafter ‘sub-integrated circuit block’) depending on the applications in
`
`different embodiments.” (Ex. 1001, 13:38-42.)
`
`Therefore, in the context of the ’523 patent a “sub-integrated circuit block”
`
`includes the switches corresponding to a single row (which figure 1C of the ’523
`
`patent shows as a single “block”) with the addition of “Configurable Logic Blocks
`
`(CLB) or any arbitrary digital circuit.” (Ex. 1002, ¶55.) The following
`
`demonstratives supplied in Dr. Baker’s declaration illustrate a “sub-integrated circuit
`
`block” in figures 1B and 1C of the ’523 patent in the context of how a POSITA
`
`would have understood claim 1. (Id.) As is apparent from the discussion below,
`
`
`
`
`13
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`such an understanding of a “sub-integrated circuit block” is consistent with the other
`
`claim limitations. (Infra Sections IX.A.1(c)-(k); Ex. 1002, ¶55.)
`
`(Ex. 1001, FIG. 1C (excerpt, annotated); Ex. 1002, ¶55.)
`
`
`
`
`
`(Ex. 1001, FIG. 1B (excerpt, annotated), Ex. 1002, ¶55.)
`
`In the annotated excerpts of figures 1B and 1C above, each “sub-integrated
`
`circuit block” (red box) includes all of the switches in a row and a “Configurable
`
`Logic Block[] (CLB) or any arbitrary digital circuit” (green “CLB” box). (Ex. 1002,
`
`¶56.)
`
`
`
`
`14
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Wong discloses a plurality of “sub-integrated circuit blocks.” (Ex. 1002, ¶57.)
`
`The folded network shown below in figure 4C of Wong is similar to the folded
`
`network shown in figure 1B of the ’523 patent. (Id.)
`
`(Ex. 1008, FIG. 4C; Ex. 1002, ¶57.)
`
`
`
`
`
`
`15
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`(Ex. 1001, FIG. 1B; Ex. 1002, ¶57.)
`
`Figures 13A and 13B of Wong illustrate exemplary floorplan layouts of
`
`FPGAs that use a Benes network topology such as that shown in figure 4C. (Ex.
`
`1008, 3:7-10, 13:19-22, FIG. 13A (reproduced below); Ex. 1002, ¶58.) Thus, figure
`
`13A of Wong illustrates the network of figure 4C of Wong with the addition of logic
`
`cells 81. (Ex. 1002, ¶58.)
`
`
`
`
`16
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`(Ex. 1008, FIG. 13A; Ex. 1002, ¶58.)
`
`As shown in figure 13A of Wong, each row includes a plurality of switches
`
`82 and a pair of logic cells 81. (Ex. 1002, ¶59.) Similarly, figure 13B shows a multi-
`
`column embodiment that includes two instantiations of the layout shown in figure
`
`
`
`13A. (Ex. 1008, 3:7-10, 13:36-38; Ex. 1002, ¶59.) In each of the two columns
`17
`
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`shown in figure 13B, each row includes a plurality of switches 82, 83 and a pair of
`
`logic cells 81. (Ex. 1002, ¶59.)
`
`
`
`(Ex. 1008, FIG. 13B; Ex. 1002, ¶59.)
`
`As depicted in figures 13A and 13B, logic cells 81 are included in the FPGA
`
`along with switch cells 82 and 83, where the switch cells make up the “routing
`
`network” that provides the interconnect in the FPGA. (Ex. 1008, 13:22-23, 13:36-
`
`38; Ex. 1002, ¶60.) Wong discloses that the logic cells are configurable and can be
`
`
`
`
`18
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`programmed to perform desired functions. (Ex. 1008, 3:22-24, 7:34-38; Ex. 1002,
`
`¶¶60-62.)
`
`Therefore, Wong discloses “a plurality of sub-integrated circuit blocks and a
`
`routing network” as recited in claim element 1(b). (Ex. 1002, ¶63.) Wong discloses
`
`a plurality of rows of switches and their corresponding logic cells (“plurality of sub-
`
`integrated circuit blocks”), where the switches provide the desired interconnects for
`
`the network (“routing network”) in the FPGA (“integrated circuit device”). (Id.)
`
`Annotated figures 13A and 13B below show Wong’s plurality of sub-
`
`integrated circuit blocks and corresponding routing network. (Id., ¶63.)
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶63.)
`
`
`
`
`19
`
`
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`(Ex. 1008, FIG. 13B (annotated); Ex. 1002, ¶63.)
`
`c)
`
`“Said each plurality of sub-integrated circuit blocks
`comprising a plurality of inlet links and a plurality of
`outlet links”
`Wong discloses this limitation. (Ex. 1002, ¶¶64-68.) For instance, Wong
`
`discloses that the logic cells 81 included in the “sub-integrated circuit blocks”
`
`include output pins (“plurality of outlet links”), which are coupled to inputs of the
`
`switches 82 in the first stage of the network. (Id., ¶64.) The logic cells 81 also
`
`
`
`
`20
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`include input pins (“plurality of inlet links”) that are coupled to outputs of the
`
`switches 82 in the first stage of the network inputs. (Id.)
`
`For example, as shown in figure 13A of Wong (annotated below), each of the
`
`two logic cells in each of the “sub-integrated circuit blocks” includes an output pin
`
`(“plurality of outlet links”) that is coupled to an input of one of the switches 82 in
`
`the first stage of the network. (Ex. 1008, FIG. 13A, 13:24-26; Ex. 1002, ¶65.)
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶65.)
`
`
`
`
`
`
`21
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Each of the two logic cells in each sub-integrated circuit block also includes
`
`an input pin (“plurality of inlet links”) that is coupled to an output of one of the
`
`switches 82 in the first stage of the network. (Ex. 1008, FIG. 13A, 13:24-26.)
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶66.)
`
`Because figure 13B of Wong includes two instantiations of the layout shown
`
`in figure 13A of Wong, figure 13B also discloses the claimed “inlet links” and “outlet
`
`links” in the same manner described with respect to figure 13A. (Ex. 1008, 13:36-
`
`
`
`
`
`
`22
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`38; Ex. 1002, ¶67.) The inlet links and outlet links shown in figure 13A of Wong
`
`above correspond to inlet links and outlet links included in embodiments in the ’523
`
`patent. (Ex. 1002, ¶67.) Examples of such inlet links and outlet links are illustrated
`
`in an excerpt from figure 1B of the ’523 patent annotated below. (Ex. 1001, 12:6-
`
`19, FIG. 1B; Ex. 1002, ¶67.)
`
`
`
`(Ex. 1001, FIG. 1B (excerpt, annotated); Ex. 1002, ¶67.)
`
`The inlet links (IL1, IL2, … IL8) and outlet links (OL1, OL2, … OL8) provide
`
`connections between the configurable logic blocks and the first stage of switches in
`
`the ’523 patent in the same manner that the inlet links and outlet links shown above
`
`in Wong connect the logic cells with the first stage of switches in Wong’s network.
`
`(Ex. 1002, ¶68; Ex. 1001, 8:44-52, 12:6-8.)
`
`
`
`
`23
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`d)
`
`“Said routing network comprising of a plurality of
`stages y, in each said sub-integrated circuit block,
`starting from the lowest stage of 1 to the highest stage
`of y, where y ≥ 1; and”
`Wong discloses this limitation. (Ex. 1002, ¶¶69-71.) For example, within the
`
`routing network of figure 13A of Wong, each sub-integrated circuit block includes
`
`three stages (each switch 82 corresponds to a “stage”), and therefore Wong discloses
`
`the “routing network comprising of a plurality of stages y, in each said sub-integrated
`
`circuit block, starting from the lowest stage of 1 to the highest stage of y, where y ≥
`
`1.” (Id., ¶69.)
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶69.)
`24
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Similarly, as shown in figure 13B of Wong (annotated below), each sub-
`
`integrated circuit block includes four stages (each switch 82, 83 corresponds to a
`
`“stage”). (Ex. 1002, ¶70.)
`
`(Ex. 1008, FIG. 13B (annotated); Ex. 1002, ¶70.)
`
`Wong’s disclosure of the sub-integrated circuit blocks including a plurality of
`
`stages aligns with the teachings of the ’523 patent. (Ex. 1002, ¶71.) For example,
`
`the ’523 patent states that figure 1A has nine stages (Ex. 1001, 3:51-57), whereas
`
`
`
`figure 1B has five stages (id., 3:58-64).
`25
`
`
`
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`(Ex. 1001, FIG. 1A (excerpt, annotated); Ex. 1002, ¶71.)
`
`
`
`
`
`(Ex. 1001, FIG. 1B (excerpt, annotated); Ex. 1002, ¶71.)
`
`e)
`
`“Said routing network comprising a plurality of
`switches of size dxd, where d≥2, in each said stage and
`each said switch of size dxd having d inlet links and d
`outlet links; and”
`Wong discloses this feature. (Ex. 1002, ¶¶72-83.) According to limitation
`
`1(e), each stage of the network includes a plurality of switches, each of which has at
`
`least two inlet links (d inputs) and the same number of outlet links (d outputs).
`
`
`
`
`26
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`Notably, in the relevant art of integrated circuits, “a switch of size d x d” in the
`
`context of “each said switch of size dxd having d inlet links and d outlet links” would
`
`have informed a POSITA about the input/output configuration of the switch, and not
`
`the actual area (i.e., physical size) of the switch. (Ex. 1002, ¶72.) In other words, a
`
`POSITA would have understood that “size” in the context of this claim term does
`
`not refer to the physical measurements of the switch, but instead refers to the number
`
`of inputs and outputs. (Id.) A POSITA would have understood that a dxd switch is
`
`a symmetrical switch in that it has the same number of inputs and outputs. (Id., ¶73
`
`(citing Ex. 1006, 49:1-3).)
`
`As explained below, Wong discloses that in the embodiments shown in figures
`
`13A and 13B each stage includes a 4x4 switch that in turn can be made up of multiple
`
`2x2 switches. (Ex. 1002, ¶74.) Therefore, Wong discloses “a plurality of switches
`
`of size d x d, where d ≥ 2, in each said stage and each said switch of size d x d having
`
`d inlet links and d outlet links.” (Id.)
`
`
`
`
`27
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Each stage in the sub-integrated circuit blocks shown in figures 13A and 13B
`
`includes a switch. (Id., ¶75.) For example, as shown below in figure 13A, each of
`
`stages 1-3 includes a switch 82. (Ex. 1008, 13:22-24; Ex. 1002, ¶75.)
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶75.)
`
`
`
`
`
`
`28
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`
`Similarly, each stage in each sub-integrated circuit block in figure 13B
`
`includes switches 82 and 83. (Ex. 1008, 13:22-24, 13:33-38; Ex. 1002, ¶76.)
`
`(Ex. 1008, FIG. 13B (annotated); Ex. 1002, ¶76.)
`As shown in figure 13A, each switch 82 has four inputs and four outputs. (Ex.
`
`1008, FIG. 13A; Ex. 1002, ¶77.) While the switches 83 added in figure 13B only
`
`show two inputs and outputs, a POSITA would have understood that there are also
`
`
`
`
`
`
`29
`
`

`

`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`two additional inputs and outputs corresponding to the primary input/output (I/O) of
`
`the FPGA, which are not shown in figure 13B, but are shown in figure 13A. (Ex.
`
`1008, FIGs. 13A-13B, 13:42-43 (“As before, each column’s top-level inputs and
`
`outputs are connected to the primary I/O of the FPGA.”); Ex. 1002, ¶77.)
`
`Wong discloses that the 4x4 switches shown in figures 13A and 13B can be
`
`made up of sets of 2x2 switches such as those shown in figures 2A and 2B. (Ex.
`
`1008, 5:4-6 (“[t]he building block of the described Benes network is the 2x2 (2 input,
`
`2 output) switch 20, having operations illustrated in FIGS. 2A and 2B.”).) As further
`
`disclosed by Wong, “[t]hese 2x2 switches are connected in a specific topology to
`
`build a Benes network. (Id., 5:26-27.) Such a Benes network is shown in figure 4B,
`
`where figures 13A and 13B are also Benes networks that build on the disclosure
`
`corresponding to figure 4B in Wong. (Id., 7:6-8, 8:65-9-1, 13:19-22, 13:33-38; Ex.
`
`1002, ¶78.)
`
`
`
`
`30
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`
`
`(Ex. 1008, FIGs. 2A, 2B; Ex. 1002, ¶78.)
`Therefore, a POSITA would have understood that all of the switches 82, 83
`
`shown in figures 13A and 13B can be 4x4 switches or a set of two 2x2 switches
`
`(such as is shown in figure 4B). (Ex. 1008, FIGs. 13A, 13B, 4B.) As shown in the
`
`annotated versions of figure 13A of Wong below, each switch cell 82 in each of
`
`stages 1-3 can include two 2x2 switches, where each 2x2 switch has two inputs (“d
`
`inlet links”) and two outputs (“d outlet links”). (Ex. 1002, ¶78.)
`
`
`
`
`31
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶79.)
`
`
`
`
`
`
`32
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶79.)
`
`
`
`
`
`
`33
`
`

`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,269,523
`
`(Ex. 1008, FIG. 13A (annotated); Ex. 1002, ¶79.)
`
`As disclosed by Wong, figure 13B includes two instantiations of figure 13A
`
`with the addition of another stage of switches 83. (Ex. 1008, 3:7-10, 13:36-38; Ex.
`
`1002, ¶80.) Therefore, like the network of figure 13A, each switch in each of the
`
`
`
`
`
`
`34
`
`

`

`Petition for Inter Parte