United States Patent
`
`[19]
`
`[11] Patent Number:
`
`4,874,971
`
`
`
`
`
` Fletcher [45] Date of Patent: Oct. 17, 1989
`
`[54] EDGE-SENSITIVE DYNAMIC SWITCH
`
`[56]
`
`[75]
`
`Inventor:
`
`Thomas D. Fletcher, Orem, Utah
`
`[73] Assignee: North American Philips Corporation,
`Signetics Division, Sunnyvale, Calif.
`
`[21] App]. No.: 180,425
`
`[22] Filed:
`
`Apr. 8, 1988
`
`[63]
`
`Related U.S. Application Data
`_
`_
`,
`Connnuation-m-part of Ser. N°‘ 934’753’ N°V‘ 25’
`1986’ Pat. No' 4’740’717'
`'
`[51]
`Int. Cl.‘ ............................................. H03K 5/153
`
`[52] U.S. C1. ............................... 307/605; 307/573;
`307/576; 307/594; 307/517
`[58] Field of Search ............... 307/443, 573, 575, 576,
`307/585, 597, 601, 605, 266, 261, 517, 518, 594,
`273; 328/114
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3/1977 Stewart _
`4,039,858
`FOREIGN PATENT DOCUMENTS
`
`0242721 12/1985 Japan ................................... 307/576
`Primary Examiner—John Zazworsky
`Attorney, Agent, or Firm—R. Meetin; D. Treacy; T.
`Briody
`
`[57]
`
`ABSTRACT
`
`An edge-sensitive dynamic switch center around a
`transmission gate (16) formed with a pair of comple-
`mentary FET’S (QN and QP) coupled together in paral-
`lel between a pair of nodes (1 and 2). The signals at the
`two nodes vary between a low voltage level and a high
`voltage level. An inverter (17) is coupled between the
`gate electrodes of the FET’s. A delay element (18) is
`coupled between one of the nodes and one of the gate
`electrodes. Due to the transmission delays through the
`delay element and the inverter, the switch turns off with
`a controlled delay.
`
`11 Claims, 5 Drawing Sheets
`
`
`
`Page 1 of 12
`
`'
`
`FLEX LOGIX EXHIBIT 1045
`
`FLEX LOGIX EXHIBIT 1045
`
`Page 1 of 12
`
`

`

`US. Patent
`
`Oct. 17,1989
`
`Sheet 1 of 6
`
`4,874,971
`
`
`
`Page 2 of 12
`
`Page 2 of 12
`
`

`

`US. Patent
`
`Oct. 17, 1989
`
`Sheet 2 of 6
`
`4,874,971
`
`
`
`Page 3 of 12
`
`Page 3 of 12
`
`

`

`' US. Patent
`
`Oct. 17,1989
`
`Sheet 3 of6
`
`4,874,971
`
`
`
`ON
`
`0N
`
`QN CONDITION
`
`Qp CONDITION
`
`"._....-_-_--______ _.._---- . -. --- .-_
`
`rII
`
`III
`
`TlME—-D-
`
`Page 4 Of 12
`
`Page 4 of 12
`
`

`

`US. Patent
`
`0&.17,1989
`
`Sheet 4 of 6
`
`'
`
`4,874,971
`
`
` INTER -
`MEDIATE
`
`LOGIC
`SECTION
`
`
`
`
`Page 5 of 12
`
`Page 5 of 12
`
`

`

`US. Patent
`
`Oct. 17, 1989"
`
`"
`
`'
`
`.
`
`‘Sheét 5 01‘6
`
`4,874,971
`
`(PRIOR ART)
`
`VOLTAGE———-——>
`VOLTAGE
`
` VOLTAGEH <r-r
`l_< [-
`
`VOLTAGE——-—>
`
`<I I
`
`Page 6 of 12
`
`Page 6 of 12
`
`

`

`US. Patent
`
`Oct. 17, 1989
`
`Sheet 6 of6
`
`4,874,971
`
`Fig. 6
`
`
`
`Page 7 of 12
`
`Page 7 of 12
`
`

`

`4,874,971
`
`1
`
`EDGE-SENSITIVE DYNAMIC SWITCH
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`2
`signal is present. An inverter responsive to a third Signal
`at a third node coupled to the gate electrode of one of
`the FET’s provides a substantially inverse fourth signal
`to the gate electrode of the other FET.
`A critical part of the switch is a delay element that
`causes the third signal to continually follow the first
`signal, either directly or inversely, by a specified time
`delay. The delay element is typically an inverting cir-
`cuit coupled between the first and third nodes. The
`delay element may, however, be a non-inverting buffer
`circuit.
`The switch turns off in response to a voltage transi-
`tion of the first signal in one particular direction. By
`virtue of the transmission delays through the delay
`element and the (first-mentioned) inverter, one of the
`FET’s turns on briefly'when the first signal makes such
`a transition. This delays the time at which the switch
`turns off by a controllable amount.
`There are a variety of uses for the present switch. It
`can replace a capacitor in some applications because the
`delayed tum-off produces a capacitive-like current
`pulse. For the same reason, the switch can be used in
`creating dynamic hysteresis. The switch can also be
`employed to double clock frequencies or make a latch
`into an edge-sensitive flip-flop.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block/circuit diagram of a prior art transi-
`tion detector.
`FIGS. 2a, 2b, 2c, and 2d are block/circuit diagrams of
`four general variations of an edge-sensitive dynamic
`switch in accordance with the invention.
`FIGS. 2e and 2}" are circuit diagrams for implementa-
`tions of the main delay element in FIGS. 2a—2d.
`FIGS. 3a and 3b are respective timing diagrams for
`the versions of the dynamic switch shown in FIGS. 2a
`and 2b.
`FIG. 4 is a block/circuit diagram for a portion of a
`digital IC that employs an input inverting device having
`dynamic hysteresis.
`FIGS. 51: and 5b are timing diagrams pertinent to the
`digital IC in FIG. 4.
`FIG. 6 is a circuit diagram showing how the present
`switch is employed in a preferred embodiment of the
`input inverting device of FIG. 4.
`'
`Like reference symbols are employed in the drawings
`and in the description of the preferred embodiments to
`represent the same or very similar item or items. In the
`drawings, each N—channel FET has an arrow pointing
`towards its channel. Each P-channel FET has an arrow
`pointing away from its channel. All of the FET’s shown
`in the drawings discussed below are enhancement-mode
`insulated-gate devices.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIGS. 2a—2d illustrate four general ways for imple-
`menting the dynamic switch of the invention. Each of
`the implementations centers around a transmission gate
`16 consisting of complementary FET’s QN and Q}: con-
`nected in parallel between nodes 1 and 2 in the same
`manner that FET’s Q0N and Q0}: are arranged in the
`prior art circuit mentioned above. N-channel FET QN
`has a positive threshold voltage VTN which is typically
`in the vicinity of 1 volt. P-channel FET Qp has a nega-
`tive threshold voltage VT}: that is usually around ——1
`volt.
`
`This is a continuation-in—part of U.S. patent applica-
`tion Ser. No. 934,753, filed November 25, 1986 now
`U.S. Pat. No. 4,740,717.
`
`FIELD OF USE
`
`This invention relates to an electronic circuitry em-
`ploying transmission gates formed with complementary
`field-effect transistors (FET’s).
`BACKGROUND ART
`
`A useful building block for a semiconductor inte-
`grated circuit (IC) is a transmission gate consisting of a
`pair of opposite-polarity FET’s connected in parallel.
`Depending on the signals that control the gate, it can be
`placed in a conductive condition across the full range of
`the IC power supply voltage. This is highly desirable in
`many applications.
`Referring to FIG. 1, it illustrates how a transmission
`gate 10 is used in a transition detector as disclosed in
`U.S. Pat. No. 4,039,858. Gate 10 is composed of an
`N-channel insulated-gate FET Q0N and a P-channel
`insulated-gate FET Q0p. One source/drain element of
`FET Q0Nis connected to one source/drain element of
`FET QOP by way of a node 1 at which a gate input
`signal V1 is received. The other source/drain element of
`FET QON is connected to the other source/drain ele-
`ment of FET Q01: via a node 2 at which a gate output
`signal V2 is supplied.
`An inverter 11 is connected between the gate elec-
`trodes. In response to a signal V3 provided from a node
`3 connected to the QON gate electrode, inverter 11
`supplies an inverse signal V4 to the Q01: gate electrode.
`Signal V2 is provided to a flip-flop 12 that supplies a
`signal V5 representing the flip-flop state. Signal V2 con-
`trols flip-flop 12 when transmission gate 10 is conduc-
`tive. An EXCLUSIVE NOR gate 13 provides a detec-
`tion signal V5 as the EXCLUSIVE NOR of signals V1
`and V5. The final component of the transition detector
`is an inverter 14 that generates signal V3 by inverting
`signal V5.
`The transition detector operates as follows. Both of
`FET’s QON and Q01: are normally off so that gate 10 is
`non-conductive. Signal V5 is normally at a high voltage.
`When signal V1 makes a voltage transition in one direc-
`tion, the signal transmission delays through the detector
`enable gate 10 to turn on briefly. This causes a pulse
`indicative of the transition to appear in signal V5. A
`similar pulse occurs in signal V5 when signal V1 later
`makes a transition in the opposite direction.
`
`GENERAL DISCLOSURE OF THE INVENTION
`
`The present invention centers around an electronic
`circuit in which the transmission delays through circuit
`components employed with a transmission gate enable
`the circuit to function as an edge-sensitive dynamic
`switch with a controlled turn-off delay. The transmis-
`sion gate is. formed with a pair of complementary
`FET’s, each having a first source/drain element, a sec-
`ond source/drain element, and a gate electrode. The
`first
`source/drain elements are coupled together
`through a first node at which a first signal is present.
`The second source/drain elements are similarly coupled
`together through a second node at which a second
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`65
`
`Page 8 of 12
`
`Page 8 of 12
`
`

`

`5
`
`15
`
`20
`
`25
`
`30
`
`35
`
`3
`Signals V1 and V2 are again respectively present at
`nodes 1 and 2. During normal operation, signal V1 tra-
`verses a voltage range extending from a fixed low sup-
`ply voltage VLL to a fixed high supply voltage VHH.
`Signal V2 traverses the same voltage range. Letting
`Vps represent the differential power supply voltage
`VHH—VLL, Vps exceeds both VTN and lVTPl- For
`example, Vps is typically about 5 volts.
`An inverter 17 operating in response to signal V3
`supplied from node 3 to the gate electrode of one of 10
`FET’s QN and Qp provides substantially inverse signal
`V4 to the gate electrode of the other FET. Inverter 17
`has its input and output respectively connected to the
`QN gate electrode and the Qp electrode in the embodi-
`ments of FIGS. 2a and 2b. The inverter connections are
`reversed in the implementations of FIGS. 2c and 2d.
`A main delay element 18 responsive to signal V1
`generates signal V3 in such a way that changes in signal
`V3 follow changes in signal V1 either directly or in-
`versely. In FIGS. 20 and 2c, delay element 18 is an
`inverting circuit whose input and output are respec-
`tively connected to nodes 1 and 3. Signal V3 thus in-
`versely follows signal V1 in these two versions of the
`switch. In FIGS. 2b and 2d, element 18 is a non-invert-
`ing buffer circuit having its input and output respec-
`tively connected to nodes 1 and 3 so that signal V3
`directly follows signal V1.
`Components 17 and 18 are usually implemented in
`such a manner that signals V3 and V4 vary across the
`entire VPS voltage range. For example, inverter 17 may
`be a conventional CMOS-type inverter consisting of a
`pair of complementary FET’s connected in series be-
`tween supply lines that receive voltages VLL and VHH.
`Element 18 in FIGS. 2a and 20 can be formed in the
`same way or as an odd number (e.g., 3, 5, .
`.
`. ) of such
`inverters comected in series. FIG. 2e illustrates the case
`in which element 18 consists of three serially connected ,
`CMOS-type inverters 181, 182, and 183. Element 18 in '
`FIGS. 2b and 2d can be implemented as an even number
`(e.g., 2, 4, .
`.
`. ) of conventional CMOS-type inverters
`connected in series. FIG. 2f shows the case in which
`element 18 consists of two serially connected CMOS-
`type inverters 184 and 185.
`The present switch, as represented by the condition
`of gate 16 and thus by the conditions of FET’s QN and
`Qp, turns off with a controlled time delay in response to
`a transition of signal V1 in a particular voltage direction.
`Referring to FIGS. 3a and 3b, they depict timing dia-
`grams helpful in understanding the operation of the
`switch. FIG. 3a applies specifically to The implementa-
`tion of FIG. 2a. FIG 3b applies to FIG. 2b. The voltage
`curves representing signal V1 are shown in thicker line
`in FIGS. 3a and 3b to help distinguish signal V1 from
`signals V3 and V4.
`the approximate
`TA and r3 respectively represent
`transmission delays through components 18 and 17 mea-
`sured from threshold to threshold. That is, TA is the
`difference between the time at which signal V1 passes
`the threshold voltage for element 18 and the later time
`at which signal V3 passes the same voltage in response
`to the change in signal V1. 7'B is similarly the time period
`that signal V4 is delayed relative to signal V3 measured
`at the threshold voltage for inverter 17. The total trans-
`mission delay from signal V1 to signal V4 is ”+73.
`The threshold voltages for components 17 and 18
`and, consequently, the transmission delay measurement
`points are typically about halfway between voltages
`VLL and VHH when components 17 and 18 are imple-
`
`40
`
`4
`mented using the CMOS-type circuitry described
`above. This case is shown in FIGS. 30 and 3b.
`Turning specifically to FIG. 3a, assume that signal
`V1 is initially at low voltage VLL. V3 is initially at high
`voltage V1111 due to the inversion provided by element
`18 in FIG. 2a. FET QN is turned on since the V3—-V1
`voltage difference equals power supply voltage Vp5 and
`is therefore greater than N-channel threshold VTN.
`Gate 16 is turned on. Signal V2 is at VLL. Signal V4 is
`also at VLL. Because signal V4 is at the same voltage as
`signals V1 and V2, FET Qp is turned off.
`V1 is now raised to V1111. V2 starts following V1 up-
`ward. V3—V1 drops towards —VPS so as to turn off
`FET QN. Delay 714 through element 18 extends the time
`during which FET QNis turned on. This assists V2 in its
`upward rise. FET QN turns off when V3—V1 drops
`below VTN.
`V4 also follows V1 upward. Due to delays 7,4 and TB
`through components 18 and 17, there is a short period of
`time before FET QN turns off during which the
`V4—-V1 voltage difference temporarily drops below
`P-channel threshold VTp. That is, V4 trails V1 by more
`than IVTPI . This allows FET Qp to turn on briefly. The
`dynamic turn on of FET Qp usually enables V2 to rise
`all the way up to V3”.
`FET Qp turns off when V4 has risen enough that
`V4—V1 is greater than VTP. With FET Qp now turned
`off, gate 16 is turned off. The result is that the time at
`which gate 16 turns off in response to a low-to-high
`voltage transition in signal V1 is delayed by an amount
`dependent on delays TA and 7'3.
`After gate 16 turns off node 2 is effectively discon-
`nected from node 1. The variation in the V2 voltage, as
`indicated by the dotted portion of the V2 curve in FIG.
`3a, is now determined by whatever further circuitry is
`connected to node 2. At a later time, V1 is returned to
`VLL. FET QNturns back on to reactivate gate 16. If not
`already set at VLL by the further circuitry connected to
`node 2, V2 returns to VLL. This completes the cycle.
`The situation is similar with the embodiment shown
`in FIG. 2b except that the roles of FET’s QN and Q1: are
`largely reversed so that the switch has a delayed tum-
`off when V1 makes a high-to-low voltage transition.
`With reference to FIG. 3b, FET Qp is turned on during
`the time that V1 is at VHH. Gate 16 is conductive. When
`V1 is reduced to VLL, FET QNturns on briefly to delay
`the time at which gate 16 turns off by an amount deter-
`mined by delays ‘rA and TB.
`The implementations of FIGS. 2c and 2d respectively
`operate in the same way as those of FIGS. 2a and 2b
`with the voltage polarities and roles of FET’s QN and
`Qp reversed.
`When a fast IC interacts with the outside world, the
`voltages on the internal supply lines often “bounce” up
`and down. The bounce can cause the IC to operate
`improperly when it responds to an input signal having a
`slowly changing voltage. The problem usually becomes
`more serious as the IC speed increases. FIGS. 4, 50, 5b,
`and 6 illustrate an example of how the present dynamic
`switch is employed in creating dynamic hysteresis to
`prevent supply line bounce from causing improper IC
`operation.
`Beginning with FIG. 4, it shows a portion of a digital
`IC 20 that receives supply voltages VHH and VLL at
`respective supply terminals (or pads) TH and TL. IC 20
`produces a circuit output voltage V0 at an output termi-
`nal Toin response to a circuit input voltage V[received
`at an input terminal T]. A capacitor C0 (real or para-
`
`4,874,971
`
`45
`
`50
`
`55
`
`65
`
`Page 9 of 12
`
`Page 9 of 12
`
`

`

`4,874,971
`
`6
`temporarily raises VN enough to turn FET Q3N on for
`a brief period. FET Q31) remains off. Rp/N drops below
`its quiescent level. This reduces VT until circuit 28 re-
`duces VN sufficiently to turn FET Q3N back off.
`Largely the reverse occurs when VA drops below
`VLL+VS. FET QlN turns off and FET Q11: turns on,
`causing device 22 to switch from its low logic state to its
`high logic state. VB goes from VLL up to VHH. In re-
`sponse to this VB change, circuit 28 temporarily pro-
`vides Vp at a sufficiently low voltage to turn FET Q31:
`on for a short time. FET Q3N stays off. Consequently,
`Rp/N rises above its quiescent value so as to increase VT.
`When circuit 28 subsequently raises Vp to turn off FET
`Q3p, VT drops back down.
`Now, look at what happens in IC 20 if input V1
`changes very slowly. Assume (for example) that logic
`section 26 provides a voltage inversion so that Vcis the
`inverse of V3.
`First consider how IC 20 would operate if (as in the
`prior art) dynamic hysteresis circuit 24 were absent.
`This case is represented by the voltage variations shown
`in FIG. 5a. Assume that V] is initially low. Also assume
`that VL and VH are respectively at VLL and VH3. VA is
`then low, causing V3 to be at VH3. Vc is low so that
`FET Q2N is turned off and FET Q2}: is turned on. VD
`and V0 are both at VHH. Capacitor Co is charged to a
`high level.
`As V1 rises slowly, VA tracks V1 closely. Inductance
`L1 does not have any significant effect. At a time t1, VA
`starts to go above VLL+V3. This causes V3 to drop
`rapidly to VLL. Vc goes high to turn FET Q2N on and
`FET Q21: off. VD drops rapidly to VLL. At a time t2
`depending on the transmission delays through compo-
`nents 26 and 27, capacitor C0 starts discharging to the
`VLL supply by way of a path through elements Lo,
`Q2N, and LL to pull V0 rapidly down to VLL.
`The current flowing through this path varies with
`time in a non-linear manner. Since the voltage across an
`inductor is the inductance times the time rate of change
`of current flowing through the inductor, a positive
`voltage builds up across inductance LL, reaching a
`maximum at a time t3. A positive (or upward going)
`spike in VL thereby occurs at t3 as shown in FIG. 5a.
`The VL spike at t3 is the “first” spike in a set of timewise
`contiguous pairs of alternating apikes that die out
`quickly, of which only the first pair of alternating spikes
`are actually shown in FIG. 5a.
`The VL spike at t3 is often so high that VA—VL tem-
`porarily drops below threshold VT. See shaded area 29
`in FIG. 5a. Inverter 23 then makes a pair of rapid
`changes in logic state at approximately a time t4, caus-
`ing V3 to spike upwards. In turn, the VB spike causes a
`positive V0 spike to occur at a time t5.
`The same situation arises if V; drops slowly, except
`that the polarities and supply lines are reversed. The
`first spike is a negative VH spike that results from the
`rapid charging of capacitor Co by way of a path
`through elements LH, Q2p, and L0.
`The V0 spikes and the corresponding spikes in VB,
`Vc, and VD can be disastrous. They could cause a cir-
`cuit (such as a flip-flop) responsive to V0, VB, VC, or
`V3 to be set at a wrong state.
`Circuit 24 enables IC 20 to avoid unwanted changes
`of state that would otherwise occur as a result of supply
`line bounce. FIG. 5b, which is an analogous timing
`diagram to FIG. Sa for the case in which circuit 24 is .
`present, is helpful in showing how this is accomplished.
`
`10
`
`15
`
`20
`
`25
`
`3O
`
`35
`
`45
`
`50
`
`55
`
`65
`
`5
`sitic) is connected between terminal To and the VLL
`supply.
`The illustrated portion of IC 20 is a very fast logic
`circuit powered by high and low internal supply volt-
`ages VH and VL provided on lines connected respec-
`tively to terminals TH and TL. Responsive to an internal
`input voltage VA supplied on a line connected to termi-
`nal T1, the logic circuit produces an internal output
`voltage VD on a line connected to terminal To. Parasitic
`inductances LL, L11, L1, and Lo are respectively associ-
`ated with the lines carrying voltages VL, V3, V4, VD.
`The logic circuit consists of (a) an input inverting
`device 22 formed with an input inverter 23 and a dy-
`namic hysteresis circuit 24 that together generate a
`voltage VB inverse to voltage VA, (b) an intermediate
`logic section 26 that operates on voltage VB and possi-
`bly on other input voltages (not shown) to produce a
`voltage Vc at a value that is logically the same as or
`inverse to voltage VB, and (c) an output inverter 27 that
`generates voltage VD as the inverse of voltage Vc.
`Inverter 23 is a conventional CMOS-type inverter
`formed with complementary input FET’s QlNand le.
`Inverter 27 is similarly formed with complementry
`output FET’s Q2N and Q2p.
`Dynamic hysteresis circuit 24 consists of a control
`circuit 28 powered by supply voltages V]; and VL, an
`N-channel FET Q3N, and a P-channel FET Q3p. In
`response to voltage V}; control circuit 28 supplies thre-
`shold-control voltages VN and V}: to the respective
`gates of FET’s Q31v and Q3p. FET QSN is “in parallel”
`with FET QlN. FET Q31: is similarly in parallel with
`FET le.
`Circuit 24 provides dynamic hysteresis for the thresh-
`old voltage VT of device 22. More particularly, the
`threshold voltage for an inverter formed with comple-
`mentary FET’s depends on the ratio Rp/N of the P-
`channel width to the N-channel width (at constant
`channel length). This means the widths of the channel
`areas that are conducting at the threshold point. The
`threshold voltage increases when RP/N increases and
`vice versa.
`
`FET’s Q3N and Q3p are normally off or at so low
`conductive levels as to be effectively off. Accordingly,
`the quiescent value of Rp/N for device 22 is simply the
`Q1}: channel width divided by the QlN channel width
`since FET’s QlN and Q1}: are both conducting at the
`threshold point, one in the midst of turning on and the
`other in the midst of turning off. If FET Q3N is on but
`FET Q3p is off, the N-channel width for device 22
`increases since FET’s Q3N and QIN are in parallel.
`RP/N for device 22 is therefore less than its quiescent
`value. In like manner, RP/N for device 22 is greater than
`the quiescent value when FET Q3p is on but FET Q3N
`is off.
`With the foregoing in mind, device 22 operates as
`follows. FET’s Q3N and Q3,» are initially off. Supply
`voltages V1, and V]; are initially at (or very near) re-
`spective substantially constant levels VLL and VHH.
`Under these conditions, threshold VTis at a quiescent
`value Vs determined by the quiescent Rp/N of device
`22. When the difference VA—VL passes VT, device 22
`changes state.
`If VA rises above VLL+V5, FET QlN turns on and
`FET le turns off. Device 22 as represented by the
`conductive conditions of FET’s QlN and Q1}: switches
`from a high logic state to a low logic state, causing V3
`to go from a high level near V3}; to a low level near
`VLL. Responsive to this change in V3, control circuit 28
`
`Page 10 of 12
`
`Page 10 of 12
`
`

`

`4,874,971
`
`8
`gradually turns off, positive charge from the VH line
`now flows through FET’s Q4}: and Q81: to the Q3N gate
`to raise VN further. This continues for the entire time
`needed for inverter 36 to raise VG up to VHH. At some
`point during the charging of the Q3N gate, FET Q3N
`turns on.
`
`7
`The initial conditions for the case shown in FIG. 5b
`are the same as those for FIG. 50. As V1 rises slowly,
`VA follows closely. When VA passes VLL+VS at time
`t1, VB drops rapidly to VLL. In response, hysteresis
`circuit 24 reduces VT starting at a time t1.5. The differ-
`ence between dotted line 30 and the solid line represent-
`ing VA—VTin FIG. 5b indicates the amount of reduc-
`tion in VT.
`Capacitor Co starts discharging at time t2. This pro-
`duces a positive VL spike at time t3 according to the
`mechanism described above. Due to the VT reduction
`produced by circuit 24, VA—VL stays above VTduring
`the positive VL spike. Capacitor Co thereby remains
`discharged so as to substantially inhibit any further
`internal supply line voltage bounce. Accordingly, no
`spikes occur in VB, Vc, V1), and V0. At a later time t3,5,
`VT automatically returns to V3.
`The situation in which V1 falls slowly is essentially
`the complement of that shown in FIG. 5b. In the inter-
`val between th and t3_5, circuit 24 increases VT by an
`amount sufficient to prevent spikes from occurring in
`VB, Vc, VD, and V0. If section 26 supplies Vc at the
`same logical value as VB, circuit 24 operates in basically
`the same way to prevent undesired changes in state.
`The dynamic switch of the invention is employed in
`a capacitive-like mode in a preferred embodiment of
`control circuit 28 shown in FIG. 6. Circuit 28 consists
`of (a) an inverter 34 formed with complementary FET’s
`Q4Nand Q41: that produce a voltage V}: inverse to volt-
`age VB, (b) dynamic switches 351v and 35p that respec-
`tively produce voltages VN and Vpin response to volt-
`age V5, and (c) complementary discharge FET’s QSN
`and Q5}: whose gate electrodes receive a voltage Va.
`FET QSN is source-drain connected between the VL
`line and the Q3N gate. FET Q51: is source-drain con-
`nected between the V11 line and the Q31) gate.
`Switch 35N consists of an inverter 36 that provides a
`voltage VFas the inverse of voltage VE, an inverter 38
`that produces voltage VG as the inverse of voltage VF,
`and a transmission gate 40. Inverter 36 is formed with
`complementary FET’s Q6N and Q6p. Inverter 38 is
`formed with complementary FET’s Q7N and Q7p.
`Transmission gate 40 is formed with complementary
`FET’s Q8N and Q8p whose gate electrodes respectively
`receive voltages V): and VG. FET’s Q8N and Q8}: have
`interconnected first source/drain elements connected to
`the Q4N and Q4}: drains and interconnected second
`source/drain elements connected to the Q3N gate. Con-
`sequently, switch 351v is an embodiment of the switch
`version shown in FIG. 2a.
`
`Switch 35p consists of a transmission gate 42 along
`with inverters 36 and 38. Gate 42 consists of comple-
`mentary FET’s Q9N and Q9p arranged with regard to
`the Q3p gate in a manner that is complementary to the
`arrangement of gate 40 with respect to the Q3N gate.
`Switch 35}: is thus an embodiment of the version shown
`in FIG. 2c.
`Circuit 28 in FIG. 6 operates as follows. Assume that
`V]; is initially at VH1; so that FET Q4N is on and FET
`Q41: is off. VFis likewise at V1111. V5 and VG are both at
`VLL. FET Q81vis on, thereby setting VN at VLL. FET’s
`Q3N, QSN, and Q8N are all off.
`When VB drops to VLL, FET Q4Ntums off and FET
`Q4p turns on. V3 starts rising toward VHH. During an
`initial part of the time needed for inverter 36 to drop
`VF down to VLL, positive charge from the V3 line
`flows through FET’s Q41: and Q8N to the Q3N gate. VN
`starts to rise as FET Q8p turns on. Although FET Q8N
`
`Page 11 of 12
`
`5
`
`10
`
`15
`
`20
`
`25
`
`3O
`
`35
`
`45
`
`50
`
`55
`
`65
`
`When inverter 38 finally switches, FET Q8p turns off
`to stop the charging of the Q3N gate. At this point, FET
`Q5Nturns on. It opens a path to the VL line for discharg-
`ing the Q3N gate, causing FET Q3N to turn off. Invert-
`ers 36 and 38 and FET’s Q4N, Q9N, Q9p, and Q5}: oper-
`ate in a similar, complementary manner to enable FET
`Q3}: to turn on briefly when VB later returns to VHH.
`If the transmission delay of inverter 36 or 38 is too
`small to allow enough time to charge the Q3N gate
`and/or the Q31: gate, a further delay element can be
`placed in series with inverter 36 or 38. The delay ele-
`ment might, for example, consist of a pair of inverters in
`series.
`While the invention has been described with refer-
`ence to particular embodiments,
`this description is
`solely for the purpose of illustration and is not to be
`construed as limiting the scope of the invention claimed
`below. For example, junction FET’s could be used
`instead of insulated-gate FET’s. Certain of the enhance-
`ment~mode FET’s could be replaced with depletion-
`mode FET’s. Various modifications and applications
`may thus be made by those skilled in the art Without
`departing from the true scope and spirit of the invention
`as defined by the appended claims.
`I claim:
`1. An electronic circuit comprising (a) a pair of com-
`plementary field-effect transistors (FET’s), each having
`a first source/drain element, a second source/drain
`element, and a gate electrode, the first source/drain
`’ elements coupled together through a first node at which
`a first signal is present, the second source/drain ele-
`ments coupled together through a second node at
`which a second signal is present, both of the first and
`second signals substantially varying between a low
`voltage level and a high voltage level, and (b) an in-
`verter responsive to a third signal at a third node cou-
`pled to the gate electrode of one of the FET’s for pro-
`viding a substantially inverse fourth signal to the gate
`electrode of the other FET, characterized by delay
`means for causing the third signal to continually follow
`the first signal, either directly or inversely, by a speci-
`fied timedelay.
`2. A circuit as in claim 1 characterized in that the
`inverter provides a further time delay such that the
`fourth signal continually follows the first signal, either
`inversely or directly, by the sum of the two delays.
`3. A circuit as in claim 1 characterized in that the
`delay means comprises inverting means coupled be-
`tween the first and third nodes.
`4. A circuit as in claim 3 characterized in that the
`
`inverting means comprises a single inverter or an odd
`number of inverters coupled in series.
`5. A circuit as in claim 3 characterized in that the
`FET’s are enhancement-mode insulated-gate FET’s.
`6. A circuit as in claim 1 characterized in that delay
`means comprises non-inverting buffer means coupled
`between the first and third nodes.
`7. A circuit as in claim 6 characterized in that the
`buffer means comprises an even number of inverters
`coupled in series.
`8. A circuit as in claim 6 characterized in that the
`FET’s are enhancement-mode insulated-gate FET’s.
`
`Page 11 of 12
`
`

`

`9
`9. A circuit as in claim 1 further including circuit
`means coupled to the second node for producing a
`
`4,874,971
`
`10
`ggmprises 1031‘: means for performing a logical opera-
`11. A circuit as in claim 10 characterized in that the
`inverter provides a further time delay such that the
`fourth signal continually follows the first si nal, either
`inversely or directly, by the sum of the tw0gdelays.
`*
`*
`*
`*
`*
`
`further signal that varies in response to the second sig-
`.
`.
`.
`nal as it varies between the low and high voltage levels.
`10. A circuit as in claim 9 wherein the circuit means
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`Page 12 of 12
`
`Page 12 of 12
`
`